JPH05111241A - Dc/dc converter - Google Patents

Abstract

PURPOSE:To obtain an output voltage of an arbitrary value in a charge pump type DC/DC converter using charging/discharging of a capacitor. CONSTITUTION:A variable voltage source 10 outputs a DC voltage of an arbitrary value. When switches 2, 3 are closed and switches 4, 5 are opened, a capacitor 6 is charged by the power source 10. When the switches 2, 3 are opened and the switches 4, 5 are closed, the capacitor 6 is discharged, and a capacitor 7 is charged. The switches 2, 3 and the switches 4, 5 are alternately closed and opened, thereby obtaining an output voltage Vo at one end of the capacitor 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump type DC-DC converter utilizing charge / discharge of a capacitor.

Charge pump type DC-DC converters are used in portable electronic devices such as cordless telephones. However, such portable electronic devices have higher functions, for example, various circuits operating with different power supplies. It is required to be installed. Therefore, it is necessary to improve the power efficiency of the DC-DC converter by generating different voltages corresponding to various circuits and to make the generated voltage of the DC-DC converter highly accurate.

[0003]

2. Description of the Related Art An example of a conventional charge pump type DC-DC converter is shown in FIG. Switches 2 and 3 are connected to both electrodes of the capacitor 6, the switch 2 is connected to the battery 9 via the voltage input terminal 1, and the switch 3 is connected to the ground. Further, switches 4 and 5 are connected to both electrodes of the capacitor 6 in parallel with the switches 2 and 3, respectively, the switch 4 is connected to the ground, and the switch 5 is connected to the voltage output terminal 8. An output capacitor 7 is connected between the voltage output terminal 8 and the ground.

When the switches 2 and 3 are turned on and the switches 4 and 5 are turned off, the battery 9 charges the capacitor 6. Next, when the switches 2 and 3 are turned off and the switches 4 and 5 are turned on, the capacitor 6 is discharged and the capacitor 7 is charged. In this way, the switches 2 and 3 and the switches 4 and 5 are turned on.
A predetermined output voltage Vo can be obtained from the voltage output terminal 8 by alternately repeating turning off. still,
When the voltage value of the battery 9 is V1, the output voltage Vo is “−
V1 ”.

[0005]

However, in the above-mentioned conventional DC-DC converter, since the battery 9 having the voltage value V1 is used as the DC power source, the value of the output voltage Vo becomes a constant value "-V1", which is arbitrary. There is a problem in that it cannot be dealt with even if the output voltage Vo having the voltage value of is required.

The present invention has been made to solve the above problems, and an object thereof is to obtain an output voltage having an arbitrary value. Another object of the present invention is to obtain an output voltage of any desired value with high accuracy.

[0007]

FIG. 1 is a diagram illustrating the principle of one embodiment of the first invention. The charging means 2 and 3 are variable voltage sources 10
The charging means 4 and 5 discharge the capacitor 6 and charge the capacitor 7. The charging means 2, 3 and 4,5 are capacitors 6 and 7 respectively.
Are repeatedly charged to obtain the output voltage Vo at one end of the capacitor 7.

FIG. 2 is an explanatory view of the principle of the second invention. The charging means 2 and 3 charge the capacitor 6 by the DC power source 9, and the charging means 4 and 5 discharge the capacitor 6 and charge the capacitor 7. Each charging means 2, 3 and 4,5
Repeatedly charges each of the capacitors 6 and 7 to generate an output voltage Vo at one end of the capacitor 7. The charging path cutoff means 11 cuts off the charging path of the capacitor 7,
The output voltage detection means 13 detects the output voltage Vo of the capacitor 7 based on the DC reference voltage from the variable voltage source 12,
When the detected output voltage Vo becomes equal to or higher than a predetermined value or lower than a predetermined value, the charging path blocking means 11 is controlled to block the charging path of the capacitor 7.

[0009]

According to the first aspect of the present invention, the charging means 2 and 3 charge the capacitor 6 from the variable voltage source 10, the charging means 4 and 5 discharge the capacitor 6 and charge the capacitor 7, and the capacitor 7 An output voltage Vo is obtained at one end of. Since the variable voltage source 10 is used, the output voltage Vo having an arbitrary value can be obtained by arbitrarily changing the DC voltage of the variable voltage source 10.

According to the second aspect of the invention, the charging means 2 and 3 charge the capacitor 6 from the DC power supply 9, and the charging means 4 and 5 discharge the capacitor 6 and charge the capacitor 7. At this time, the output voltage detecting means 1 is based on the DC reference voltage from the variable voltage source 12.
When the output voltage Vo of the capacitor 7 detected by 3 becomes equal to or more than a predetermined value or less than a predetermined value, the charging path cutoff means 1
1 is controlled and the charging path to the capacitor 7 is cut off.
As a result, the capacitor 7 is no longer charged, and the output voltage Vo of the capacitor 7 is maintained at a predetermined value with high accuracy. Since the variable voltage source 12 that generates the DC reference voltage is used, the output voltage Vo of an arbitrary value can be obtained with high accuracy by arbitrarily changing the DC reference voltage of the variable voltage source 12. Become.

[0011]

[First Embodiment] A first embodiment of a DC-DC converter embodying the first invention will be described below with reference to FIG.

A digital / analog (hereinafter simply referred to as D / A) converter 21 as a variable voltage source is connected to the voltage input terminal 20, and a battery 22 having a voltage value V1 is connected to the D / A converter 21. At the same time, n-bit digital signals D0 to Dn-1 are input from a control circuit (not shown). Then, the D / A converter 21 converts the digital signals D0 to Dn-1 and outputs an output voltage Va satisfying 0 <Va≤V1.

The voltage input terminal 20 has a PMOS transistor (hereinafter, transistor is referred to as Tr) 23 and an NMO.
The STr24 is connected in series, and the source terminal of the NMOSTr24 is connected to the ground. In addition, NMOSTr25 and NMOSTr25 are connected in series to the NMOSTr24.
The output terminal 27 is connected to the source terminal of r26.

One electrode of the capacitor 28 is a PMOST
connected to a node a between r23 and NMOSTr24,
The other electrode is connected to the node b between the NMOS Trs 25 and 26. An output capacitor 29 is connected between the output terminal 27 and the ground.

In this embodiment, the PMOSTr 23 and the NMO are
The STr 25 constitutes a charging means for the capacitor 28, and N
The MOSTrs 24 and 26 form a charging means for the capacitor 29. That is, PMOSTr23 and NMOST
When r25 is on and the NMOS Trs 24 and 26 are off, the capacitor 28 is charged by the output voltage Va of the D / A converter 21, and the PMOS Tr 23 and NM are charged.
When the OSTr 25 is off and the NMOS Trs 24 and 26 are on, the capacitor 28 is discharged and the capacitor 29 is charged. In this way, the PMOSTr
23 and NMOSTr25, and NMOSTr24, 26
By alternately repeating ON and OFF of, a predetermined output voltage Vo (= -Va) is obtained from the voltage output terminal 27.

The oscillator 30 outputs a clock signal CLK to a data flip-flop (hereinafter, flip-flop is referred to as FF) 31 at a predetermined cycle. The clock signal CLK is input to the clock terminal CK of the data FF 31,
An inverted output terminal bar Q is connected to the data terminal D.

Further, the output terminal Q of the data FF 31 has the above N
It is connected to the gate terminal of the MOSTr 25 and also connected to the gate terminal of the PMOSTr 23 via the inverter 32. The inverted output terminal bar Q of the data FF 31 is connected to the gate terminals of the NMOS Trs 24 and 26.

Then, the data FF 31 receives the clock signal C.
Each time LK is input, the output signals of H and L are alternately output from the output terminal Q to output the PMOSTr23 and the NMOST.
The r25 is turned on or off at the same time, and the output signals of L and H are alternately output from the inverting output terminal bar Q to turn off or turn on the NMOS Trs 24 and 26 at the same time.

Next, the operation of the DC-DC converter configured as described above will be described. In the initial state, the capacitor 29 is not charged and the output voltage Vo is 0
It's a bolt.

Now, when the power is turned on, n
When the bit digital signals D0 to Dn-1 are input to the D / A converter 21, the D / A converter 21 outputs 0 <
An output voltage Va that satisfies Va ≦ V1 is output.

When the power is turned on, the data FF 31
Assuming that the output terminal Q and the inverted output terminal Q of L are at L and H, the output terminal Q and the inverted output terminal Q of the data FF 31 become H and L when the pulse of the clock signal CLK is input. As a result, the output of the inverter 32 becomes L level, the PMOSTr 23 and the NMOSTr 25 are turned on, and the NMOSTrs 24 and 26 are turned off.

As a result, a current flows from the D / A converter 21 to the ground via the voltage input terminal 20, the PMOSTr 23, the node a, the capacitor 28, the node b and the NMOSTr 25, and the capacitor 28 is charged.

Next, when a new pulse of the clock signal CLK is input, the output terminal Q and the inverted output terminal bar Q of the data FF 31 become L and H. As a result, the inverter 3
The output of 2 becomes H level, and PMOSTr23 and NM
The OSTr25 is turned off, and the NMOSTr24, 2
6 is turned on.

As a result, the capacitor 29 is connected to the NMOS.
Tr 26, node b, capacitor 28, nodes a and N
A current flows to the ground via the MOSTr 24, and the capacitor 28 is discharged and the capacitor 29 is charged.

Thereafter, each time a new pulse of the clock signal CLK is input, the PMOSTr23 and the NMOSTr2
5 and the ON / OFF of the NMOS Trs 24 and 26 are alternately repeated, and the output voltage Vo having a voltage value of "-Va" is obtained from the voltage output terminal 27.

Thus, in this embodiment, the capacitor 28
D / A converter 21 as a DC power supply for charging
And a DC voltage V of an arbitrary value that satisfies 0 <Va ≦ V1 by a digital signal input to the D / A converter 21.
Since a is generated, the output voltage Vo is changed to "-V
a ”. Therefore, the DC-D of this embodiment
A semiconductor device equipped with a C converter can generate voltages corresponding to various circuits, and the power efficiency of the DC-DC converter can be improved.

[Second Embodiment] Next, a second embodiment of the first invention will be described with reference to FIG. The same components as those in FIG. 3 are designated by the same reference numerals and the description thereof is partially omitted.

In this embodiment, the variable voltage source is a D / A converter 33, an operational amplifier 35, a PNPTr 36 and a pair resistor 3.
Different from the above-mentioned embodiment in that it is provided with 7, 38, the other configurations are the same.

The D / A converter 33 has a voltage value V2 (<
The battery 34 of V1) is connected, and n-bit digital signals D0 to Dn-1 are input from a control circuit (not shown), so that the driving capability is lower than that of the D / A converter 21 in the above embodiment. .. Then, the D / A converter 33 converts the digital signals D0 to Dn-1 to 0 <
A DC voltage Vb that satisfies Vb ≦ V2 is output.

The non-inverting input terminal of the operational amplifier 35 is PNP.
It is connected to a node c between resistors 37 and 38 provided in series between the collector terminal of Tr36 and ground, and PNPTr
The divided voltage Vd obtained by dividing the DC voltage Vc output from 36 by the resistance ratio of the resistors 37 and 38 is input. Further, the inverting input terminal of the operational amplifier 35 is the D / A converter 3
3 is connected to the output terminal and the DC voltage Vb is input. Then, the operational amplifier 35 differentially amplifies the divided voltage Vd and the DC voltage Vb and outputs the output voltage Vo1.

The resistance values of the resistors 37 and 38 are R respectively.
37 and R38, the divided voltage Vd is

[0032]

[Equation 1]

It becomes The emitter terminal of the PNPTr 36 is connected to the battery 22 having the voltage value V1, the collector terminal is connected to the ground via the pair resistors 37 and 38, and is also connected to the voltage input terminal 20. And PNP
The base terminal of Tr36 is connected to the operational amplifier 35 and the output voltage Vo1 is input thereto, and the PNPTr36 is a constant DC voltage V corresponding to the output voltage Vo1 of the operational amplifier 35.
c is output to the voltage input terminal 20.

That is, when the DC voltage Vc of the PNPTr 36 decreases from a certain value, the divided voltage Vd of the resistor 38 also decreases, and when this divided voltage Vd becomes smaller than the DC voltage Vb of the D / A converter 33, the operational amplifier 35. Of the output voltage Vo1 of the above. As a result, the PNPTr 36 shifts to the ON side, the collector current increases, and the DC voltage Vc rises. Then, the DC voltage Vc rises and the divided voltage Vd
Becomes larger than the DC voltage Vb of the D / A converter 33, the output voltage Vo1 of the operational amplifier 35 rises. As a result, the PNPTr 36 shifts to the off side, the collector current decreases, the DC voltage Vc decreases, and the PNPTr 36 decreases.
The DC voltage Vc of is maintained at a constant value.

Also in this embodiment, as in the first embodiment, when the PMOSTr 23 and the NMOSTr 25 are turned on and the NMOSTrs 24 and 26 are turned off, the PNPTr 36 is turned on.
The capacitor 28 is charged by the DC voltage Vc output from the
When 25 is turned off and NMOSTrs 24 and 26 are turned on, the capacitor 28 is discharged and the capacitor 29 is charged. After that, the PMOSTr23 and the NMOSTr25,
The NMOS Trs 24 and 26 are alternately turned on and off, and the output voltage Vo having a voltage value of "-Vc" is obtained from the voltage output terminal 27.

Therefore, according to this embodiment, the digital signals D0 to Dn-1 inputted to the D / A converter 33 are changed to arbitrarily change the DC voltage Vb within the range of 0 <Vb≤V2. Set DC voltage Vc of PNPTr36 to 0 <V
The output voltage Vo can be changed to any value within the range of c ≦ V1.

[Third Embodiment] Next, a third embodiment of the second invention will be described with reference to FIG. The same components as those in FIG. 3 are designated by the same reference numerals and the description thereof is partially omitted.

In this embodiment, the voltage value V is applied to the voltage input terminal 20.
The battery 22 of No. 1 is connected, an NMOSTr39 as a charging path breaking means is connected between the NMOSTr24 and the ground, and its gate terminal is connected to the output voltage detecting circuit 40 as an output voltage detecting means.

The output voltage detection circuit 40 is the comparator 4
1, a D / A converter 42 as a variable voltage source, pair resistors 44 and 45, and a battery 46 having a voltage value V3. A battery 43 having a voltage value V4 is connected to the D / A converter 42, and the control circuit (not shown)
Bit digital signals D0 to Dn-1 are input.
Then, the D / A converter 42 uses the digital signals D0 to D
DC reference voltage Ve for converting n-1 to 0 <Ve ≦ V4
Is to be output.

The resistors 44 and 45 are provided in series between the battery 46 and the voltage output terminal 27, and a difference voltage between the voltage value V3 of the battery 46 and the output voltage Vo is applied to the resistor 44 at the node d between the resistors 44 and 45. , 45 to generate a divided voltage Vf divided by the resistance ratio. That is, when the resistance values of the resistors 44 and 45 are R44 and R45, respectively, the divided voltage Vf is

[0041]

[Equation 2]

It becomes The non-inverting input terminal of the comparator 41 is connected to the node d to receive the divided voltage Vf, and the inverting input terminal is connected to the output terminal of the D / A converter 42 to receive the DC voltage Ve. Then, the comparator 41 outputs an H level control voltage Vo2 when the divided voltage Vf is equal to or higher than the DC voltage Ve, and outputs an L level control voltage Vo2 when the divided voltage Vf is less than the DC voltage Ve.

Next, the operation of the DC-DC converter of this embodiment will be described. Now, with the power turned on,
When the n-bit digital signals D0 to Dn-1 are input to the D / A converter 42, the D / A converter 42 outputs 0.
A DC reference voltage Ve that satisfies <Ve ≦ V4 is output.
Further, by setting the resistance values of the resistors 44 and 45 and the voltage value V3 of the battery 46 so that the divided voltage Vf takes a value larger than the DC reference voltage Ve when the capacitor 29 is not charged to the predetermined voltage. The control voltage Vo2 of the comparator 41 becomes H level, the NMOSTr 39 is in the ON state, and the charging path to the capacitor 29 is formed.

Then, when the pulse of the clock signal CLK is input and the output terminal Q and the inverted output terminal Q of the data FF 31 become H and L, the PMOSTr 23 and NMO.
The STr 25 is turned on and the NMOS Trs 24 and 26 are turned off. This allows the battery 22 to be connected to the voltage input terminal 20, PM
A current flows to the ground via the OSTr 23, the node a, the capacitor 28, the node b, and the NMOSTr 25, and the capacitor 28 is charged.

Next, when a new pulse of the clock signal CLK is input and the output terminal Q and the inverted output terminal Q of the data FF 31 become L and H, the PMOSTr 23 and N are turned on.
The MOSTr 25 is turned off and the NMOSTrs 24 and 26 are turned on. As a result, the capacitor 29 to the NMOSTr2
6, node b, capacitor 28, node a, NMOST
A current flows to the ground via r24 and the NMOSTr 39, and the capacitor 28 is discharged and the capacitor 29 is charged.

Thereafter, each time a new pulse of the clock signal CLK is input, the PMOSTr23 and the NMOSTr2 are
5 and the NMOS Trs 24 and 26 are alternately turned on and off, the capacitor 29 is gradually charged, and the output voltage Vo of the voltage output terminal 27 decreases. If the capacitor 29 is not charged to the predetermined voltage, the output voltage Vo is still high, the divided voltage Vf becomes equal to or higher than the DC reference voltage Ve, the control voltage Vo2 of the comparator 41 is maintained at the H level, and N
The MOSTr 39 is turned on and the charging path remains formed.

When the output voltage Vo drops to a predetermined voltage and the divided voltage Vf becomes less than the DC reference voltage Ve,
The control voltage Vo2 of the comparator 41 becomes L level, the NMOSTr 39 is turned off, and the charging path to the capacitor 29 is cut off. As a result, the capacitor 29 is no longer charged and the output voltage Vo is stabilized at that level.

Therefore, according to this embodiment, the digital signals D0 to Dn-1 input to the D / A converter 42 are changed to set the DC reference voltage Ve input to the comparator 41 to 0 <.
By arbitrarily changing within the range of Ve ≦ V4, the divided voltage Vf for switching the level of the control voltage Vo2, that is, the output voltage Vo can be changed with high accuracy to a desired arbitrary value.

[Fourth Embodiment] FIG. 6 shows a fourth embodiment of the second invention. The output voltage detection circuit 47 of this embodiment uses a variable resistor 48 connected in series with a battery 46 as a variable voltage source instead of the D / A converter 42 in the output voltage detection circuit 40 of the third embodiment. The output voltage of the variable resistor 48 is input to the inverting input terminal of the comparator 41 as a DC reference voltage.

Also in this embodiment, the variable voltage source can be simplified in addition to the same operation and effect as those of the third embodiment. [Fifth Embodiment] FIG. 7 shows a fifth embodiment of the first invention, which is a variable voltage source 49 connected to a voltage input terminal 20.
Is a D / A converter or the like, and outputs a DC voltage Va whose voltage value is variable. Switches 50 and 51 are connected to both electrodes of the capacitor 28, the switch 50 is connected to the voltage input terminal 20, and the switch 51 is connected to the ground.

Further, on both electrodes of the capacitor 28, switches 52 and 53 are arranged in parallel with the respective switches 50 and 51.
Are connected, and the switch 52 is connected to ground.
A capacitor 54 is connected between the switch 53 and ground.

A switch 5 is provided on both electrodes of the capacitor 57.
5, 56 are connected, and the switch 55 is the voltage input terminal 20.
, And the switch 56 is connected to the switch 53.

Further, on both electrodes of the capacitor 57, switches 58 and 59 are arranged in parallel with the respective switches 55 and 56.
Are connected, and the switch 58 is connected to ground. The switch 59 is connected to the voltage output terminal 27. or,
An output capacitor 29 is connected between the voltage output terminal 27 and the ground.

In this embodiment, first, the switches 50 and 51 are
When only this is turned on, the variable voltage source 49 charges the capacitor 28, and the charging voltage of the capacitor 28 becomes Va. Next, when the switches 50 and 51 are turned off and the switches 52 and 53 are turned on, the upper electrode of the capacitor 28 is connected to the ground, and the voltage of the node A becomes "-V".
a ”. Subsequently, when the switches 52 and 53 are turned off and the switches 55 and 56 are turned on, the potentials of the upper and lower electrodes of the capacitor 57 become Va and “−Va”, respectively, and the charging voltage of the capacitor 57 becomes 2Va.

When the switches 55 and 56 are turned off and the switches 58 and 59 are turned on, the upper electrode of the capacitor 57 is connected to the ground, and the voltage of the node B becomes "-2".
Va ”.

Therefore, the output voltage Vo having a voltage value of "-2Va" (Va is an arbitrary value) is obtained from the voltage output terminal 27. [Sixth Embodiment] FIG. 8 shows a sixth embodiment of the first invention. The DC-DC converter of the present embodiment differs from the fifth embodiment shown in FIG. 7 in that the switch 58 is connected to the node A.

In this embodiment, when the switches 50 and 51 are turned on, the variable voltage source 49 charges the capacitor 28, and the charging voltage of the capacitor 28 becomes Va. Next, the switches 50 and 51 are turned off, and the switches 52 and 5
When 3 is turned on, the upper electrode of the capacitor 28 is connected to the ground, and the voltage of the node A becomes "-Va".
Subsequently, the switches 52 and 53 are turned off, and the switches 55 and 56 are turned on.
When is turned on, the potentials of the upper and lower electrodes of the capacitor 57 become Va and "-Va", respectively, and the charging voltage of the capacitor 57 becomes 2Va.

When the switches 55 and 56 are turned off and the switches 58 and 59 are turned on, the upper electrode of the capacitor 57 is connected to the node A having the voltage value "-Va" at the ground, and the voltage of the node B becomes " -3Va ".

Therefore, the output voltage Vo having a voltage value of "-3Va" (Va is an arbitrary value) is obtained from the voltage output terminal 27. [Seventh Embodiment] FIG. 9 shows a seventh embodiment of the first invention, in which switches 50 and 5 are provided on both electrodes of the capacitor 28.
1 is connected, the switch 50 is connected to the variable voltage source 49 via the voltage input terminal 20, and the switch 51 is connected to the ground. The switches 58 and 59 are the switches 5 described above.
The switch 58 is connected to the voltage output terminal 27, and the switch 59 is connected to the variable voltage source 49.

In the present embodiment, when only the switches 50 and 51 are turned on, the variable voltage source 49 charges the capacitor 28, and the charging voltage of the capacitor 28 becomes Va. Next, the switches 50 and 51 are turned off, and the switch 58 and
When 59 is turned on, the lower electrode of the capacitor 28 is connected to the variable voltage source 49 having the voltage value Va, and the voltage of the node C becomes 2Va.

Therefore, according to this embodiment, the voltage output terminal 2
Output voltage V with a voltage value of 2Va from 7 (Va is an arbitrary value)
o is obtained. In the third embodiment shown in FIG. 5, the divided voltage Vf obtained by dividing the difference voltage between the voltage value V3 of the battery 46 and the output voltage Vo by the resistance ratio of the resistors 44 and 45 is applied to the non-inverting input terminal of the comparator 41. The DC reference voltage Ve of the D / A converter 42 was input to the inverting input terminal, but the DC reference voltage Ve of the D / A converter 42 was input to the non-inverting input terminal, and the divided voltage Vf was input to the non-inverting input terminal. May be input.

[0062]

As described above in detail, according to the first aspect of the present invention, an output voltage having an arbitrary value can be obtained.

Further, according to the second invention, it is possible to obtain an output voltage having a desired arbitrary value with high accuracy.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the first invention.

FIG. 2 is a diagram illustrating the principle of the second invention.

FIG. 3 is a circuit diagram showing a first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a second embodiment.

FIG. 5 is a circuit diagram showing a third embodiment.

FIG. 6 is a circuit diagram showing a fourth embodiment.

FIG. 7 is a circuit diagram showing a fifth embodiment.

FIG. 8 is a circuit diagram showing a sixth embodiment.

FIG. 9 is a circuit diagram showing a seventh embodiment.

FIG. 10 is a circuit diagram showing a conventional DC-DC converter.

[Explanation of symbols]

 2,3,4,5 Charge means 6,7 Capacitor 9 DC power source 10,12 Variable voltage source 11 Charging path interruption means 13 Output voltage detection means Vo Output voltage

Claims (2)

[Claims] 1. A DC power supply (10), a plurality of capacitors (6, 7), and a capacitor provided before each of the capacitors (6, 7) for discharging and charging the capacitor in the preceding stage. Charging means (2,
3), (4, 5), each charging means (2, 3),
The output voltage (Vo) is obtained at one end of the final stage capacitor (7) by sequentially repeating charging and discharging of each stage capacitor by the DC power supply or the charging voltage of the previous stage capacitor from (4, 5) from the first stage capacitor. A DC-DC converter configured as described above, wherein the DC power supply (10) is a variable voltage source. 2. A DC power supply (9), a plurality of capacitors (6, 7), and a capacitor provided in correspondence with each capacitor (6, 7) respectively for discharging a capacitor in a preceding stage of the capacitor and charging the capacitor. Charging means (2,
3), (4, 5), each charging means (2, 3),
The output voltage (Vo) is obtained at one end of the final stage capacitor (7) by sequentially repeating charging and discharging of each stage capacitor by the DC power supply or the charging voltage of the previous stage capacitor from (4, 5) from the first stage capacitor. In the DC-DC converter configured as described above, a charging path cutoff means (11) for cutting off the charging path of the final stage capacitor (7), and a variable voltage source (1) for generating a DC reference voltage whose voltage value is variable
2) and the output voltage (Vo) of the final stage capacitor (7) is detected based on the DC reference voltage from the variable voltage source (12), and the detected output voltage (Vo) is equal to or higher than a predetermined value or lower than a predetermined value. DC-, which is provided with output voltage detection means (13) for controlling the charging path cut-off means (11) so that the charging path of the final stage capacitor (7) is cut off when
DC converter.