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JPH0488477U - - Google Patents

Info

Publication number
JPH0488477U
JPH0488477U JP40302290U JP40302290U JPH0488477U JP H0488477 U JPH0488477 U JP H0488477U JP 40302290 U JP40302290 U JP 40302290U JP 40302290 U JP40302290 U JP 40302290U JP H0488477 U JPH0488477 U JP H0488477U
Authority
JP
Japan
Prior art keywords
switching semiconductor
semiconductor element
terminal
level input
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP40302290U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP40302290U priority Critical patent/JPH0488477U/ja
Publication of JPH0488477U publication Critical patent/JPH0488477U/ja
Withdrawn legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を説明するための図
、第２図は本考案の他の一実施例を説明するため
の図、第３図は従来のスイツチング回路を説明す
るための図である。 １…高レベルの入力端子、１′…低レベルの入
力端子、２…発振回路、３…駆動トランス、４…
第１のスイツチング半導体素子、５…第２のスイ
ツチング半導体素子、６…主トランス、７〜１０
…ダイオード、１１…インダクタ、１２…コンデ
ンサ、１３…負荷、１４…線間容量。 FIG. 1 is a diagram for explaining one embodiment of the present invention, FIG. 2 is a diagram for explaining another embodiment of the present invention, and FIG. 3 is a diagram for explaining a conventional switching circuit. It is. 1...High level input terminal, 1'...Low level input terminal, 2...Oscillation circuit, 3...Drive transformer, 4...
First switching semiconductor element, 5... Second switching semiconductor element, 6... Main transformer, 7-10
...Diode, 11...Inductor, 12...Capacitor, 13...Load, 14...Line capacitance.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 主トランスの入力巻線の一方の端子を第１のス
イツチング半導体素子を介して高レベルの入力端
子に接続し、他方の端子を第２のスイツチング半
導体素子を介して低レベルの入力端子に接続して
なるスイツチング回路において、上記第１のスイ
ツチング半導体素子をＰ型のスイツチング半導体
素子とし、上記第２のスイツチング半導体素子を
Ｎ型のスイツチング半導体素子としたことを特徴
とするスイツチング回路。 One terminal of the input winding of the main transformer is connected to a high-level input terminal through a first switching semiconductor device, and the other terminal is connected to a low-level input terminal through a second switching semiconductor device. A switching circuit characterized in that the first switching semiconductor element is a P-type switching semiconductor element, and the second switching semiconductor element is an N-type switching semiconductor element.
JP40302290U 1990-12-10 1990-12-10 Withdrawn JPH0488477U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP40302290U JPH0488477U (en) 1990-12-10 1990-12-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP40302290U JPH0488477U (en) 1990-12-10 1990-12-10

Publications (1)

Publication Number Publication Date
JPH0488477U true JPH0488477U (en) 1992-07-31

Family

ID=31880864

Family Applications (1)

Application Number Title Priority Date Filing Date
JP40302290U Withdrawn JPH0488477U (en) 1990-12-10 1990-12-10

Country Status (1)

Country Link
JP (1) JPH0488477U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016074530A (en) * 2014-10-08 2016-05-12 東芝ロジスティクス株式会社 Cargo hanging cover

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016074530A (en) * 2014-10-08 2016-05-12 東芝ロジスティクス株式会社 Cargo hanging cover

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19950518