JPH048707Y2 - - Google Patents

Description

[Detailed explanation of the idea] [Technical field of invention] The present invention relates to a timing signal generation circuit.

[Prior art and its problems] In recent years, liquid crystal television receivers that use a liquid crystal display panel in the display section have been put into practical use as small portable television receivers. In this liquid crystal television receiver, a received video signal is A/D converted by an A/D conversion circuit, and thereafter is treated as a digital signal. The digital circuit that processes the digital signal requires various timing signals including sampling pulses for A/D conversion.
Preferably, this timing signal is synchronized with the horizontal synchronization signal. For this reason, conventionally PLL
(Phase-Locked Loop) circuit is used to obtain various timing signals for digital circuits using the horizontal synchronization signal as a reference. The above PLL circuit includes a phase comparator to which a horizontal synchronizing signal is input, a voltage controlled oscillator connected to this phase comparator via a low-pass filter and outputting a predetermined frequency signal, and a voltage controlled oscillator that outputs a predetermined frequency signal. /N and inputs the signal to the phase comparator as a comparison signal.
When configuring a PLL circuit as described above, an analog phase comparator or a digital phase comparator is generally used as the phase comparator. However, when a PLL circuit is constructed using an analog phase comparator or a digital comparator as described above, there is no stability against input signal noise, and especially in places with a weak electric field, there is a lot of noise and unstable horizontal In the case of a synchronization signal, there was a problem that the timing signal could not be stably generated and the image would be distorted.

[Purpose of the invention] The present invention was developed in view of the above points, and is capable of generating a stable timing signal even when a noisy and unstable horizontal synchronization signal is given in a weak electric field. The purpose of this invention is to provide a timing signal generation circuit for LCD television receivers, etc.

[Main points of the invention] This invention is the first method using an analog phase comparator.
A second circuit using a PLL circuit and a digital phase comparator
The first PLL circuit performs automatic frequency control, and the second PLL circuit performs frequency multiplication to generate a stable timing signal.

[Embodiment of the invention] An embodiment of the invention will be described below with reference to the drawings. First, the overall circuit configuration will be explained with reference to FIG. In FIG. 1, 10 is a PLL circuit for automatic frequency control, and 20 is a PLL circuit for frequency multiplication. The automatic frequency control PLL circuit 10 is
An analog phase comparator 11 to which a horizontal synchronization signal from a television synchronization separation circuit (not shown) is input, and a low-pass filter 12 is connected to this analog phase comparator 11.
The output of the voltage controlled oscillator 13 is connected to the analog phase comparator 11 as a comparison signal, and is connected to the analog phase comparator 11 as a comparison signal. The signal is sent to the PLL circuit 20 for use. This PLL circuit 20 includes a digital phase comparator 21 to which the clock pulse from the voltage controlled oscillator 13 is input, and is connected to this digital phase comparator 21 via a low-pass filter 22, with a timing N times that of the horizontal synchronizing signal. A voltage controlled oscillator 23 that generates a signal and outputs it to other circuits, and a frequency divider 24 that divides the output signal of this voltage controlled oscillator 23 into 1/N and outputs it as a comparison signal to the digital phase comparator 21. It is made up of

The analog phase comparator 11 is constructed as shown in FIG. In FIG. 2, reference numeral 31 denotes an input terminal to which a horizontal synchronizing signal from a television synchronization separation circuit is input, and this input terminal 31 is connected to the base of a transistor 33 via a resistor 32. The emitter of this transistor 33 is grounded via a resistor 34, and the collector is commonly connected to the emitters of transistors 35 and 36.
A comparison signal from the voltage controlled oscillator 13 is input to the base of the transistor 35 via a time constant circuit consisting of a resistor 37 and capacitors 38 and 39. Further, the transistors 35, 3
A predetermined voltage is applied to the base of 6 from a battery 40 via resistors 41 and 42. The collector of the transistor 35 is supplied with Vcc power through the emitter and base of the transistor 43, and the collector of the transistor 36 is supplied with the Vcc power through the emitter and base of the transistor 43.
Vcc power is supplied through the bases and collectors of transistors 44 and 45 in series. in this case,
The bases of the transistors 43 and 44 are connected together to the collector of the transistor 44. Also,
The base of the transistor 45 is connected to the transistor 4.
3 collector output voltages are supplied. Then, a signal taken out from the collector of the transistor 36 is sent to the next stage low-pass filter 12 as an output signal of the analog phase comparator 11.

Further, the digital phase comparator 21 in the frequency multiplication PLL circuit 20 is configured as shown in FIG. In Figure 3, 51 is the above
This is an input terminal to which the output signal of the PLL circuit 10 is input, and is connected to an input terminal of a NAND circuit 53 via an inverter 52. The output of this NAND circuit 53 is input as a set signal to a latch circuit 54 consisting of NAND circuits 54a and 54b, and is also input to NAND circuits 55 and 56. The output of the latch circuit 54 is further input to the NAND circuits 55 and 56. Further, 57 is an input terminal to which the frequency-divided signal from the frequency divider 24 is input, and this input terminal 57 is connected to a NAND circuit 58 . The output of this NAND circuit (circuit) 58 is a NAND circuit 59a,
The signal is input as a set signal to a latch circuit 59 consisting of a latch circuit 59b, and is also input to NAND circuits 55 and 60. The NAND circuits 55 and 60 are further input to a latch circuit 59. The output of the NAND circuit 55 is input to the latch circuits 54 and 59 as a reset signal, and is also input to the NAND circuits 56 and 60. The output of the NAND circuit 56 is input to the NAND circuit 53 and also to the gate of an N-channel MOS transistor 61 via an inverter 61. Further, the output of the NAND circuit 60 is input to the NAND circuit 58 and to the gate of the P-channel MOS transistor 63. The above MOS transistor 63,
62 is provided in series between the Vcc power supply and ground, and the output signal of the commonly connected drain electrodes is sent to the next stage low-pass filter 22 as the output of the digital phase comparator 21.

Next, the operation of the above embodiment will be explained with reference to the timing chart of FIG. The automatic frequency control PLL circuit 10 in FIG. 1 receives a horizontal synchronization signal from the television synchronization separation circuit, but noises N1 and N2 are present in this horizontal synchronization signal as shown in FIG. 4a. shall be included.
Therefore, the analog phase comparator 11 shown in FIG.
The pulse signal shown in FIG. 4e outputted from the voltage controlled oscillator 13 is input as a comparison signal, and this pulse signal
The signal is converted into a sawtooth wave signal as shown in FIG. 4b by time constant circuits 8 and 39, and is input to the transistor 35. Since the horizontal synchronization signal sent from the synchronization separation circuit is input to the transistor 33 through the input terminal 31, the transistor 33 is turned on while the horizontal synchronization signal is applied, and as shown in FIG. As shown in FIG. 3, a portion of the sawtooth wave signal input to the transistor 35 is taken out as an output signal via the transistor 36. In this case, the noise N1 mixed in the horizontal synchronization signal,
Since transistor 33 is turned on by N2,
Depending on the input timing, a part of the sawtooth wave signal is extracted as an output signal as shown in FIG. 4c. As described above, the analog phase comparator 11 compares the phase of the signal input to the input terminal 31 with the pulse signal from the voltage controlled oscillator 13,
A signal corresponding to the phase difference is output. and,
The signal output from the analog phase comparator 11 is sent to a low-pass filter 12, where only the low-frequency component is extracted and becomes a control signal for the voltage controlled oscillator 13, as shown in FIG. Through the above series of operations, a noise-free horizontal synchronization signal is obtained from a noise-containing horizontal synchronization signal, and it is used for frequency multiplication.
The signal is sent to the digital phase comparator 21 of the PLL circuit 20. This digital phase comparator 21 receives a pulse signal from the voltage controlled oscillator 13 from the inverter 52.
is converted into a negative pulse signal by NAND circuit 5
3 and the frequency divider 2 shown in FIG.
A negative pulse signal having the same frequency as the horizontal synchronizing signal output from 4 is input to the NAND circuit 58. Therefore, between each pulse signal, the NAND circuit 5
The signal level input to 3 and 58 is high level,
In other words, it is "1". Further, at this time, "1" signals are output from the NAND circuits 56 and 60 and input to the NAND circuits 53 and 58. Therefore, the outputs of the NAND circuits 53 and 58 become "0", and the outputs of the NAND circuits 56 and 60 are held in the "1" state. Further, when the outputs of the NAND circuits 53 and 58 are "0", a "1" signal is output from the NAND circuits 54a and 59a and input to the NAND circuit 55. As described above, when the outputs of the NAND circuits 56 and 60 are both “1”, the transistors 62 and
63 is in an off state. Therefore, when the pulse signal from the voltage controlled oscillator 13 and the divided output of the frequency divider 24 are equal in frequency and phase, the pulse signal causes the outputs of the NAND circuits 53 and 58 to simultaneously " Since it changes from "0" to "1", the input of the NAND circuit 55 becomes all "1" and its output becomes "0",
The outputs of the NAND circuits 56 and 60 are held in the "1" state. Therefore, while the output signal of the voltage controlled oscillator 13 and the frequency-divided output of the frequency divider 24 are in phase, the transistors 62 and 63 are kept in the off state, and the output of the digital phase comparator 21 does not change at all. do not. If there is a phase shift between the output signal of the voltage controlled oscillator 13 and the output signal of the frequency divider 24 in this state, the NAND circuits 56 and 60
The output level of transistors 62 and 63 changes.
is controlled on and off. The signals output from the drain electrodes of the transistors 62 and 63 are taken out as the output signal of the digital phase comparator 21 and sent to the voltage controlled oscillator 23 via the low-pass filter 22. This controls the oscillation frequency of the voltage controlled oscillator 23. In this case, the voltage controlled oscillator 13 outputs a horizontal synchronization signal containing almost no noise, as described above.
The output of the digital phase comparator 21 hardly changes as shown in FIG. 4f. Therefore, the output of the low-pass filter 22 is a signal that is completely unaffected by noise, and the output from the voltage controlled oscillator 23 is the fourth signal.
As shown in Figure h, a timing signal obtained by multiplying the horizontal synchronization signal by N is stably output.

[Effects of the invention] As detailed above, according to the invention, the first PLL circuit using an analog phase comparator and the second PLL circuit using a digital phase comparator are combined, The second PLL circuit performs automatic frequency control, and the second PLL circuit performs frequency multiplication to generate a stable timing signal, so noisy and unstable horizontal synchronization signals are generated in locations with weak electric fields. Therefore, it is possible to provide a timing signal generation circuit that can generate a stable timing signal even when the timing signal is changed.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; FIG. 1 is a block diagram showing the overall schematic configuration, FIG. 2 is a circuit diagram showing details of the analog phase comparator in FIG. 1, and FIG. 1 is a circuit diagram showing details of the digital phase comparator, and FIG. 4 is a timing chart for explaining the operation. 10... PLL circuit for automatic frequency control, 11...
... Analog phase comparator, 12 ... Low pass filter, 13 ... Voltage controlled oscillator, 20 ... PLL circuit for frequency multiplication, 21 ... Digital phase comparator,
22...Low pass filter, 23...Voltage controlled oscillator, 24...Frequency divider.

Claims (1)

[Scope of utility model registration request] The first is configured using an analog phase comparator and receives a horizontal synchronization signal separated from the video signal.
A second PLL circuit is configured using a PLL circuit and a digital phase comparator and receives the output signal of the first PLL circuit, and the first PLL circuit performs automatic frequency control, and the second PLL circuit performs automatic frequency control. 1. A timing signal generation circuit comprising means for frequency multiplication using a PLL circuit.