JPH0486117A - Cyclic digital filter - Google Patents

Abstract

PURPOSE:To utilize an existing general-purpose memory cell for the filter by providing a shift register to the filter to use it for reset control of an FIFO memory. CONSTITUTION:A horizontal synchronizing pulse HD is inputted to a shift register 7 to generate a signal delayed by a period equivalent to two stages of D flip-flops and the signal is used for reset control of an FIFO memory 4. When the FIFO memory 4 is used as a 1H delay line and the FIFO memory 4 is accessed by two clocks faster by the reset control, the delay in the digital filter is formed to be 1H. Thus, the cyclic digital filter in which the delay time is matched is realized by using the horizontal synchronizing pulse HD for a read set of the FIFO memory and using a delayed synchronizing signal for write reset.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a recursive digital filter used in a video signal processing device or the like constructed using a FIFO memory.

[Conventional technology]

Conventionally, a recursive digital filter configured using a FIFO memory takes into consideration the access time of the FIFO memory and the delay time of the arithmetic unit, etc., and as shown in FIG.
D-type flip-flops 3.5 are used on the input and output sides of the IFO memory 4 to match data delays. In FIG. 3, ``■'' indicates an input terminal for a video signal, 2 indicates an arithmetic unit for calculating a human-powered video signal and a memory output signal, and 6 indicates a reset circuit for the FIFO memory 4, which will be described later.

[Problem to be solved by the invention]

However, as shown in FIG. 3, when a recursive digital filter using FIFO memory is configured to match the delay using a D-type flip-flop tab 3.5, as shown in FIG. FIFO memory 4
It is necessary to provide a reset circuit 6 for the FIFO memory 4 so that the delay time is one cycle of the video signal using the D-type flip-flop 13.5. Furthermore, if the reset circuit 6 is monolithic with the FIFO memory 4, a set circuit is added, so although it is not necessary to delete memory cells equivalent to a D type flip-flop, a physical space is required.

The present invention has been made to solve the above-mentioned problems in conventional recursive digital filters, and eliminates the need to incorporate a large control circuit such as a reset circuit for correcting the characteristics specific to recursive digital filters. An object of the present invention is to provide a recursive digital filter that can use existing memory cells for general purpose even when monolithic.

(Means and Effects for Solving the Problems) In order to solve the above problems, the present invention provides a recursive digital filter having a summer resistor, a FIFO memory, and a D-type flip-flop, which includes at least one shift register. ,
The shift register is configured to be used for the FIFO memory input control.

In the recursive digital filter configured in this way, the F
By controlling the IFO memory, it is possible to process one cycle of the video signal without changing it.

Also, when the shift register is monolithically integrated with the FIFO memory, if the shift register is incorporated in the reset signal system of the FIFO memory in advance, it is possible to realize a monolithic cyclic digital filter with a slight wiring change.

[Example] Next, an example will be described. FIG. 1 is a block diagram showing an embodiment of a recursive digital filter according to the present invention. This embodiment uses a horizontal synchronization pulse HD as a synchronization signal.
This is an example of a configuration of a recursive digital filter using line-to-line calculations. In the figure, 1 is a video signal input terminal to the digital filter, 2 is a demultiplexer that performs f4X on the input video signal and the FIFO memory output signal, and 3 and 5 are output propagation delay times of the demultiplexer 2 and FIFO memory 4. This is a D type flip-flop for correction. Note that 7 is a shift register to be described later.

In the recursive digital filter configured as described above, the input video signal is input to the video signal input terminal l of the digital filter in synchronization with the horizontal synchronizing pulse HD, and the input video signal is input to the video signal input terminal l of the digital filter.
It is transferred to the FIFO memory 4 via the D-type flip-flop 3, but two stages of D-type flip-flops 3 and 5 are used in the digital filter.
If the IFO memory 4 is used as it is as an IH delay line, the delay in the digital filter will be IH+20 (D: delay time of a D type flip-flop), and line interleaving will not be possible.

Therefore, in the present invention, the shift register 7 is arranged,
A horizontal synchronizing pulse) (D) is input to this shift register 7, and as shown in FIG.
It is configured to perform reset control of the O memory 4.

In the case of this embodiment, when the FIFO memory 4 is used as an IH delay line, it can be interpreted that the data appears on the output line 8 with a delay of two flip-flop stages. If accessed earlier, the delay within the digital filter can be reduced to IH.

Therefore, by using the horizontal synchronization pulse HD as the read center of the FIFO memory and the delayed synchronization signal HD' for the write reset, it is possible to construct a recursive digital filter with matched delays.

Furthermore, by installing a shift register in advance in the FIFO memory signal system, a monolithic recursive digital filter can be easily constructed with a slight wiring change.

Although the above embodiment has been described assuming that the FIFO memory is used as an IH line memory, the present invention can also be applied to a digital filter using a field memory.

〔Effect of the invention〕

As described above based on the embodiments, according to the present invention, the shift register is provided and configured to be used for the FIFO memory cent control, so there is no need for a large-scale separate configuration or a cent control circuit. A recursive digital filter can be easily constructed. Furthermore, by incorporating the shift register in advance into the reset signal system of the FIFO memory, a monolithic cyclic digital filter can be realized with a slight wiring change.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a recursive digital filter according to the present invention, FIG. 2 is a timing chart for explaining its operation, and FIG. 3 is a diagram of a conventional recursive digital filter. FIG. 4, a block configuration diagram showing a configuration example, is a timing chart for explaining the operation. In the figure, numeral numeral numeral ``input terminal'' for the video signal, numeral 2 arithmetic unit, numeral 3
．． 5 is a D type flip-flop, 4 is a FIFO memory, 6 is a reset circuit, and 7 is a shift register. Patent applicant: Olympus Optical Industry Co., Ltd. Figure 1 Figure 2 D

Claims (1)

[Claims] 1. A cyclic digital filter having an arithmetic unit, a FIFO memory, and a D-type flip-flop, characterized in that it includes at least one shift register, and the shift register is used for reset control of the FIFO memory. A cyclic digital filter. 2. The recursive digital filter according to claim 1, wherein the shift register is integrated into a reset signal system of the FIFO memory.