JPH0486022A - Pulse counting and reading circuit - Google Patents

Abstract

PURPOSE:To prevent a hardware from increasing by executing reading and resetting to the low-order digit binary counter of (m) bits and a one bit register. CONSTITUTION:A CPU 5 selects the output (c) of a counter 2 for high-order digit and fetches the value and just after that, the counter 2 for high-order digit is reset while including a one bit register 3 for carry detection of a counter 1 for low-order digit. Next, according to a selective signal (d), the CPU 5 switches a selector 4 and reads the output of the counter 1 for low-order digit and the value of the one bit register 3 for carry detection of this counter. In this case, when a digit is carried, the CPU 5 adds the digit to the counted value of the first read high-order digit and therefore, the digit is counted up during the two times of read time. Thus, exact counting can be executed without fail even when the digit is carried.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a pulse counting readout circuit, and its application to an online performance monitoring function of a patented communication device.

[Conventional technology]

In order to monitor the data transmission quality between communication devices, CR
C (Cyclic Redundancy Check
), etc., and the results are sent to the upper CPU (Central Processor).
There is an online pulse counting readout circuit that reads out periodically. In such a circuit, in order to collect accurate data, it is necessary to read data from the CPLI at exactly equal intervals and to sample and collect data at one time.

In a conventional online pulse count readout circuit, if the number of bits of the count is larger than the number of bits that can be read at one time, it is necessary to read the upper and lower digits twice or more.

An example of such a pulse counting readout circuit is shown in FIG. In Figure 2, l is an m-bit counter for lower digits (
CNT), 2 is a bit counter for the upper digits, 6 is a latch register (LATCH), and 4 is a selector circuit (SE
L), 5 is a CPU.

In such a pulse counting readout circuit, a launch register 6 is connected to the outputs of the counting counters 1 and 2 in order to guarantee the conditions for sampling data at one time as described above. Then, at regular intervals, all bits of the counter output are latched using the latch clock h from the CPU 5 (
After sampling the data), the CPU 5 controls the data bus selector circuit 4 again and reads the data several times.

[Problem to be solved by the invention]

This conventional pulse counting readout circuit necessarily requires a latch circuit, and has the disadvantage that the number of registers increases by the number of bits of the counter. Generally, one device usually has a different counting circuit for each type of error, and in this case, registers occupy a fairly large proportion of the hardware, which is one reason for the increase in hardware.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pulse counting readout circuit that eliminates such drawbacks and prevents an increase in hardware.

[Means for Solving the Problems] The present invention provides an (m+k) bit pulse counting and reading circuit that constantly counts randomly arriving pulses and reads out a count value at regular intervals. A binary counter for lower digits with bit reset, a binary counter for upper digits with bit reset to count the output from this binary counter for lower digits, and a 1-bit reset to detect a carry of the binary counter for lower digits. counting means that reads a k-bit upper-digit binary counter, resets the upper-digit binary counter and 1-bit register, and reads and resets an m-bit lower-digit binary counter and 1-bit register; It is characterized by having the following.

In the present invention described above, the counting means sends out the value of the binary counter for upper digits or the value of the binary counter for lower digits and the 1-bit register as a count value by the selection signal, and sends out the value of the binary counter for upper digits and the value of the binary counter for lower digits and the 1-bit register by the reset signal. It has a selector that resets a 1-bit register and resets a binary counter for lower digits, and a processing section that sends a selection signal and a reset signal to this selector and reads the count value from this selector.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. This embodiment is an (m+k)-bit pulse counting/reading circuit that constantly counts randomly arriving pulses and reads out the count value at fixed time intervals, and is an m-bit binary counter (CNT) for lower digits with reset. ] and k
Upper digit binary counter with bit reset (CN
T) 2, a 1-bit reset register (REG) 3 that detects the carry of lower digit binary counter 1, reading of k-bit upper digit binary counter 2, and resetting this counter 2 and 1-bit register 3. A selector circuit (SEL) 4 reads out and resets the m-bit lower digit binary counter + 1-bit register, and a selection signal d reads the value of (m+1) bits or 2 bits from the selector circuit 4 and resets the m-bit lower digit binary counter + 1-bit register. The CPU 5 sends the signal e to the selector circuit 4.

In such a pulse counting readout circuit, a randomly arriving pulse train (PULSE) a is connected to the clock input terminal CK of the counter 1 for lower digits, and this counter 1
The most significant bit CA is connected to the clock input terminal CK of the upper digit counter 2 and the clock input terminal CK of the 1 via 1□ register 3 for carry detection. The 1-bit register 3 is reset at the same time as the high-order digit counter 2. Furthermore, a data bus b of (m+1) bits which combines the output of the lower digit counter 1 and the output Q of the 1-bit register 3;
A data bus C of the output bits of the second-digit counter 2 is connected to a data bus selector circuit 4. It is assumed that the CPU 5 can read each value by switching the data bus using the selection signal d from the CPU 5.

Further, by selecting the counter reset signal 3 from the CPU 5 by the selector circuit 4, either the counter reset signal f for the lower digits or the reset signal g for the counter 2 and 1-bit register 3 for the upper digits can be used. do.

Next, the operation of this embodiment will be explained using an example in which a (m, -1-k) bit counter value is read.

First, the CPU 5 selects the output C of the high-order digit counter 2.
is selected and the value is taken in, and immediately after that, the upper digit counter 2 including the 1-bit register 3 for detecting a carry of the lower digit counter 1 is reset.

Next, the CPU 5 switches the selector 4 using the selection signal d, and reads the lower digit counter output 1 and the value of the 1-bit register 3 for detecting a carry of this counter.

At this time, if the carry counter 3 is "0", that is, there is no carry, the pulse count is simply the first read upper bit and the second read lower m bits. . Also, when the carry counter 3 is "1", that is, there is a carry, the count value is added to the count value of the first high-order digit read by CPtJ5, and the count is increased between the two reading times. As a result, accurate counting can be performed without any problem even if a carry occurs.

In this way, while constantly counting randomly arriving pulses, the count value is not read out at regular intervals (rn-+
−k) Bit pulse counting readout circuit
It consists of a binary counter for lower digits with a bit reset, a binary counter for upper digits with a k-bit reset, and a register with a 1-bit reset that detects the carry of the binary counter for lower digits. It is provided with means for reading and setting the bit register and means for reading and setting the lower bit register binary counter + 1 bit register. This allows accurate pulse counting with small-scale hardware.

〔Effect of the invention〕

As explained above, the present invention has the effect of eliminating the counter output register, which conventionally required a considerable hardware scale, and guaranteeing the one-time sampling performance of the performance monitoring circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is a circuit diagram showing an example of a conventional pulse count readout circuit. 1... m-bit counter for lower digits 2... bit counter 3 for upper digits... 1-bit register for carry detection 4... selector circuit 5...・CPtJ

Claims (2)

[Claims] (1) In an (m+k)-bit pulse counting readout circuit that constantly counts randomly arriving pulses and reads out the count value at regular intervals, an m-bit binary counter with reset for lower digits counts the arriving pulses. , k to count the output from this binary counter for lower digits
A binary counter for the upper digit with a bit reset, a register with a 1-bit reset that detects the carry of the binary counter for the lower digit, and a register for reading the upper digit binary counter of the bit, and this upper digit binary counter and the 1-bit register. 1. A pulse counting readout circuit comprising: a m-bit lower digit binary counter; and counting means that reads and resets an m-bit register. (2) The counting means sends out the value of the binary counter for upper digits or the value of the binary counter and 1-bit register for lower digits as a count value by the selection signal, and sends out the value of the binary counter for upper digits and the 1-bit register by the reset signal. 2. The pulse count readout according to claim 1, further comprising a selector that resets the lower digit binary counter, and a processing section that sends a selection signal and a reset signal to this selector and reads the counted value from this selector. circuit.