JPH0484507A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To improve the noise frequency characteristic even against further multi-channel requirements by providing sets of transistors (TRs) each comprising a couple of common base TRs to each group channel, connecting outputs of each of TR sets altogether and using the connected point as a signal output terminal. CONSTITUTION:Lots of channels 1 are grouped to form group channels A-C, sets of TRs 2A-2C each comprising a couple of common base TRs are provided respectively to the group channels A-C, and outputs of the sets of TRs 2A-2C are connected together to form signal output terminals 41,42. Thus, the parasitic capacitance between the input and output terminals of the common base TRs being components of an activated group is reduced. Then the noise frequency characteristic at harmonic frequencies even against further multi-channel requirements is maintained within a prescribed excellent range.

Description

[Detailed description of the invention] [Summary of the invention] Regarding multi-channel cascade-connected differential amplifier circuits.

Improvements in the frequency characteristics of noise when increasing the number of channels
The purpose is 1-.

A large number of channels are divided into each BY to form a group channel, and each group channel is provided with a transistor set consisting of a pair of common base transistors.

The output sides of each transistor set are connected together to form a signal output terminal.

[Field of Industrial Application] The present invention relates to a multi-channel cascade-connected differential amplifier circuit that activates one of the multi-channel inputs to amplify and output the input signal of one channel.

The cascade-connected differential amplifier circuit used as the first stage amplifier circuit of the readout circuit in magnetic storage devices such as hard disks has conventionally been configured as 2 to 4 channels, but it has been developed to accommodate the increasing capacity of magnetic storage devices. In response to the demand for improved signal processing capability, it has become necessary to have even more channels, for example, 8 to 10 channels, and this multi-channel technology is equivalent to or even higher than the conventional one.
Low noise, low input capacitance characteristics, and noise frequency characteristics in a high frequency range are required.

[Conventional technology] A conventional cascade-connected differential amplifier circuit is shown in FIG.

Note that in this figure and other figures, since all the internal circuits of each channel 1 have the same configuration, illustrations of the internal circuits of other channels except for some channels 1 are omitted.

In the figure, a pair of transistors Q1. Q2 is configured as a differential pair whose emitters are directly connected to each other, and a transistor Q constitutes a differential pair and a selection section that activates this differential pair.
3 constitutes one channel 1. One transistor Q1 of each channel 1 differential pair is collectively connected to one transistor Q1 of the other channel 1 differential pair at their respective collectors to form a first collective connection, and similarly each The other transistor Q2 of the channel 1 differential pair is each configured to be collectively connected with the other transistor Q2 of the other channel 1 differential pair at their respective collectors to form a second collective connection. Ru.

Both collective connection portions are connected to respective emitter terminals of the first common base transistor Q4 and the second common base transistor Q5 constituting the transistor set.

Both of these common base transistors Q4. The collector terminal of Q5 is connected to the same power supply V through load resistors R1 and R2, respectively.
cc and a pair of signal output terminals 41.cc. ,
42.

- The input signal from the input signal terminal 11.12 of one selected channel 1 is amplified and outputted from the signal output terminal 41.42 according to the overall configuration described in (a).

The signal is input to the next stage amplifier circuit or used as is as an output signal.

[Problems to be Solved by the Invention] As mentioned above, with the increase in density and capacity of magnetic storage devices such as hard disks, conventional multi-channel cascade-connected differential amplifier circuits have had to improve their signal processing capabilities. 1-
There is a constant demand for further multichannelization and improvement of the frequency characteristics of noise in the high frequency range.

The present invention aims to further increase the number of channels in a conventional multi-channel cascade-connected differential amplifier circuit, and to
The purpose of this invention is to maintain constant frequency characteristics of noise in a high frequency range even when the layer is multi-channeled, thereby meeting the above requirements.

[Means to achieve the task] FIG. 1 is a diagram showing the principle of the present invention.

Divide the large number of channels 1 into each group and divide them into group channels AB.
, C, and transistor sets 2A and 2B consisting of a pair of common base transistors.

2C is provided for each group of channels A, B, and C, and the output sides of each transistor set 2A, 2B, and 2C are connected together to form signal output terminals 41 and 42.

The present invention is based on the following findings.

When attempting to increase the number of channels based on the conventional 4-channel cascade-connected differential amplifier circuit 1 For example, 8
In the case of using a channel, the amplifier circuit of the comparative example shown in FIG. 5 will be selected.

In other words, if such an amplifier circuit is constructed as an IC circuit, the chip area can be minimized to a near limit, and moreover, this cascade-connected differential amplifier with many channels Considering that in a circuit, only one channel is always selected to be active, and only one signal is amplified and transmitted, in the conventional cascade-connected differential amplifier circuit, An attempt will first be made to select a comparative amplifier circuit (FIG. 5) in which all channels are connected in parallel and combined with one transistor set.

In the present invention, we first analyzed the required signal characteristics in the case of the comparative example amplifier circuit as described above, and it became clear that the noise frequency characteristics deteriorate in the high frequency range of 10 to 1.00 M1lz. Therefore, for the improvement,
This is a result of further consideration. As a result, it has been found that the configuration of the present invention eliminates the drawbacks of the amplifier circuit of the comparative example.

[In other words, by dividing a large number of channels into groups to form a group channel, and combining each transistor set for each group channel, the output terminal of each channel that is not active and the wiring and board that connect it. The parasitic capacitance that exists between the input and output terminals of the common-base transistors that make up the active group of transistors is reduced and increases. The frequency characteristics in the frequency range are improved, and the frequency characteristics of the noise of the entire cascade-connected differential amplifier circuit are improved.

[Example] Embodiments of the present invention will be further described with reference to the drawings.

FIG. 2 is a circuit diagram of a first embodiment of the present invention. In the figure, each channel 1, 1' consists of a pair of NPN transistors Ql, Q2 . A differential pair consisting of Ql', Q2' and each transistor Ql, Q2 . Ql', Q2'
A 30NPN transistor Q3. whose collector is connected to the mutually connected emitter terminals of the transistors Q3. and whose base is supplied with a channel selection signal via the selection terminal I3. Q3
It consists of ' and.

Each channel is divided into two groups, and each group has 4
channels 1.1' are included.

In each group channel A, B, the collectors of one transistor Ql, Ql' of the differential pair of each channel in one group are collectively connected for each group channel A, B to form a first collective connection part, The other transistor Q2. The collectors of Q2' are similarly connected together for each of the group channels A and B to form a second collective connection section.

Each of the first common base transistors Q4 configuring the transistor sets 2A and 2B. The emitter of Q4' is connected to the first collective connection consisting of the collective connected collectors,
Similarly, each second common base transistor Q5. The emitter of Q5' is connected to a second collective connection consisting of the collective connected collectors, and each group channel A, B is combined with a transistor set 2A, 2B.

The collector terminals of the first common-base transistors Q4 of the respective transistor sets 2A and 2B combined with the channels A and B of each group are collectively connected to the collector terminals of the first common-base transistors Q4' of the other transistor set. The collector terminal of the second common-base transistor Q5 is similarly connected to the collector terminal of the second common-base transistor of the other transistor group to become the other signal output terminal 42, and thus a pair of signal outputs. Terminals 41, 42 are formed.

When a channel selection signal for activating one selected channel 1.1' with the configuration shown in FIG. 2 is transmitted to the selected channel through the selection terminal 13.13',
A pair of signal input terminals 11.12°11', 12'
The signal input to the channel 1.1' and the transistor group 2 combined with the channels A and B
The signals A and 2B are amplified and transmitted to the next stage amplifier circuit via signal output terminals 41 and 42, or used as an output signal.

In this embodiment, NPN transistors Ql, Q2 . The collectors of Ql' and Q2' are connected together for each set in each group, and the base-grounded transistors Q4. Q5. Q4', Q5
', the parasitic capacitance to ground of the collectors of the transistors of each channel that belong to a group different from the active channels and the wiring that connects them is different from the group of active channels. There is no parasitic capacitance between the input and output of the combined transistor set, and the frequency characteristics of noise, especially in the high frequency range, are improved compared to the amplifier circuit of the comparative example.

FIGS. 3(a), 3(b), and 3(c) each show a circuit diagram showing the configuration of each channel 1 as an example. FIG. 2(a) is the same as the channel circuit diagram shown in FIG.

Figure (b) shows a pair of bipolar transistors Ql.

The emitters of Q2 are connected to each other via diodes DI and D2, and in the same figure (C), the emitters are connected to each other via a resistor R1.
, R2. According to the circuits of (b) and (c) in the same figure, the transistors Ql and Q in each channel
2. The manpower capacity of Ql' and Q2' can be reduced. However, in this case, the noise generated within the circuit tends to increase somewhat. In each of the figures (a) to (e), a preferable example is shown in which the differential pair is composed of bipolar transistors, but as is well known, it is also possible to employ a differential pair composed of field effect transistors. .

FIG. 4 shows a circuit diagram of a second embodiment of the invention. The main differences from Figure 1 are transistor sets 2A and 2.
Schottky diode SDI for shunt on the collector side which becomes the output terminal of B.

SO2, SDI', and SD2' are connected, and each collector is collectively connected via this Schottky diode, and this collective connection is configured as a signal output terminal 41, 42. In this way, it is possible to prevent an increase in the parasitic capacitance of the signal output terminal to ground due to the common-base transistor of the transistor set combined with a group channel other than the group channel including the activated channel, and to improve the frequency characteristics. be able to.

Key diode SDI, SO2, SDI
It is also possible to connect the output terminals of each transistor group together via a resistor instead of ', SD2'.

FIG. 7 shows the frequency characteristics of the input equivalent noise voltage (nV/f[) in the conventional cascade-connected differential amplifier circuits according to the comparative example and the first embodiment of the present invention. In the case of the 8-channel differential amplifier circuit diagram of the embodiment of the present invention shown in FIG.
In the frequency range of , it is possible to obtain a suitable diagram similar to the frequency characteristics of the input equivalent voltage of the 4-channel differential amplifier circuit shown in the same figure (C). It has better characteristics than the diagram of the cascade-connected differential amplifier circuit of the comparative example, which is simply connected all together and combined with one transistor set. In the case of the circuit characteristics of the comparative example, when used in a high-density hard disk drive, the input equivalent noise voltage exceeds the upper limit for good characteristics, which is 0.9 nV. It can be understood that this cannot be used in the frequency range of ~100 MIIZ.

In this embodiment, two group channels are shown, but a similar configuration can be made with three or more group channels. Preferably, the number of channels in one group is 5 or less to maintain the frequency characteristics of noise in a high frequency range within a certain good range.

[Effects of the Invention] As explained below, in the cascade-connected differential amplifier circuit of the present invention, the parasitic capacitance between the input and output terminals of the transistor set is reduced, and as a result, the high The frequency characteristics of noise in the frequency range can be maintained within a certain good range.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention. FIG. 2 is a circuit diagram of a first embodiment of the present invention. FIG. 3 is a diagram showing an example of the circuit of each channel. FIG. 4 is a circuit diagram of a second embodiment of the present invention. FIG. 5 is a circuit diagram of a comparative example for comparison with the amplifier circuit of the present invention. FIG. 6 is a circuit diagram of a conventional cascade-connected differential amplifier circuit. FIG. 7 is a frequency characteristic diagram of the input equivalent noise voltage in each amplifier circuit. In FIG. 1, 1 is a channel and 2A. 2B and 2C are transistor sets, 41.42 are signal output terminals, and A, B, and C are group channels.

Claims (3)

[Claims] (1) A pair of transistors, each having its base or gate as a pair of signal input terminals, its emitter or source/drain connected in common, and its collector or source/drain serving as a pair of output terminals. a plurality of channels (1) each comprising a differential pair consisting of a differential pair and a selection section connected to the commonly connected terminal to activate the differential pair; Each group is divided into a plurality of group channels (A, B, C), and the output terminals of one transistor of the differential pair and the output terminals of the other transistor are connected to each other of the group channels (A, B, C), respectively. C) are connected together to form first and second collective connection parts, and a first common base transistor connected to the first collective connection part and connected in cascade with the one transistor; A transistor set (2A, 2
B, 2C) are provided for each group channel (A, B, C), and the output terminals of the respective first base-grounded transistors and the respective second bases of each transistor set (2A, 2B, 2C) are provided for each group channel (A, B, C). The output terminals of the grounded transistors are connected together to form a pair of signal output terminals (41, 42), and the signal applied to the signal input terminal of one active channel (1) is amplified. A differential amplifier circuit characterized by outputting a single amplified signal. (2) The differential amplifier circuit according to claim 1, wherein the differential pair is composed of bipolar transistors, and the emitters of the bipolar transistors are connected to each other via a resistor or a diode. circuit. (3) The differential amplifier circuit according to claim 1, wherein the first common-base transistors and the second common-base transistors of each group are connected together via a resistor or a diode, respectively. differential amplifier circuit.