JPH0484494A - Multilayer circuit board - Google Patents
Multilayer circuit boardInfo
- Publication number
- JPH0484494A JPH0484494A JP2200032A JP20003290A JPH0484494A JP H0484494 A JPH0484494 A JP H0484494A JP 2200032 A JP2200032 A JP 2200032A JP 20003290 A JP20003290 A JP 20003290A JP H0484494 A JPH0484494 A JP H0484494A
- Authority
- JP
- Japan
- Prior art keywords
- glass frit
- multilayer circuit
- circuit board
- board
- yield point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011521 glass Substances 0.000 claims abstract description 55
- 238000005245 sintering Methods 0.000 claims abstract description 21
- 239000000843 powder Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 30
- 229910010293 ceramic material Inorganic materials 0.000 claims description 9
- 239000004020 conductor Substances 0.000 abstract description 19
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000010030 laminating Methods 0.000 abstract description 3
- 239000000919 ceramic Substances 0.000 abstract 1
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 238000010304 firing Methods 0.000 description 7
- 239000010931 gold Substances 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 239000011230 binding agent Substances 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- DOIRQSBPFJWKBE-UHFFFAOYSA-N dibutyl phthalate Chemical compound CCCCOC(=O)C1=CC=CC=C1C(=O)OCCCC DOIRQSBPFJWKBE-UHFFFAOYSA-N 0.000 description 2
- 238000007606 doctor blade method Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- IHWJXGQYRBHUIF-UHFFFAOYSA-N [Ag].[Pt] Chemical compound [Ag].[Pt] IHWJXGQYRBHUIF-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052878 cordierite Inorganic materials 0.000 description 1
- JSKIRARMQDRGJZ-UHFFFAOYSA-N dimagnesium dioxido-bis[(1-oxido-3-oxo-2,4,6,8,9-pentaoxa-1,3-disila-5,7-dialuminabicyclo[3.3.1]nonan-7-yl)oxy]silane Chemical compound [Mg++].[Mg++].[O-][Si]([O-])(O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2)O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2 JSKIRARMQDRGJZ-UHFFFAOYSA-N 0.000 description 1
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000006112 glass ceramic composition Substances 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000004898 kneading Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920000609 methyl cellulose Polymers 0.000 description 1
- 239000001923 methylcellulose Substances 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052863 mullite Inorganic materials 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 239000004014 plasticizer Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- ONVGIJBNBDUBCM-UHFFFAOYSA-N silver;silver Chemical compound [Ag].[Ag+] ONVGIJBNBDUBCM-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、回路基鴨葎に、多層回路基板に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a circuit board and a multilayer circuit board.
電子機器の混成集積回路等に用いられる回路基板として
、所定の導体パターンが形成された基板を複数枚積層し
て一体焼成した多層回路基板が知られている。この多層
回路基板では、内部に内部配線が配置されており、また
表面に表面配線が配置されている。2. Description of the Related Art Multilayer circuit boards are known as circuit boards used in hybrid integrated circuits and the like of electronic devices, in which a plurality of boards on which predetermined conductor patterns are formed are laminated and integrally fired. This multilayer circuit board has internal wiring arranged inside and surface wiring arranged on the front surface.
従来、多層回路基板として、エポキシ樹脂やフェノール
樹脂等の有機基板、またはアルミナセラミック基板が用
いられている。ところが、有機基板は熱的信頼性が充分
ではない。また、アルミナセラミック基板は、抵抗値が
高いモリブデンやタングステン等を内部配線材料として
いるため、信号伝達の高速化が困難である。また、アル
ミナセラミック基板は、高温焼成が必要なため、高価格
である。そこで、アルミナ等のセラミック材料を含むガ
ラスフリント製基板の積層体からなり、Ａｕ、Ａｇ、Ｃ
ｕ等の低融点で低抵抗の金属からなる内部配線を備えた
低温焼成型の多層回路基板が提案されている（たとえば
、特開昭６１−１０８１９２号公報参照）。Conventionally, organic substrates such as epoxy resin and phenol resin, or alumina ceramic substrates have been used as multilayer circuit boards. However, organic substrates do not have sufficient thermal reliability. Furthermore, since the alumina ceramic substrate uses molybdenum, tungsten, or the like, which have a high resistance value, as an internal wiring material, it is difficult to increase the speed of signal transmission. Furthermore, alumina ceramic substrates are expensive because they require high-temperature firing. Therefore, it is made of a laminate of glass flint substrates containing ceramic materials such as alumina, Au, Ag, and C.
A low-temperature firing type multilayer circuit board having internal wiring made of a metal with a low melting point and low resistance, such as U, has been proposed (see, for example, Japanese Patent Laid-Open No. 108192/1983).
前記多層回路基板では、製造工程で用いるバインダーの
除去を容易にするために、基板の焼結開始温度を高く設
定するのが好ましい。ところが、この場合、内部配線に
使用するＡｇ等の導電性粉末が基板の焼結開始温度前に
焼結し始めるため、基板と内部配線との焼結及び収縮の
挙動が合わず、基板に反りが生じる。特に、Ａｕ及びＣ
ｕに比べて融点が低いＡｇを用いた場合は、基板の反り
が顕著である。このような基板の反りを解決するために
、基板用のガラスセラミック材料を内部配線用の導電性
ペーストに添加することが提案されている（特開昭６０
−２４０９５号公報参照）が、この場合は導電性粉末の
焼結が阻害されて内部配線の導電性が低下する。In the multilayer circuit board, the sintering start temperature of the board is preferably set high in order to facilitate the removal of the binder used in the manufacturing process. However, in this case, since the conductive powder such as Ag used for the internal wiring begins to sinter before the sintering start temperature of the board, the sintering and shrinkage behavior of the board and internal wiring do not match, causing the board to warp. occurs. In particular, Au and C
When Ag, which has a lower melting point than U, is used, the substrate warps significantly. In order to solve this problem of substrate warpage, it has been proposed to add a glass-ceramic material for substrates to conductive paste for internal wiring (Japanese Patent Application Laid-open No. 60-1999).
In this case, the sintering of the conductive powder is inhibited and the conductivity of the internal wiring is reduced.
本発明の目的は、基板の反りが少なく、しかも内部配線
の導電性が良好な、ガラスフリット製の多層回路基板を
提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer circuit board made of glass frit, in which the board is less warped and the internal wiring has good conductivity.
本発明に係る多層回路基板は、ガラスフリットを含むセ
ラミック材からなる基板が積層された積層基板内に、前
記基板の焼結開始温度よりも低い屈伏点をもったガラス
フリットを含む導電性ペーストを用いて内部配線を形成
したことを特徴としている。A multilayer circuit board according to the present invention includes a conductive paste containing a glass frit having a yield point lower than the sintering start temperature of the substrate, in a laminated substrate in which substrates made of a ceramic material containing a glass frit are laminated. The feature is that the internal wiring is formed using
なお、本発明では、導電性ペーストに含まれるガラスフ
リットの屈伏点は、たとえば７００〜８４５℃である。In addition, in this invention, the bending point of the glass frit contained in a conductive paste is 700-845 degreeC, for example.
また、導電性ペーストは、たとえばＡｇ系の導電性粉末
を含んでいる。さらに、導電性粉末がＡｇ系の場合、導
電性ペースト中のガラスフリットの添加量は導電性粉末
の３０〜５５体積％である。Further, the conductive paste contains, for example, Ag-based conductive powder. Furthermore, when the conductive powder is Ag-based, the amount of glass frit added in the conductive paste is 30 to 55% by volume of the conductive powder.
本発明に係る多層回路基板では、内部配線を形成するた
めの導電性ペーストに上述のようなガラスフリントが含
まれている。この導電性ペーストは、焼結開始温度が基
板の焼結開始温度と接近しているため焼結時に基板に反
りを起こさせにくい。In the multilayer circuit board according to the present invention, the above-mentioned glass flint is included in the conductive paste for forming internal wiring. Since the sintering start temperature of this conductive paste is close to the sintering start temperature of the substrate, it is difficult to cause the substrate to warp during sintering.
また、導電性ペーストには基板の焼結開始温度よりも低
い屈伏点のガラスフリットが含まれているため、焼結後
の導電性が良好である。このため、本発明によれば、反
りが少なく、また内部配線の導電性が良好なガラスフリ
ット製の多層回路基板が実現できる。Furthermore, since the conductive paste contains glass frit whose yield point is lower than the sintering start temperature of the substrate, the conductivity after sintering is good. Therefore, according to the present invention, a multilayer circuit board made of glass frit with less warpage and good conductivity of internal wiring can be realized.
第１図は、本発明の一実施例に係る多層回路基板の縦断
面部分図である。図において、多層回路基板１は、積層
基板２と、内部配線３と、表面配置ｌａ４とから構成さ
れている。FIG. 1 is a partial vertical cross-sectional view of a multilayer circuit board according to an embodiment of the present invention. In the figure, a multilayer circuit board 1 is composed of a laminated board 2, internal wiring 3, and a surface arrangement la4.
積層基板２は、たとえば３枚のガラスフリット製グリー
ンシートを積層して一体焼成することにより得られた一
体化したシート２ａ、２ｂ、２ｃから構成されている。The laminated substrate 2 is composed of integrated sheets 2a, 2b, and 2c obtained by laminating, for example, three glass frit green sheets and firing them together.
各グリーンシートを構成するガラスフリットとしては、
たとえばＭｇ０−Ａ１．０．−３ ｉ Ｏ□を主成分と
するものが用いられる。また、上述のガラスフリットに
は、セラミック材料が含まれている。セラミック材料と
しては、たとえばアルミナ、ムライト、コージェライト
等が挙げられる。このセラミック材料は、単独で添加さ
れてもよいし、２種以上混合して添加されてもよい。な
お、セラミック材料は、ガラスフリットに対して通常１
０〜４５重量％程度添加される。The glass frit that makes up each green sheet is as follows:
For example, Mg0-A1.0. -3 i O□ is used as the main component. Moreover, the above-mentioned glass frit contains a ceramic material. Examples of the ceramic material include alumina, mullite, and cordierite. These ceramic materials may be added alone or in a mixture of two or more. Note that ceramic materials usually have a ratio of 1 to glass frit.
It is added in an amount of about 0 to 45% by weight.
内部配線３は、シーｆ−２ａ、２ｂ間、及びシート２ｂ
、２ｃ間に所定のパターンで形成されている。各内部配
線３は、スルーホール６を通じて積層基Ｆｉ２の表面に
延びており、その先端が積層基板２の図上面及び図下面
で電極３ａを形成している。内部配線３は、導電性材料
と、ガラスフリントと、有機ビヒクルとを含む導電性ペ
ーストにより形成されている。導電性材料としては、銀
（Ａｇ）系、金（Ａｕ）系及び銅（Ｃｕ）系の導電性材
料が用いられる。このうち、本実施例では、導電性が良
好な銀系の導電性材料を用いるのが好ましい。Ａｇ系の
導電性材料は、Ａｕ系またはＣｕ系の導体材料よりも焼
結開始温度が低いため、積層基板２の反りの防止効果を
さらに高めることができる。Ａｇ系の導電性材料として
は、たとえば銀、銀−パラジウム、銀−白金、銀−パラ
ジウム−白金等の導電性材料が例示できる。ガラスフリ
ットとしては、上述のガラスフリット製グリーンシート
の焼結開始温度よりも低い屈伏点のものが用いられる。The internal wiring 3 is between sheets f-2a and 2b, and between sheets f-2b
, 2c in a predetermined pattern. Each internal wiring 3 extends to the surface of the laminated substrate Fi2 through a through hole 6, and its tips form electrodes 3a on the upper and lower surfaces of the laminated substrate 2 in the figure. The internal wiring 3 is formed of a conductive paste containing a conductive material, glass flint, and an organic vehicle. As the conductive material, silver (Ag)-based, gold (Au)-based, and copper (Cu)-based conductive materials are used. Among these, in this embodiment, it is preferable to use a silver-based conductive material having good conductivity. Since the Ag-based conductive material has a lower sintering start temperature than the Au-based or Cu-based conductive material, the effect of preventing warpage of the laminated substrate 2 can be further enhanced. Examples of the Ag-based conductive material include conductive materials such as silver, silver-palladium, silver-platinum, and silver-palladium-platinum. As the glass frit, one having a yield point lower than the sintering start temperature of the above-mentioned glass frit green sheet is used.
ここで、屈伏点とは、ガラスフリットの体積が熱膨張に
より急激に増加する挙動を示す温度範囲から粘性流動に
より収縮する温度範囲に移行する際の境界の温度をいう
。屈伏点は、通常ガラスフリットのガラス転移点と軟化
点との間で観測される。なお、ガラスフリットの屈伏点
が基板の焼結開始温度よりも高い場合は、反りの少ない
多層回路基板が実現できない。上述のような屈伏点のガ
ラスフリットとしては、たとえばＢ２Ｏ５Ｓ ＋ ０２
Ｃａ ＯＡ ｅ ｔ０２を挙げることができる。こ
のうち、特に屈伏点が７００〜８４５℃のガラスフリン
トが好ましい。屈伏点が７００℃未満の場合は、ガラス
流動が速くなり、導電性材料同士が引き寄せられて焼結
が促進され、この結果導電性材料が過焼結状態となり、
内部配線抵抗値が大きくまた不安定となる。逆に、屈伏
点が８４５℃を超える場合は、ガラスフリットの軟化流
動性が悪く、ガラスフリットが導電性粒子間に均一に介
在せず、導電性粒子どうしが焼結反応を起こし、その結
果基板の反りが生じる。前記範囲の屈伏点のガラスフリ
ットとしては、Ｂ、０３ Ｓ ｉＯ２Ｂ ａ Ｏが例
示できる。上述のガラスフリットは、平均粒径が１０μ
ｍ以下のものが好ましい。平均粒径が１０μｍを超える
と、たとえば内部配線をスクリーン印刷する際に、スク
リーンに目詰まりが生じる恐れがある。また、焼成時に
ガラスフリットが流動しきらない場合がある。Here, the yield point refers to the temperature at the boundary when the glass frit's volume changes from a temperature range in which it rapidly increases due to thermal expansion to a temperature range in which it contracts due to viscous flow. The yield point is usually observed between the glass transition point and the softening point of the glass frit. Note that if the yield point of the glass frit is higher than the sintering start temperature of the substrate, a multilayer circuit board with less warpage cannot be realized. As the glass frit with the above-mentioned deformation point, for example, B2O5S + 02
Ca OA e t02 can be mentioned. Among these, glass flint having a yield point of 700 to 845°C is particularly preferred. When the yield point is less than 700°C, the glass flow becomes faster, the conductive materials are attracted to each other, and sintering is promoted. As a result, the conductive materials become oversintered,
The internal wiring resistance value becomes large and unstable. On the other hand, if the yield point exceeds 845°C, the softening fluidity of the glass frit is poor, the glass frit is not evenly interposed between the conductive particles, and a sintering reaction occurs between the conductive particles, resulting in the substrate Warping occurs. An example of the glass frit having a deformation point within the above range is B,03S iO2B a O. The above-mentioned glass frit has an average particle size of 10μ
m or less is preferable. If the average particle size exceeds 10 μm, the screen may become clogged when, for example, internal wiring is screen printed. Further, the glass frit may not completely flow during firing.
ガラスフリットは、上述の導電性材料としてＡｇ系の導
電性粉末を用いた場合、Ａｇ系の導電性粉末の３０〜５
５体積％添加される。添加量が３０体積％未溝の場合は
、導電性材料の焼結を充分に抑制できず、積層基板２に
反りが生じやすい。逆に、添加量が５５体積％を超える
場合は、内部配線３中のガラス成分が多くなるため、Ａ
ｇ系導電性粉末木来の高導電性が得られず、多層回路基
板をｉ１通ずる信号の高速化が困難になる。When using Ag-based conductive powder as the above-mentioned conductive material, the glass frit is
5% by volume is added. If the amount added is 30% by volume without grooves, sintering of the conductive material cannot be sufficiently suppressed, and the laminated substrate 2 is likely to warp. On the other hand, if the amount added exceeds 55% by volume, the glass component in the internal wiring 3 will increase.
The high conductivity of the g-based conductive powder cannot be obtained, making it difficult to increase the speed of signals passing through the multilayer circuit board.
表面配線４は、積層基板２の少なくとも一方の主面（図
では両生面）に所定の高密度パターンで形成されている
。表面配Ｉｉ４は、たとえばマイグレーションを起こし
にくいＣｕ系の導電性材料を含む導電性ペーストにより
形成されている。The surface wiring 4 is formed in a predetermined high-density pattern on at least one main surface (the bidirectional surface in the figure) of the laminated substrate 2. The surface wiring Ii4 is formed of, for example, a conductive paste containing a Cu-based conductive material that does not easily cause migration.
前記多層回路基板１では、内部配線３の電極３ａ、３ａ
間及び電極３ａと表面配線４との間に電子部品ψチップ
７が配置される。そして、このチップ７は、電極３ａま
たは表面配線４にはんだ付けされる。これにより、電極
３ａ、３ａ間及び電極３ａと表面配線４との間が接続さ
れる。なお、電極３ａと表面配線４との接続は、両者の
間に接続誘導体８を配置することにより行われてもよい
。In the multilayer circuit board 1, the electrodes 3a, 3a of the internal wiring 3
An electronic component ψ chip 7 is arranged between the electrode 3 a and the surface wiring 4 . This chip 7 is then soldered to the electrode 3a or the surface wiring 4. This connects the electrodes 3a and 3a and the electrode 3a and the surface wiring 4. Note that the connection between the electrode 3a and the surface wiring 4 may be performed by arranging the connection inductor 8 between them.
次に、前記多層回路基板１の製造方法について説明する
。Next, a method for manufacturing the multilayer circuit board 1 will be explained.
多層回路基板１の製造では、まず積層基板２を形成する
。積層基板２は、上述のガラスフリットからなるグリー
ンシートを積層して一体焼成することにより得られる。In manufacturing the multilayer circuit board 1, first, the laminated board 2 is formed. The laminated substrate 2 is obtained by laminating green sheets made of the above-mentioned glass frit and firing them together.
グリーンシートは、ガラスフリットとセラミック材料と
有機バインダーと有機溶剤とを混練し、得られたペース
トをたとえばドクターブレード法によりシート化するこ
とにより得られる。The green sheet is obtained by kneading a glass frit, a ceramic material, an organic binder, and an organic solvent, and forming the resulting paste into a sheet by, for example, a doctor blade method.
内部配線３は、上述の導電性ペーストをあらかじめ各グ
リーンシートの表面及び各グリーンシートに設けられた
スルーホール内に印刷または充填し、グリーンシートと
同時に焼成することにより形成される。この際、導電性
ペーストでは、導電性材料の粒子表面にガラス成分が均
一に分布し、これによりグリーンシートの焼結開始温度
と導電性材料の焼結開始温度とが接近する。この結果、
積層基板２の反りが抑制される。The internal wiring 3 is formed by printing or filling the above-mentioned conductive paste in advance on the surface of each green sheet and into the through holes provided in each green sheet, and firing the paste at the same time as the green sheet. At this time, in the conductive paste, the glass component is uniformly distributed on the particle surface of the conductive material, so that the sintering start temperature of the green sheet approaches the sintering start temperature of the conductive material. As a result,
Warpage of the laminated substrate 2 is suppressed.
次に、積層基板２の表面に表面配線４を配置する。表面
配線４は、導電性材料と有機ビヒクルとからなる導電性
ペーストを所定の高密度パターンで積層基板２上に印刷
し、これを焼成することにより形成される。Next, surface wiring 4 is arranged on the surface of laminated substrate 2. The surface wiring 4 is formed by printing a conductive paste made of a conductive material and an organic vehicle on the laminated substrate 2 in a predetermined high-density pattern, and firing the paste.
こうして得られた多層回路基板】の所定部位には、電子
部品や表面配線４と内部配線３との接続用導体等が配置
される。Electronic components, conductors for connection between the surface wiring 4 and the internal wiring 3, and the like are arranged at predetermined portions of the thus obtained multilayer circuit board.
ＭｇＯ１ＡＩ！、、０．及びＳｉｎ、を主成分とするガ
ラスフリットとセラミック材料としてのアルミナとを混
合し、これにアクリル系樹脂とトルエンとジブチルフタ
レート（可塑剤）とを加えてボールミルで混合してペー
ストを作成した。そして、得られたペーストからドクタ
ーブレード法によりグリーンシートを作成した。MgO1AI! ,,0. A paste was prepared by mixing a glass frit mainly composed of and Sin and alumina as a ceramic material, adding an acrylic resin, toluene, and dibutyl phthalate (plasticizer) and mixing in a ball mill. A green sheet was then created from the resulting paste by a doctor blade method.
一方、Ａｇ粉末とガラスフリットとメチルセルロースと
２．２．４−）ジメチル−１，３−ベンタンジオールモ
ノイソブチレートとを３本ボールミルで混練し、導電性
ペーストを作成した。ガラスフリットには、ＢｔＯ，、
Ｓ ｉ Ｏｘ及びＰｂＯを主成分とするガラスフリット
（■）、またはＢｔｏ、ｌ、Ｓ Ｉ Ｏｘ及びＢａＯを
主成分とするガラスフリット（ＩＩ）を用いた。なお、
ガラスフリットの添加量等は、表に示す通りに設定した
。On the other hand, Ag powder, glass frit, methylcellulose, and 2.2.4-)dimethyl-1,3-bentanediol monoisobutyrate were kneaded in a three-ball mill to create a conductive paste. The glass frit contains BtO,
A glass frit (■) whose main components are S i Ox and PbO, or a glass frit (II) whose main components are Bto, I, S I Ox, and BaO were used. In addition,
The amount of glass frit added was set as shown in the table.
得られた導電性ペーストを上述のグリーンシート上に所
定のパターンで印刷し、このグリーンシートを５枚積層
してピーク温度９００℃で３０分間焼成し、多層回路基
板を得た。The obtained conductive paste was printed in a predetermined pattern on the above-mentioned green sheet, and five of these green sheets were laminated and fired at a peak temperature of 900° C. for 30 minutes to obtain a multilayer circuit board.
得られた多層回路基板について、基板の反り及び内部配
線の抵抗値を調べた。測定方法番よ次の通りである。The resulting multilayer circuit board was examined for board warpage and internal wiring resistance. The measurement method number is as follows.
反与
反りゲージで基板の最大高さを求め、この高さから基板
の厚みを差し引いた値を反りとした。０゜０２闘以下が
合格である。The maximum height of the board was determined using an anti-warp gauge, and the value obtained by subtracting the thickness of the board from this height was defined as the warp. A score of 0°02 or less is considered passing.
専生抵バ通
４端子法（ホイートストンブリ・ンジを用し）た抵抗値
測定方法）により測定した。４．５ｍΩ以下が合格であ
る。The resistance value was measured using the 4-terminal method (using a Wheatstone bridge). A value of 4.5 mΩ or less is acceptable.
２ Ｂ ｚ Ｏ３Ｃａ ＯＺ ｒ Ｏｚガラスなどが
用いられてもよい。2BzO3CaOZrOz glass or the like may be used.
たとえば、屈伏点８４０℃５平均粒径５．５μｍのＳ
ｔ Ｏｔ ＢｚＯｉ Ｃａ ＯＺ ｒ Ｏｘガラス
を用い、その添加量を４５体積％に設定した場＊：本発
明に係る実験例
前記実施例では、ガラスフリットとして（１）（ＩＩ）
の２種類を用いたが、これらに代えてＣａＱ−Ｂ２０３
Ｓ ｉ Ｏｘガラス、ＳｉＯ□−Ｂ２０ｚ −Ｃａ
Ｏ−Ａｌｔｏｓガラス、またはＳｉ０〔発明の効果〕
本発明では、内部配線が上述のような導電性ペーストを
用いて形成されている。このため、第１の発明によれば
、基板の反りが少なく、また内部配線の抵抗値が小さな
多層回路基板が実現できる。For example, S with a yield point of 840°C and an average grain size of 5.5 μm.
When using t Ot BzOi Ca OZ r Ox glass and setting the addition amount to 45% by volume *: Experimental example according to the present invention In the above example, as the glass frit (1) (II)
Two types of CaQ-B203 were used in place of these.
SiOx glass, SiO□-B20z-Ca
O-Altos glass or Si0 [Effects of the Invention] In the present invention, the internal wiring is formed using the above-mentioned conductive paste. Therefore, according to the first invention, a multilayer circuit board can be realized in which the board has less warpage and the resistance value of the internal wiring is small.
第１図は本発明の一実施例の縮断面部分図である。
１・・・多層回路基板、２・・・積層基板、２ａ、２ｂ
。
２Ｃ・・・シート、３・・・内部配線。
特許出願人 京セラ株式会社
代理人 弁理士 宮 川 良 夫
第１図
手続補正書
（自発）
■、
事件の表示
平成２年特許願第２０
０３２号
２゜
発明の名称
多層回路基板
３、補正をする者
事件との関係FIG. 1 is a partial cross-sectional view of an embodiment of the present invention. 1... Multilayer circuit board, 2... Laminated board, 2a, 2b
. 2C... Sheet, 3... Internal wiring. Patent Applicant Kyocera Corporation Agent Patent Attorney Yoshio Miyagawa Figure 1 Procedural Amendment (voluntary) Relationship with the incident
Claims (4)
が積層された積層基板内に、前記基板の焼結開始温度よ
りも低い屈伏点をもったガラスフリットを含む導電性ペ
ーストを用いて内部配線を形成したことを特徴とする多
層回路基板。(1) Internal wiring is formed using a conductive paste containing glass frit that has a yield point lower than the sintering start temperature of the substrate in a laminated substrate in which substrates made of ceramic material containing glass frit are laminated. A multilayer circuit board characterized by:
トの屈伏点は、７００〜８４５℃である請求項（１）に
記載の多層回路基板。(2) The multilayer circuit board according to claim 1, wherein the glass frit contained in the conductive paste has a yield point of 700 to 845°C.
んでいる請求項（１）または（２）に記載の多層回路基
板。(3) The multilayer circuit board according to claim 1 or 2, wherein the conductive paste contains Ag-based conductive powder.
加量は、前記Ａｇ系の導電性粉末の３０〜５５体積％で
ある請求項（３）に記載の多層回路基板。(4) The multilayer circuit board according to claim 3, wherein the amount of the glass frit added in the conductive paste is 30 to 55% by volume of the Ag-based conductive powder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02200032A JP3130914B2 (en) | 1990-07-27 | 1990-07-27 | Multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02200032A JP3130914B2 (en) | 1990-07-27 | 1990-07-27 | Multilayer circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0484494A true JPH0484494A (en) | 1992-03-17 |
| JP3130914B2 JP3130914B2 (en) | 2001-01-31 |
Family
ID=16417690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP02200032A Expired - Fee Related JP3130914B2 (en) | 1990-07-27 | 1990-07-27 | Multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3130914B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6217990B1 (en) | 1997-05-07 | 2001-04-17 | Denso Corporation | Multilayer circuit board having no local warp on mounting surface thereof |
| US6376906B1 (en) | 1997-02-12 | 2002-04-23 | Denso Corporation | Mounting structure of semiconductor element |
| JP2014033004A (en) * | 2012-08-01 | 2014-02-20 | Ngk Spark Plug Co Ltd | Multilayer ceramic substrate and method for producing the same |
-
1990
- 1990-07-27 JP JP02200032A patent/JP3130914B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6376906B1 (en) | 1997-02-12 | 2002-04-23 | Denso Corporation | Mounting structure of semiconductor element |
| US6217990B1 (en) | 1997-05-07 | 2001-04-17 | Denso Corporation | Multilayer circuit board having no local warp on mounting surface thereof |
| JP2014033004A (en) * | 2012-08-01 | 2014-02-20 | Ngk Spark Plug Co Ltd | Multilayer ceramic substrate and method for producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3130914B2 (en) | 2001-01-31 |
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