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JPH0476037U - - Google Patents

Info

Publication number
JPH0476037U
JPH0476037U JP11850390U JP11850390U JPH0476037U JP H0476037 U JPH0476037 U JP H0476037U JP 11850390 U JP11850390 U JP 11850390U JP 11850390 U JP11850390 U JP 11850390U JP H0476037 U JPH0476037 U JP H0476037U
Authority
JP
Japan
Prior art keywords
semiconductor chip
lead
lead frame
frame
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11850390U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11850390U priority Critical patent/JPH0476037U/ja
Publication of JPH0476037U publication Critical patent/JPH0476037U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示す断面図、第2
図は本実施例の正面図、第3図は本考案の他の実
施例の断面図、第4図は本考案の他の実施例の要
部断面図、第5図は従来例の断面図である。 1……半導体チツプ、2……ダイパツド、3…
…ボンデイングワイヤ、4……リード、5……樹
脂、10……リードフレーム、11……枠状ダイ
パツド、12……リード、13……樹脂、15…
…テーパー部、16……凹部。
Fig. 1 is a sectional view showing one embodiment of the present invention;
The figure is a front view of this embodiment, FIG. 3 is a sectional view of another embodiment of the present invention, FIG. 4 is a sectional view of essential parts of another embodiment of the present invention, and FIG. 5 is a sectional view of a conventional example. It is. 1... Semiconductor chip, 2... Die pad, 3...
... bonding wire, 4 ... lead, 5 ... resin, 10 ... lead frame, 11 ... frame-shaped die pad, 12 ... lead, 13 ... resin, 15 ...
...Tapered portion, 16...Concave portion.

Claims (1)

【実用新案登録請求の範囲】 半導体用のリードフレームと、 前記リードフレームに搭載される半導体チツプ
と、 前記リードフレームに設けられ、前記半導体チ
ツプが挿通される穴が開口されると共に、半導体
チツプに接着される枠状ダイパツドと、 前記リードフレームに形成され、ボンデイング
ワイヤにより半導体チツプに接続されるリードと
、 前記の半導体チツプ、ダイパツド、ボンデイン
グワイヤ及びリードの一部が封止される樹脂と、 を備えたことを特徴とする半導体装置。
[Claims for Utility Model Registration] A lead frame for a semiconductor; a semiconductor chip mounted on the lead frame; a hole provided in the lead frame through which the semiconductor chip is inserted; a frame-shaped die pad to be bonded; a lead formed on the lead frame and connected to the semiconductor chip by a bonding wire; and a resin in which a portion of the semiconductor chip, die pad, bonding wire, and lead are encapsulated. A semiconductor device characterized by:
JP11850390U 1990-11-14 1990-11-14 Pending JPH0476037U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11850390U JPH0476037U (en) 1990-11-14 1990-11-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11850390U JPH0476037U (en) 1990-11-14 1990-11-14

Publications (1)

Publication Number Publication Date
JPH0476037U true JPH0476037U (en) 1992-07-02

Family

ID=31866426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11850390U Pending JPH0476037U (en) 1990-11-14 1990-11-14

Country Status (1)

Country Link
JP (1) JPH0476037U (en)

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