JPH0474241A - Fault processing system - Google Patents

Abstract

PURPOSE:To assure the fault processing and a normal operation after the fault processing by copying a control program including the fault processing program of a ROM onto a RAM and performing the due processing based on the copied control program. CONSTITUTION:When an error report signal 8 is applied to a CS switching circuit 5, the circuit 5 applies a signal 9 to a wait circuit 6. At the same time, the circuit 5 separates a RAM 3 from an internal bus 7 and connects a ROM 2 to the bus 7 so as to read a control program 10A out of the ROM 2. When the signal 9 is applied to the circuit 6, the circuit 6 applies a wait signal to a processor 1 and reduces the access speed of the processor 1 down to a level corresponding to the response speed of the ROM 2. Meanwhile the processor 1 transfers the control to a fault processing program 10A-a with the signal 8 and reads the program 10A out of the ROM 2. Therefore the processor 1 performs the fault processing based on the program 10A-a.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention involves copying a control program including a fault handling program stored in a ROM onto a RAM, and performing processing according to the control program copied onto the RAM. The present invention relates to an information processing device that enables high-speed operation, and particularly relates to a failure handling method when a parity error occurs in the output of a RAM.

[Conventional technology]

Conventionally, in this type of information processing device, when a parity error is detected in the output of the RAM, the fault is handled by executing a fault processing program included in the control program copied to the RAM. ing.

[Problem to be solved by the invention]

As mentioned above, conventionally, when a parity error is detected in the output of the RAM, the fault is handled according to the fault handling program that has been copied to the RAM. The problem was that it could not be guaranteed.

A ROM that stores a control program including a fault handling program; a RAM to which the control program stored in the ROM is copied when the power is turned on; and a RAM that accesses the RAM and executes the control program stored in the RAM. an information processing apparatus comprising: a parity checker that performs a parity check on the output of the RAM; and a control program stored in the RAM or a fault stored in the ROM for the processor; A switching means for executing the processing program; and a wait means for changing the access speed of the processor to correspond to the response speed of the ROM or to the response speed of the RAM, and a parity error is detected by the parity checker. Accordingly, the switching means causes the processor to execute a fault handling program stored in the ROM, the wait means makes the access speed of the processor correspond to the response speed of the ROM, and the processor Copying at least the contents of the portion where the parity checker detected a parity error from the ROM to the RAM by executing a fault handling program stored in the ROM, and completing the copying from the ROM to the RAM. Accordingly, the switching means causes the processor to select the RAM.
The wait means executes a control program stored in the RAM, and the wait means adjusts the access speed of the processor to the RAM.
be compatible with the response speed of

Further, in order to reduce the number of occurrences of parity errors, the present invention includes: a ROM in which a control program including a failure handling program is stored; a RAM to which the control program stored in the ROM is copied when power is turned on; An information processing device comprising: a processor that accesses a RAM and performs processing according to a control program stored in the RAM; a parity checker that performs a parity check on the output of the RAM; and the parity checker. an error record jf) means for storing whether or not a parity error was detected in the past; and a switching means for causing the processor to execute a control program stored in the RAM or a fault handling program stored in the ROM. , wait means for making the access speed of the processor correspond to the response speed of the ROM or the response speed of the RAM, and when a parity error is detected by the parity checker, the switching means causes the processor to execute the fault processing program stored in the ROM, the wait means makes the access speed of the processor correspond to the response speed of the ROM, and the processor executes the fault processing program stored in the ROM. By executing the processing program, it is determined whether or not a parity error has been detected in the past by referring to the error storage means, and if it is determined that a parity error has not been detected, the parity checker detects a parity error. Copy only the contents of the detected portion from the ROM to the RAM, and if it is determined that a parity error has been detected, copy the entire control program stored in the ROM to the RAM, and from the ROM to the RAM. When the copying to the RAM is completed, the switching means causes the processor to transfer the data to the RAM.
The wait means executes a control program stored in the RAM, and the wait means adjusts the access speed of the processor to the RAM.
be compatible with the response speed of

Furthermore, the present invention reduces the number of occurrences of parity errors and reduces the time required for troubleshooting. In an information processing device, the RAM is physically copied, and a processor accesses the Tomi RAM and performs processing according to the control program stored in the Tomi RAM. a parity checker which is composed of a plurality of blocks and which performs a parity check on the output of the RAM; and an error storage means which stores whether or not a parity error has been detected by the parity checker in the past for each block of the RAM. , the RAM in the processor
switching means for executing a control program stored in the ROM or a fault handling program stored in the ROM; and an access speed of the processor corresponding to a response speed of the ROM or a response speed of the RAM; When a parity error is detected by the parity checker, the switching means causes the processor to execute a fault handling program stored in the ROM, and the wait means causes the processor to execute an error handling program stored in the ROM. The speed is set to correspond to the response speed of the ROM, and the processor executes a fault handling program stored in the ROM to refer to the error storage means and determine whether the parity checker has detected a parity error this time. It is determined whether or not a parity error has been detected in the past for the block of the RAM, and if it is determined that a parity error has not been detected, the parity checker extracts only the contents of the part where the parity error was detected this time from the ROM. Copy to the RAM, and if it is determined that a parity error has been detected, copy only the contents of the block in which the parity checker detected a parity error this time from the ROM to the RAM, and copy from the rlOM to the RAM. is completed, the switching means causes the processor to switch to the RA.
The wait means executes a control program stored in the RA, and the wait means adjusts the access speed of the processor to the RA.
[Function] When the parity checker detects a parity error in the output of the RAM, the switching means causes the processor to execute the fault handling program stored in the ROM, and the wait means makes the access speed of the processor correspond to the response speed of the ROM.

By executing the fault handling program stored in the ROM, the processor reads at least the contents of the part where the parity checker detected a parity error from the ROM.
Copy to AM. When the copying from the ROM to the RAM is completed, the switching means causes the processor to execute the control program stored in the RAM, and the wait means makes the access speed of the processor correspond to the response speed of the RAM.

Further, in order to reduce the number of occurrences of parity errors, error storage means is provided for storing whether or not a parity error has been detected by the parity checker in the past.

When the processor executes the fault handling program stored in the ROM, the processor refers to the error storage means to determine whether or not a parity error has been detected in the past;
If the parity checker determines that no parity error has been detected, the parity checker copies only the contents of the part where the parity error was detected from the ROM to the RAM; if it determines that a parity error has been detected, the contents are stored in the ROM. Copy all control programs to the RAM.

In addition to reducing the number of parity errors,
In order to reduce the time required for troubleshooting, the RAM is physically composed of a plurality of blocks, and error storage means is provided for storing whether or not a parity error has been detected in the past by the parity checker for each block of the RAM. establish. When the processor executes the faulty processor stored in the ROM, the processor refers to the error storage means and determines whether or not a parity error has been detected in the past for the block in which the parity checker has detected a parity error this time; If the parity checker determines that no parity error has been detected, the parity checker copies only the contents of the part where the parity error was detected this time from ROM to RAM. Copy only the contents of the block in which an error has been detected from ROM to RAM.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which includes a processor 1, a ROM 2 in which a control program IOA including a failure handling program 10A-a is stored in an executable format, and a ROM 2 stored in the ROM 2 when the power is turned on. Control program I
RAM where OA is copied as control program 10B
3, a parity checker 4 that detects a parity error in the output of the RAM 3, a C3 (control memory) switching circuit 5 that allows the processor 1 to access only one of the ROM 2 and the RAM 3, and a C3 (control memory) switching circuit 5 that controls the access speed of the processor 1. A weight circuit 6 to control, a processor 1. ROM2.
It is composed of an internal bus 7 that connects the RAM 3.

FIG. 2 is a diagram showing an example of the configuration of the RAM 3, which is physically composed of a plurality of blocks 3-1 to 3-4. Each block 3-1 to 3-4 contains l0A-1 to l0A-4 of the control program 10A stored in the RAM 2.
The parts are copied as l0B-1 to l0B-4. Further, ROM2 and RAM3 have the same address space.

Next, the operation of this embodiment will be explained.

During normal operation, the processor l reads out the control program IOB copied onto the RAMa word by word and performs processing according to the read contents.

When the parity checker 4 detects a parity error in the output of the RAM 3, it reports this to the processor 1 and the CS switching circuit 5 using a CS parity error report signal 8.

When the C8 switching circuit 5 receives the CS parity error report signal 8, it applies a wait instruction signal 9 to the wait circuit 6 and also outputs, for example, I? By disconnecting AM3 from internal bus 7 and connecting ROM2 to internal bus 7,
To enable a processor 1 to read a control program IOA from a ROM 2 instead of a RAM 3. Weight circuit 6
When the wait instruction signal 9 is applied, the access speed of the processor 1 is reduced to a speed corresponding to the response speed of the ROM 2 by applying a wait signal to the processor 1.

Furthermore, when the CS parity error report signal 8 is applied, the processor 1 transfers control to the fault processing program l0A-a, which is an interrupt processing program.

At this time, the C8 switching circuit 5 reads the control program IOA from the ROM2 instead of the RAM3, so the processor 1 is able to read the control program IOA from the ROM2 instead of from the RAM3.
Failure handling will be performed according to the failure handling program l0A-a, which is a part of OA.

In handling the failure according to the failure handling program 10A-a, the processor 1 performs the CS recovery operation shown in FIG. That is, the R of one word 10B-41 in the control program IOB where the parity checker 4 detected a parity error.
One word l0A-41 in the control program IOA corresponding to the word 1013-41 is stored in the storage location on AM5.
Copy.

Further, the CS recovery operation performed in failure processing according to the failure handling program 10A-a can be as shown in FIG. That is, one word 10 in the control program IOB in which the parity checker 4 detected a parity error.
Block 3-4 of control program 10Δ stored in ROM2 is stored in block 3-4 storing B-41.
10A-4 corresponding to .

Furthermore, the CS recovery operation performed in the process according to the failure handling program 10A-a may be as shown in FIG. That is, the entire control program IOA stored in ROM2 is copied to RAM3.

When the failure processing is completed, the processor 1 sends a recovery completion report 1 to the C8 switching circuit 5. CS switching circuit 5
When the recovery completion report 11 is added, the wait instruction signal 9 is withdrawn, and, for example, the ROM 2 is disconnected from the internal bus 7 and the RAM 3 is connected to the internal bus 7, so that the processor 1 again transfers the control program I from the RAM 3.
Read out OB. Further, when the wait instruction signal 9 is withdrawn, the wait circuit 6 stops outputting the wait signal, and the access speed of the processor 1 is increased again to the RAM 3.
This corresponds to the response speed of

FIG. 6 is a block diagram of another embodiment of the present invention.
The configuration is such that an error storage circuit 12 is added to the configuration of the embodiment shown in the figure. In this figure, the same reference numerals as in FIG. 1 represent the same parts.

The error storage surface 1R12 is reset when the power is turned on, and is set by applying the CS parity error report signal 8 output from the parity checker 4 twice after the reset. Further, the error storage circuit 12 is connected to the internal bus 7 so that the processor 1 can read its contents via the internal bus 7.

When the parity checker 4 detects a parity error in the output of the RAM 3 and outputs the CS parity error report signal 8, the CS switching circuit 5 applies the wait instruction signal 9 to the wait circuit 6 as described above, and reads the control program IOA from ROM2 instead of RAM3. Further, the error storage circuit 12 is stored by outputting the CS parity error report signal 8 twice from the parity checker 4.

When the CS parity error report signal 8 is applied, the processor 1 reads the fault handling program 10A-a from the ROM 2 and performs fault processing according to the fault handling program 10A-a.

In handling a failure according to the failure handling program I0A-a, the processor 1 first checks whether or not the error register 9 circuit 12 is being sent. As mentioned above, the error storage circuit 12 is reset when the power is turned on, and is set by applying the CS parity error report signal 8 twice after the reset, so it is difficult to determine whether the error storage circuit 12 is set or not. Based on this, it can be known whether the parity checker 4 has detected a parity error in the past.

If the error storage circuit 12 is not marked, that is, if the parity error detected this time by the parity checker 4 is the first parity error detected after power is turned on, the processor 1 C
If the error storage circuit 12 is set, that is, if the parity checker 4 has detected a parity error in the past, the control program IOB stored in the RAM 3 is invalid. Considering this, the CS recovery operation shown in FIG. 5 described above is performed. In this way, if parity errors have been detected in the past, there is a high possibility that parity errors will occur frequently in the future, so it is recommended to store all control program IOA in ROM.
By copying from 2 to RAM 3, the number of occurrences of parity errors can be reduced.

When the failure processing is completed, the prosensor 1 sends a CS recovery completion report 11 to the C8 switching circuit 5.

As a result, the C8 switching circuit 5 performs the same process as described above, causing the processor 1 to read the control program IOB from the RAM 3 again.

FIG. 7 is a block diagram of another embodiment of the present invention,
Blocks 3-1 to 3 of RAM3 are added to the configuration shown in FIG.
In addition to adding an error storage circuit 12° having error storage sections 12-1 to 12-4 corresponding to -4, a parity checker 4 is also provided in place of the parity checker 4. In FIG. 7, the same reference numerals as in FIG. 1 represent the same parts.

The parity checker 4' performs a parity check on the word output from the RAM 3, and when it detects a parity error, outputs a CS parity error report signal 8, and also outputs a CS parity error report signal 8 when the parity checker 4' checks the parity of the word output from the RAM 3. The error detection signal is added to the error storage section 12-1 in the error storage circuit 12' corresponding to the error storage circuit 12' corresponding to the error detection signal 23-4. Further, each error storage section 12-1 to 12-4 in the error storage circuit 12' is reset when the power is turned on, and is set by applying an error detection signal twice from the parity checker 4' after reset. .

When the CS parity error report signal 8 is applied from the parity checker 4', the processor 1 reads the fault handling program l0A-a from the ROM 2 and performs fault handling according to the fault handling program l0A-a.

In handling a failure according to the failure handling program 10A-a, the processor 1 first selects a program in RAMa where a parity error has occurred due to an address or the like.

3-i, and then each error storage unit 12-1 to 12
-4 is set.

If multiple error storage units are set, the control program 10. B is determined to be invalid, and the CS recovery operation shown in FIG. 5 described above is performed. In addition, when all error storage units 12-1 to 12-4 are in the reset state, and only one error storage unit other than the error storage unit 12-i corresponding to the block 3-i in which the parity error is detected is sent. If there is, C as shown in Figure 3 above.
8 Perform recovery operations. Furthermore, if only the error storage unit 12-1 corresponding to the block 3-i in which the parity error was detected is set, the part 10B-i of the control program lOB stored in the block 3-i of the RAM 3 is invalid. It is determined that this is the case, and the CS recovery operation shown in FIG. 4 described above is performed.

In this way, block 3-i where a parity error has been detected
If only the error detection unit 12-4 corresponding to the block 3-i is set, by copying only to the block 3-i, parity errors can be resolved in a shorter fault processing time than in the embodiment shown in FIG. The number of occurrences can be reduced or eliminated.

〔Effect of the invention〕

As explained above, in the present invention, when a parity error occurs in the output of the RAM to which the control program is copied, the control program is stored in the ROM according to the fault handling program among the normal control programs stored in the ROM. Since the control program is copied to the RAM, failure processing operation can be guaranteed, and normal operation after failure recovery can also be guaranteed.

Further, the present invention is provided with an error storage means for storing whether or not a parity error was detected in the past, and when the error storage means stores that a parity error has been detected in the past, it is stored in the RAM. Since the control program is determined to be invalid and the entire control program stored in the ROM is copied to the RAM, the number of occurrences of parity errors can be reduced.

Furthermore, the present invention physically configures the RAM to which the control program stored in the ROM is copied from a plurality of blocks, and stores an error for each block to store whether or not a parity error has been detected in the past. A storage means is provided, and if a parity error has occurred in the same block in the past as the block in which the parity error was detected this time, the corresponding part of the control program in the ROM is copied to that block. This has the effect of reducing the number of occurrences of parity errors with a short failure processing time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
A diagram showing an example of the configuration of M3, FIGS. 3 to 5 are diagrams showing an example of failure processing, FIG. 6 is a block diagram of another embodiment of the present invention, and FIG. 7 is a block diagram of another embodiment of the present invention. FIG. 2 is a block diagram of an embodiment. In the figure, 1...processor, 2...ROM, 3
...RAM, 3-1 to 3-4...Block, 4.4
゜...Parity checker, 5...C3 (control memory)
Switching circuit, 6... Wait circuit, 7... Internal bus, 8... CS parity error report signal, 9... Wait instruction signal, IOA, IOB... Control program, 10
8-a... Trouble handling program, 12, 12°...
Error storage circuit, 12-1 to 12-4...Error storage section.

Claims (3)

[Claims] (1) A ROM in which a control program including a fault handling program is stored, a RAM to which the control program stored in the ROM is copied when the power is turned on, and a control program stored in the RAM by accessing the RAM. An information processing device comprising a processor that performs processing according to a program, a parity checker that performs a parity check on the output of the RAM, and a control program that is stored in the RAM or stored in the ROM. switching means for executing a stored fault handling program; and wait means for making the access speed of the processor correspond to the response speed of the ROM or the response speed of the RAM; When a parity error is detected by the parity checker, the switching means causes the processor to execute a fault handling program stored in the ROM, and the wait means changes the access speed of the processor to the response speed of the ROM. the processor copies at least the contents of the portion where the parity checker detects a parity error from the ROM to the RAM by executing a fault handling program stored in the ROM; When the copying from the ROM to the RAM is completed, the switching means causes the processor to transfer the data to the RAM.
The wait means executes a control program stored in the RAM, and the wait means adjusts the access speed of the processor to the RAM.
A fault handling method is characterized in that it corresponds to the response speed of. (2) A ROM in which a control program including a fault handling program is stored, a RAM to which the control program stored in the ROM is copied when the power is turned on, and a control program stored in the RAM by accessing the RAM. In an information processing device comprising a processor that performs processing according to a program, a parity checker that performs a parity check of the output of the RAM, and whether or not a parity error has been detected in the past by the parity checker. error storage means for storing an error storage means; switching means for causing the processor to execute a control program stored in the RAM or a fault handling program stored in the ROM; or a wait means for adjusting the response speed of the RAM to correspond to the response speed of the RAM, and when a parity error is detected by the parity checker, the switching means is set in the processor to be stored in the ROM. The error processing program is executed, and the wait means makes the access speed of the processor correspond to the response speed of the ROM, and the processor executes the error processing program stored in the ROM to clear the error memory. It is determined whether or not a parity error has been detected in the past by referring to the means, and if it is determined that a parity error has not been detected, only the contents of the part where the parity checker detected a parity error are Copying from the ROM to the RAM, and if it is determined that a parity error has been detected, copying the entire control program stored in the ROM to the RAM, and completing the copy from the ROM to the RAM. Accordingly, the switching means causes the processor to select the RAM.
The wait means executes a control program stored in the RAM, and the wait means adjusts the access speed of the processor to the RAM.
A fault handling method is characterized in that it corresponds to the response speed of. (3) A ROM in which a control program including a fault handling program is stored, a RAM to which the control program stored in the ROM is copied when the power is turned on, and a control program stored in the RAM by accessing the RAM. In an information processing device comprising a processor that performs processing according to a program, the RAM is physically composed of a plurality of blocks, and a parity checker that performs a parity check on the output of the RAM; an error storage means for storing whether or not a parity error has been detected in the past by the parity checker for each block; and a control program stored in the RAM of the processor or a failure processing stored in the ROM. A switching means for executing a program, and a wait means for making the access speed of the processor correspond to the response speed of the ROM or the response speed of the RAM are provided, and the parity checker detects a parity error. Upon detection, the switching means causes the processor to execute a fault handling program stored in the ROM, and the wait means makes the access speed of the processor correspond to the response speed of the ROM, By executing a fault handling program stored in the ROM, the parity checker refers to the error storage means and determines whether a parity error was detected in the past for the block of the RAM in which the parity checker detected a parity error this time. If it is determined that no parity error has been detected, the parity checker copies only the contents of the part where the parity error was detected this time from the ROM to the RAM, and eliminates the parity error. If it is determined that a parity error has been detected, the parity checker copies only the contents of the block in which the parity error has been detected from the ROM to the RAM, and by completing the copying from the ROM to the RAM, The switching means causes the processor to switch between the RAM and
The wait means executes a control program stored in the RAM, and the wait means adjusts the access speed of the processor to the RAM.
A fault handling method is characterized in that it corresponds to the response speed of.