JPH0472399B2 - - Google Patents
Info
- Publication number
- JPH0472399B2 JPH0472399B2 JP57017742A JP1774282A JPH0472399B2 JP H0472399 B2 JPH0472399 B2 JP H0472399B2 JP 57017742 A JP57017742 A JP 57017742A JP 1774282 A JP1774282 A JP 1774282A JP H0472399 B2 JPH0472399 B2 JP H0472399B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- connecting portion
- adhesive
- wiring
- connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000853 adhesive Substances 0.000 claims description 34
- 230000001070 adhesive effect Effects 0.000 claims description 34
- 229910000679 solder Inorganic materials 0.000 claims description 25
- 238000003780 insertion Methods 0.000 claims description 16
- 230000037431 insertion Effects 0.000 claims description 16
- 239000011888 foil Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 19
- 239000011889 copper foil Substances 0.000 description 18
- 239000000463 material Substances 0.000 description 13
- 239000004020 conductor Substances 0.000 description 12
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 9
- 239000000126 substance Substances 0.000 description 8
- 238000005476 soldering Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 230000001680 brushing effect Effects 0.000 description 5
- 239000003960 organic solvent Substances 0.000 description 5
- 238000007639 printing Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000003973 paint Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000004381 surface treatment Methods 0.000 description 3
- 238000011282 treatment Methods 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000007872 degassing Methods 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000011176 pooling Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910000807 Ga alloy Inorganic materials 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 229960002089 ferrous chloride Drugs 0.000 description 1
- -1 for example Substances 0.000 description 1
- 230000008642 heat stress Effects 0.000 description 1
- NMCUIPGRVMDVDB-UHFFFAOYSA-L iron dichloride Chemical compound Cl[Fe]Cl NMCUIPGRVMDVDB-UHFFFAOYSA-L 0.000 description 1
- 238000010943 off-gassing Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- KCTAWXVAICEBSD-UHFFFAOYSA-N prop-2-enoyloxy prop-2-eneperoxoate Chemical compound C=CC(=O)OOOC(=O)C=C KCTAWXVAICEBSD-UHFFFAOYSA-N 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、電気部品挿入部においてその部品リ
ード線及び配線パターン間の接続を確実になした
高信頼性を有する多層配線基板の製造方法に係わ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a highly reliable multilayer wiring board in which connection between component lead wires and wiring patterns is ensured in an electrical component insertion portion.
本発明の理解を容易にするために、本出願人が
先に提案した多層配線基板について述べる。この
多層配線基板は、第1図に示すように絶縁基材1
の一面に導電箔例えば銅箔による第1の配線パタ
ーン2を形成して後、第1の配線パターン2の接
続部2aを除いて所望の絶縁樹脂層3を形成し、
さらにこの上の裏面に接着剤4を付した導電箔例
えば銅箔を積層合体し、この銅箔を選択エツチン
グして第2の配線パターン5を形成し、次に第2
の配線パターン5の接続部5aに設けられた開口
部内の接着剤4を除去し、さらにその開口部内に
臨む第1の配線パターン2の接続部2aの中央を
貫通する如く電気部品挿入孔6をプレス等にて穿
設して構成され、その後、この挿入孔6に電気部
品7のリード8を挿入して半田、その他等の導電
性物質9にてリード8、接続部2a及び5aを電
気的に接続するようになされる。この多層配線基
板は従来の多層配線基板に比して高密度回路が得
られること、安価に製造できること等の利点を有
する。 In order to facilitate understanding of the present invention, a multilayer wiring board previously proposed by the present applicant will be described. This multilayer wiring board has an insulating base material 1 as shown in FIG.
After forming a first wiring pattern 2 made of conductive foil, for example, copper foil on one surface, a desired insulating resin layer 3 is formed except for the connecting portion 2a of the first wiring pattern 2,
Furthermore, a conductive foil such as a copper foil with an adhesive 4 applied to the back surface thereof is laminated and combined, this copper foil is selectively etched to form a second wiring pattern 5, and then a second wiring pattern 5 is formed.
The adhesive 4 in the opening provided in the connection part 5a of the first wiring pattern 5 is removed, and the electrical component insertion hole 6 is inserted so as to pass through the center of the connection part 2a of the first wiring pattern 2 facing into the opening. After that, the lead 8 of the electrical component 7 is inserted into the insertion hole 6, and the lead 8 and the connecting parts 2a and 5a are electrically connected with a conductive material 9 such as solder or the like. is made to connect to. This multilayer wiring board has advantages over conventional multilayer wiring boards, such as being able to provide high-density circuits and being manufactured at low cost.
しかるに、この場合電気部品挿入孔6が形成さ
れた配線パターン2及び5の接続部分において
は、第2図の拡大図面で示すように上層の配線パ
ターン5の接続部5aが挿入孔6をとり囲むよう
に閉じた内周面を有する環状に形成されている。
このために、上層の配線パターン5を形成して後
に、接続部5aの開口部に臨む接着剤4を有機溶
剤(剥離液)によつて膨潤させ、あるいはその後
機械的ブラツシングによつて剥離する(所謂下層
の配線パターンの接続部2a上面の活性化)とき
に、剥離液の溜まりによる接着剤再溶解汚染が生
じ、また周壁の存在によつて開口部分における機
械的ブラツシングが満足に行えず、接続部2a上
面の活性化が不充分となり、結果として導電性物
質9との電気的接触が不充分となり電気抵抗が高
くなる懼れがあつた。また例えば溶融半田デイツ
プにより電導性物質9を充填する場合、第2図に
示すように開口部内に空気溜まり10が生じ電導
性物質9の充填即ち半田付けを阻害し、さらに溶
融半田温度にもとづき接続部5aの接着剤4に残
留しているガス、水分、気泡による熱時のストレ
スが導電性物質9に悪影響を与える懼れがあつ
た。 However, in this case, at the connection portion between the wiring patterns 2 and 5 where the electrical component insertion hole 6 is formed, the connection portion 5a of the upper layer wiring pattern 5 surrounds the insertion hole 6, as shown in the enlarged drawing of FIG. It is formed into an annular shape with a closed inner peripheral surface.
For this purpose, after forming the upper layer wiring pattern 5, the adhesive 4 facing the opening of the connection portion 5a is swollen with an organic solvent (removal liquid), or is then removed by mechanical brushing ( When the upper surface of the connection part 2a of the so-called lower layer wiring pattern is activated, adhesive re-dissolution contamination occurs due to pooling of the stripping liquid, and mechanical brushing cannot be performed satisfactorily at the opening due to the presence of the peripheral wall, resulting in poor connection. There was a fear that the activation of the upper surface of the portion 2a would be insufficient, and as a result, the electrical contact with the conductive substance 9 would be insufficient and the electrical resistance would increase. For example, when filling the conductive substance 9 with a molten solder dip, an air pocket 10 is generated in the opening as shown in FIG. There was a fear that stress during heat due to gas, moisture, and bubbles remaining in the adhesive 4 of the portion 5a would adversely affect the conductive material 9.
本発明は、上述の問題点を改善し、さらに信頼
性の高い多層配線基板の製造方法を提供するもの
である。 The present invention improves the above-mentioned problems and provides a method for manufacturing a multilayer wiring board with higher reliability.
以下、図面を用いて本発明による多層配線基板
の製造方法の実施例について詳述する。 Embodiments of the method for manufacturing a multilayer wiring board according to the present invention will be described in detail below with reference to the drawings.
第3図は本発明の一実施例で、工程順に示すも
のである。本例においては、第3図Aに示すよう
に絶縁基材(例えば紙フエノール、紙エポキシ等
の硬質絶縁基板、又は可撓性絶縁基板も可)21
の一主面に導電箔例えば、銅箔を被着した銅張積
層板を用意し、その銅箔を選択エツチングして第
1の配線パターン22を形成する。このとき、第
1の配線パターン22と次に形成する絶縁層との
密着性を良くするために、第1の配線パターン2
2に対して表面処理を施すを可とする。表面処理
としては黒化処理の他に表面にCuO,Cu2O等の
酸化膜を形成する化学的粗面化処理、あるいはサ
ンドブラスト又はブラツシングによる機械的粗面
化処理等がある。次に、第3図Bに示すように第
1の配線パターン22を含む基材21上に例えば
紫外線硬化型の樹脂による絶縁層23を第1の配
線パターン22の接続部(図示の例では略円形
状)22aを除いて印刷により形成する。この絶
縁層23の形成に際してはスキージを往復させる
所謂往復印刷によつて行う。これによれば第1の
配線パターン22の肩の部分が陰になつても往復
塗りのために陰の部分も充分に被着し、ピンホー
ルのない絶縁層23が形成できる。 FIG. 3 shows an embodiment of the present invention, which is shown in the order of steps. In this example, an insulating substrate (for example, a rigid insulating substrate such as paper phenol or paper epoxy, or a flexible insulating substrate is also possible) 21
A copper-clad laminate having a conductive foil, such as copper foil, coated on one main surface of the substrate is prepared, and the first wiring pattern 22 is formed by selectively etching the copper foil. At this time, in order to improve the adhesion between the first wiring pattern 22 and the insulating layer to be formed next, the first wiring pattern 22 is
It is possible to apply surface treatment to 2. In addition to blackening treatment, surface treatments include chemical roughening treatment to form an oxide film of CuO, Cu 2 O, etc. on the surface, mechanical roughening treatment by sandblasting or brushing, and the like. Next, as shown in FIG. 3B, an insulating layer 23 made of, for example, an ultraviolet curable resin is placed on the base material 21 including the first wiring pattern 22 at the connecting portion of the first wiring pattern 22 (not shown in the illustrated example). 22a (circular shape) are formed by printing. The insulating layer 23 is formed by so-called reciprocating printing in which a squeegee is moved back and forth. According to this, even if the shoulder portion of the first wiring pattern 22 is in the shadow, the shadow portion is sufficiently coated due to the reciprocal coating, and an insulating layer 23 without pinholes can be formed.
次に、第3図Cに示すように裏面に半硬化状態
の接着剤24を付した導電箔例えば銅箔25をロ
ールラミネート装置(例えば180℃に熱せられた
対の熱ロール間に挿通せしめる)を用いて基材2
1上に積層合体する。この半硬化状態の接着剤2
4は、後に選択エツチングする導電箔(例えば銅
箔)のエツチング液におかされず、有機溶剤に溶
解し、最終的に電子線、熱等の硬化エネルギーを
加えることによつて3次元硬化する性質を有する
ものである。 Next, as shown in FIG. 3C, a conductive foil such as a copper foil 25 with a semi-cured adhesive 24 applied to the back side is inserted into a roll laminating device (for example, between a pair of hot rolls heated to 180° C.). Base material 2 using
Laminated and combined on 1. This semi-cured adhesive 2
4 is the property of a conductive foil (such as a copper foil) to be selectively etched later, which is not affected by the etching solution, but dissolves in an organic solvent, and is finally three-dimensionally cured by applying curing energy such as an electron beam or heat. It has the following.
次に、第3図Dに示すように銅箔25に対して
塩化第1鉄の水溶液(エツチング液)を用いて選
択エツチングを施し、第2の配線パターン26を
形成する。このとき第2の配線パターン26の第
1の配線パターン22との接続部26aは閉じた
内周面を有する形状(所謂環状)ではなく、図示
するように第1の配線パターン22の接続部22
aに部分的に重なるように例えば図示の例では略
半円形状に形成する。この銅箔25の選択エツチ
ング時、裏面の接着剤24は除去されない。 Next, as shown in FIG. 3D, selective etching is performed on the copper foil 25 using an aqueous solution of ferrous chloride (etching solution) to form a second wiring pattern 26. At this time, the connecting portion 26a of the second wiring pattern 26 with the first wiring pattern 22 does not have a shape having a closed inner circumferential surface (so-called annular shape), but as shown in the figure, the connecting portion 26a of the first wiring pattern 22
For example, in the illustrated example, it is formed into a substantially semicircular shape so as to partially overlap with a. During this selective etching of the copper foil 25, the adhesive 24 on the back surface is not removed.
次に、第3図Eに示すように両接続部22a及
び26aに対応する部分を除いてソルダーレジス
ト層27を印刷によつて被着形成する。このソル
ダーレジスト層27としては例えばエポキシアク
リレート系の如き紫外線硬化型の樹脂を用いるこ
とができ、接着剤24の剥離に使用する有機溶剤
におかされない性質を有する。そして、このソル
ダーレジスト層27及び第2の配線パターン26
の接続部26a即ち銅箔をマスクとして第1の配
線パターン22の接続部22aに対応する部分の
露出する半硬化状態の接着剤24を有機溶剤(例
えば塩化メチレンの溶液)で選択的に溶解剥離
し、接続部22aの表面を露にする。 Next, as shown in FIG. 3E, a solder resist layer 27 is formed by printing except for the portions corresponding to both the connecting portions 22a and 26a. This solder resist layer 27 can be made of an ultraviolet curing resin such as epoxy acrylate resin, and has a property that it is not affected by the organic solvent used to peel off the adhesive 24. Then, this solder resist layer 27 and the second wiring pattern 26
Using the connecting portion 26a of the first wiring pattern 22, that is, the copper foil as a mask, the exposed semi-hardened adhesive 24 of the portion corresponding to the connecting portion 22a of the first wiring pattern 22 is selectively dissolved and peeled off using an organic solvent (for example, a methylene chloride solution). Then, the surface of the connecting portion 22a is exposed.
次に、第1の配線パターン22の接続部22a
の中央部に、この場合少くとも第2の配線パター
ン26の接続部26aが重ならない部分33を含
むように、プレス等の機械的手段により基材21
を貫通するように電気部品挿入孔28を形成す
る。次いで、半硬化状態の接着剤24を電子線硬
化、又は熱硬化して第3図Fに示す多層配線基板
29を得る。なお、挿入孔28は第3図Fの工程
で行つたが、その他第3図Aの銅箔の選択エツチ
ング前に予め挿入孔28を形成して置くことも良
い。これは、プレスで孔あけするときの衝撃で接
続部22aの基材21に対する接着強度が低下す
るのを防止するためであり、銅箔が基材21の全
面に被着された状態のときにプレス孔あけすれば
接着強度の低下は回避される。 Next, the connection portion 22a of the first wiring pattern 22
The base material 21 is pressed by mechanical means such as pressing so that the central part thereof includes at least a portion 33 where the connecting portion 26a of the second wiring pattern 26 does not overlap.
An electrical component insertion hole 28 is formed so as to penetrate therethrough. Next, the semi-cured adhesive 24 is cured by electron beam or heat to obtain a multilayer wiring board 29 shown in FIG. 3F. Although the insertion hole 28 was formed in the process shown in FIG. 3F, it is also possible to form the insertion hole 28 in advance before the selective etching of the copper foil shown in FIG. 3A. This is to prevent the adhesive strength of the connecting portion 22a to the base material 21 from decreasing due to the impact when drilling with a press, and when the copper foil is coated on the entire surface of the base material 21. If press holes are made, a decrease in adhesive strength can be avoided.
その後、第3図Gに示すように電気部品30の
リード線31を挿入孔28内に挿入し、リード線
31と両接続部22a及び26aの三者を導電性
物質32によつて電気的に接続する。導電性物質
32としては、半田(半田フロー、手半田付け、
ソルダークリームによるリフロー、ソルダーコー
タレベラー)、ガリウム合金(当初作業温度にお
いてペースト状をなし、その後経時的に合金化し
凝固する性質を有する)、銀ペイント、カーボン
ペイント、銅ペイント等による導電材を用い得
る。 Thereafter, the lead wire 31 of the electrical component 30 is inserted into the insertion hole 28 as shown in FIG. Connecting. The conductive substance 32 may be solder (solder flow, manual soldering,
Conductive materials such as reflow with solder cream, solder coater leveler), gallium alloy (which has the property of forming a paste at initial working temperature and then becoming alloyed and solidifying over time), silver paint, carbon paint, copper paint, etc. can be used. .
かかる方法によつて製造した多層配線基板29
によれば、電気部品挿入孔におけるリード線と配
線パターン間の接続部分において、上層の配線パ
ターン26の接続部26aが環状でなく部分的に
下層の配線パターン22の接続部22aに重なる
如き半円形状に形成されているので、リード線と
の接続部分27の接着剤24の剥離に際して剥離
液の溜まりがなく、又機械的ブラツシングも充分
に行え、確実に接着剤24の剥離ができる。その
結果、下層の接続部22aの上面がきれいに露わ
れ、導電性物質32との電気的接触が良好とな
る。この場合、第1、第2の配線パターン22,
26の両接続部22a,26aは、半硬化接着剤
により積層合体されるので、両接続部22a,2
6a間の絶縁層をきわめて薄く(15〜30μm程度)
形成することができ、このためこれらは導電性物
質32によりきわめて容易かつ確実に電気的接続
が行なわれる。溶融半田デイツプで導電性物質3
2を付ける場合には下層の接続部分における空気
が逃げ易くなり半田上りが良く、良好な半田付け
が出来る。従つて、例えば自動ふん流半田付装置
を用いた場合でも両接続部22a,26a間で半
田が泣き分かれてしまうことがなく信頼性が向上
する。同時に、上層の接続部26aが小面積のた
めに、その下の接着剤24に残留するガス、水
分、気泡も少なく、従つてこれらによる熱時のス
トレスの導電性物質32に与えられる影響が少な
くなる。さらに接続部26aを第1のように環状
にした場合には、空気の逃げを考慮して内径dが
決まり、またその幅aも0.3mm以上は必要なため、
結果として接続部26aを小さくするにも限界が
あつた。しかし、本実施例のように形成した接続
部26aではこのような制限がないので、より高
密度の配線パターンが形成できる。加えて、ソル
ダーレジスト層27及び第2の配線パターン26
の接続部22aをマスクとして第1の配線パター
ン22の接続部22aに対応する部分の露出する
接着剤24を除去させて第1の配線パターン22
の接続部22aを露出することから、この露出部
分を微細かつ任意の形状に加工することが可能に
なる。 Multilayer wiring board 29 manufactured by such method
According to the above, in the connection portion between the lead wire and the wiring pattern in the electrical component insertion hole, the connection portion 26a of the upper layer wiring pattern 26 is not annular but semicircular such that it partially overlaps the connection portion 22a of the lower layer wiring pattern 22. Since the shape is formed, there is no pooling of the removing liquid when removing the adhesive 24 from the connecting portion 27 with the lead wire, and sufficient mechanical brushing can be performed, so that the adhesive 24 can be removed reliably. As a result, the upper surface of the lower connecting portion 22a is clearly exposed, and electrical contact with the conductive substance 32 is improved. In this case, the first and second wiring patterns 22,
Both the connecting parts 22a, 26a of 26 are laminated together using a semi-cured adhesive, so both the connecting parts 22a, 26a
The insulation layer between 6a is extremely thin (about 15 to 30 μm).
Therefore, the electrical connection can be made very easily and reliably with the conductive material 32. Conductive material 3 with molten solder dip
When attaching the number 2, air in the lower layer connection part can easily escape, the solder rises well, and good soldering can be achieved. Therefore, even when an automatic flow soldering device is used, for example, solder does not separate between the connecting portions 22a and 26a, and reliability is improved. At the same time, since the upper layer connecting portion 26a has a small area, there is less gas, moisture, and air bubbles remaining in the adhesive 24 below it, and therefore the effects of heat stress caused by these on the conductive material 32 are reduced. Become. Furthermore, when the connecting part 26a is made into an annular shape as in the first example, the inner diameter d is determined by taking air escape into account, and the width a is also required to be at least 0.3 mm.
As a result, there is a limit to how small the connecting portion 26a can be made. However, since the connection portion 26a formed as in this embodiment does not have such restrictions, a higher density wiring pattern can be formed. In addition, the solder resist layer 27 and the second wiring pattern 26
The exposed adhesive 24 of the first wiring pattern 22 corresponding to the connection part 22a is removed using the connection part 22a of the first wiring pattern 22 as a mask.
Since the connecting portion 22a is exposed, it becomes possible to process this exposed portion into a fine and arbitrary shape.
尚、上層の接続部26aの形状としては第3図
及び第4図に示す半円形状の他に、例えば第5図
の幅狭にした形状、あるいは第6図の形状でもよ
く、要は環状でなく下層の接続部22aと一部重
なるものであれば任意形状を選ぶことができる。 In addition to the semicircular shape shown in FIGS. 3 and 4, the shape of the upper layer connecting portion 26a may be, for example, the narrowed shape shown in FIG. 5 or the shape shown in FIG. Instead, any shape can be selected as long as it partially overlaps with the lower connecting portion 22a.
第7図は本発明の他の実施例である。本例にお
いては、第7図Aに示すように絶縁基材21の一
主面に上面と同様に例えば銅箔による第1の配線
パターン22を形成し、この配線パターン22に
表面処理を施して後、第7図Bに示すように第1
の配線パターン22の接続部22a及び之に隣接
する基材21の一部21aを除いて絶縁樹脂層2
3を印刷により形成する。この基材21上の全面
に第7図Cに示すように半硬化状態の接着剤24
を付した例えば銅箔25を積層合体し、次いで、
この銅箔25を選択エツチングして第2の配線パ
ターン26を形成する。この第2の配線パターン
26の形成において、その接続部26aは第7図
Dに示すように下層の第1の配線パターン22の
接続部22a上には重ならないように、即ち接続
部22aに隣接する基材21の部分21aに形成
する。従つて両接続部22a及び26aは段差を
生じることなく略面一の状態で形成される。次
に、第7図Eに示すように両接続部22a及び2
6aを除いてソルダーレジスト層27を印刷によ
つて被着形成し、ソルダーレジスト層27及び上
層の第2の配線パターン26の接続部26a即ち
銅箔をマスクとして、接続部22a上の半硬化状
態の接着剤24を有機溶剤により溶解剥離する。
次に下層の接続部22aの中央部にプレス等によ
つて基材21を貫通する電気部品挿入孔28を形
成する。そして接着剤24を硬化する。その後、
第7図Gに示すように電気部品30のリード線3
1を挿入孔28内に挿入し、リード線31と両接
続部22a及び26aを導電性物質32によつて
電気的に接続する。 FIG. 7 shows another embodiment of the invention. In this example, as shown in FIG. 7A, a first wiring pattern 22 made of copper foil, for example, is formed on one main surface of the insulating base material 21 in the same way as on the upper surface, and this wiring pattern 22 is subjected to surface treatment. After that, as shown in Figure 7B, the first
The insulating resin layer 2 except for the connecting portion 22a of the wiring pattern 22 and a portion 21a of the base material 21 adjacent thereto.
3 is formed by printing. As shown in FIG. 7C, a semi-cured adhesive 24 is applied to the entire surface of this base material 21.
For example, copper foils 25 with markings are laminated and combined, and then,
This copper foil 25 is selectively etched to form a second wiring pattern 26. In forming the second wiring pattern 26, the connecting portion 26a is arranged so as not to overlap the connecting portion 22a of the first wiring pattern 22 in the lower layer, that is, adjacent to the connecting portion 22a, as shown in FIG. 7D. It is formed on the portion 21a of the base material 21. Therefore, both the connecting portions 22a and 26a are formed substantially flush with each other without creating a step. Next, as shown in FIG. 7E, both the connecting portions 22a and 2
The solder resist layer 27 is formed by printing except for the solder resist layer 27 and the upper layer second wiring pattern 26, and using the connecting portion 26a of the solder resist layer 27 and the upper layer second wiring pattern 26, that is, the copper foil as a mask, the semi-cured state on the connecting portion 22a is formed. The adhesive 24 is dissolved and peeled off using an organic solvent.
Next, an electrical component insertion hole 28 penetrating the base material 21 is formed in the center of the lower connecting portion 22a by pressing or the like. Then, the adhesive 24 is cured. after that,
As shown in FIG. 7G, the lead wire 3 of the electrical component 30
1 is inserted into the insertion hole 28, and the lead wire 31 and both connecting portions 22a and 26a are electrically connected by a conductive substance 32.
かかる方法により製造される多層配線基板34
は、その電気部品挿入孔におけるリード線と配線
パターン間の接続部分において両接続部22a及
び26aが略面一の状態で形成されているため
に、第3図の実施例の場合と同様に一方の接続部
22a上の接着剤24の剥離が容易に且つ確実に
行われ、接続部22aの表面がきれいに露われ、
導電性物質32との電気的接続が良好となる。ま
た、両接続部22a,26a間にはほとんど段差
が生じないのでこれらは導電性物質32によりき
わめて容易かつ確実に電気的接続が行われる。さ
らに溶融半田デイツプに際しても空気のたまりが
なく半田上りが良く、また導電性物質に対する熱
時のストレス(接着剤24に残留するガス、水
分、気泡によるもの)の影響も少なくなる。その
他の構成及び作用については上記実施例と同一で
あるので詳細な説明を省略する。 Multilayer wiring board 34 manufactured by such method
Since both the connecting portions 22a and 26a are formed substantially flush with each other at the connecting portion between the lead wire and the wiring pattern in the electrical component insertion hole, one of the connecting portions 22a and 26a is formed on the same plane as in the embodiment shown in FIG. The adhesive 24 on the connecting portion 22a is easily and reliably peeled off, and the surface of the connecting portion 22a is clearly exposed.
Electrical connection with the conductive substance 32 is improved. Moreover, since there is almost no difference in level between the two connecting portions 22a and 26a, the electrical connection between them can be made extremely easily and reliably by the conductive material 32. Furthermore, there is no air accumulation during molten solder dipping, resulting in good solder finish, and the effect of thermal stress on the conductive material (due to gas, moisture, and air bubbles remaining in the adhesive 24) is reduced. The other configurations and operations are the same as those of the above embodiment, so detailed explanations will be omitted.
第8図及び第9図は本発明の更に他の実施例で
ある。なお、第3図と対応する部分には同一符号
を付す。本例においては、第1の配線パターンに
対応する下層の導電箔パターンを単なるダミーパ
ターンとし、この導電箔パターン41において電
気部品挿入孔28を形成すると共に、導電箔パタ
ーン41上に存するように上層の配線パターン2
6の接続部26aを形成する。すなわち、この導
電箔パターン41は必ずしも他の配線パターンに
つながつている必要はなく、他から分離独立した
所謂ダミーパターンとするものである。この様
に、配線パターンの接続部26a下にダミーの導
電箔パターン41が存在すると、電気部品30の
リード線31を半田付けするための溶融半田デイ
ツプ時において、絶縁基材21からの脱ガスを遮
蔽することが出来、脱ガスの接続部26aに対す
る影響が回避され、銅箔による接続部26aの接
着力が向上する。因みに脱ガスの影響を受けると
銅箔の接着力は低下する。なお、接続部26a以
外の配線パターンの部分では、その上にソルダー
レジスト層27が被着されているのでその部分で
の配線パターンの接着力の低下は起こらない。こ
のことは前述した第3図〜第6図の構成において
も同様の効果を奏する。また配線パターンの接続
部が大面積のパターンの場合にも、その下にダミ
ーの導電箔パターンを形成すれば同様の効果が期
待出来る。 FIGS. 8 and 9 show still other embodiments of the present invention. Note that parts corresponding to those in FIG. 3 are given the same reference numerals. In this example, the lower layer conductive foil pattern corresponding to the first wiring pattern is a mere dummy pattern, and the electric component insertion hole 28 is formed in this conductive foil pattern 41, and the upper layer wiring pattern 2
6 connection portions 26a are formed. That is, the conductive foil pattern 41 does not necessarily need to be connected to other wiring patterns, but is a so-called dummy pattern that is separate and independent from the others. In this way, the presence of the dummy conductive foil pattern 41 under the connection portion 26a of the wiring pattern prevents degassing from the insulating base material 21 during molten solder dip for soldering the lead wire 31 of the electrical component 30. It can be shielded, the influence of degassing on the connection part 26a is avoided, and the adhesive strength of the connection part 26a by the copper foil is improved. Incidentally, the adhesive strength of copper foil decreases when affected by outgassing. In addition, since the solder resist layer 27 is deposited on the portions of the wiring pattern other than the connecting portion 26a, the adhesive strength of the wiring pattern does not decrease in those portions. This produces similar effects in the configurations shown in FIGS. 3 to 6 described above. Furthermore, even if the connection portion of the wiring pattern has a large area, the same effect can be expected by forming a dummy conductive foil pattern underneath.
尚、上例においては絶縁樹脂層23を設けた構
成であるが、絶縁樹脂層23を省略して接着剤2
4をもつて上下配線パターン22及び26間を絶
縁する絶縁層とすることも可能である。 In the above example, the insulating resin layer 23 is provided, but the insulating resin layer 23 is omitted and the adhesive 2 is used.
4 can also be used as an insulating layer that insulates between the upper and lower wiring patterns 22 and 26.
以上述べたように本発明によれば、上層の配線
パターンの接続部と下層の配線パターンの接続部
とが部分的に重なるか若しくは隣接するように構
成されるので、リード線との接続部分の接着剤の
剥離に際して剥離液のたまりがなく、また機械的
ブラツシングも充分に行え、確実に接着剤の剥離
ができる。その結果、下層の接続部の上面がきれ
いに露われ、導電性物質との電気的接触が良好と
なる。 As described above, according to the present invention, the connection portion of the upper layer wiring pattern and the connection portion of the lower layer wiring pattern are configured to partially overlap or be adjacent to each other, so that the connection portion with the lead wire is When removing the adhesive, there is no accumulation of release liquid, and sufficient mechanical brushing can be performed, so that the adhesive can be removed reliably. As a result, the upper surface of the lower layer connection portion is clearly exposed, and electrical contact with the conductive material is improved.
この場合、第1、第2の配線パターンの両接続
部は、半硬化接着剤により積層合体されるので、
両接続部間の絶縁層をきわめて薄く(15〜30μm
程度)に形成することができ、このためこれらは
導電性物質によりきわめて容易かつ確実に電気的
接続が行われる。 In this case, both the connection parts of the first and second wiring patterns are laminated together using a semi-cured adhesive, so
The insulation layer between both connections is extremely thin (15 to 30 μm).
Therefore, they can be electrically connected very easily and reliably using a conductive material.
また、溶融半田デイツプで導電性物質を付ける
場合には下層の接続部分における空気が逃げ易く
なり半田上りが良く、良好な半田付けができる。
従つて、例えば自動ふん流半田付装置を用いた場
合でも両接続部間で半田が泣き分かれてしまうこ
とがなく信頼性が向上する。 Furthermore, when a conductive substance is attached using a molten solder dip, air in the lower layer connection portion can easily escape, resulting in good soldering and good soldering.
Therefore, even when an automatic flow soldering device is used, for example, solder does not separate between the two connecting portions, and reliability is improved.
さらに、上層の接続部が小面積のため、その下
の接着剤に残留するガス、水分、気泡も少なく、
従つてこれらによる熱時のストレスの導電性物質
に与える影響が少なくなる。 Furthermore, because the upper layer connection area is small, there is less gas, moisture, and air bubbles remaining in the adhesive underneath.
Therefore, the influence of stress caused by heat on the conductive material is reduced.
さらにまた、本発明によれば空気の逃げが良い
ことから、接続部を小さくすることができ、より
高密度の配線パターンを形成することができる。 Furthermore, according to the present invention, since air escape is good, the connecting portion can be made smaller and a higher density wiring pattern can be formed.
加えて、ソルダーレジスト層及び第2の配線パ
ターンをマスクとして第1の配線パターンの接続
部に対応する部分の露出する半硬化接着剤を除去
させて第1の配線パターンの接続部を露出するこ
とから、この露出部分を微細かつ任意の形状に加
工することが可能になる。 In addition, using the solder resist layer and the second wiring pattern as a mask, the exposed semi-cured adhesive in the portion corresponding to the connection part of the first wiring pattern is removed to expose the connection part of the first wiring pattern. Therefore, it becomes possible to process this exposed portion into a fine and arbitrary shape.
第1図は従来の多層配線基板の一例を示す一部
断面とした斜視図、第2図はその接続部分の断面
図、第3図は本発明多層配線基板の製造方法の一
実施例を示す工程順の一部断面とした斜視図、第
4図乃至第6図は夫々その接続部の形状例を示す
要部の平面図、第7図は本発明の他の実施例を示
す工程順の一部断面とした斜視図、第8図及び第
9図は本発明のさらに他の実施例の要部を示す断
面図及び平面図である。
21は絶縁基材、22,26は配線パターン、
28は電気部品挿入孔、30は電気部品、31は
リード線、32は導電性物質、41は導電箔パタ
ーンである。
FIG. 1 is a partially cross-sectional perspective view showing an example of a conventional multilayer wiring board, FIG. 2 is a cross-sectional view of its connecting portion, and FIG. 3 is an embodiment of the method for manufacturing the multilayer wiring board of the present invention. FIG. 4 to FIG. 6 are plan views of main parts showing examples of the shapes of the connecting parts, and FIG. 7 is a perspective view of the process order showing another embodiment of the present invention. The partially sectional perspective view, FIGS. 8 and 9 are a sectional view and a plan view showing essential parts of still another embodiment of the present invention. 21 is an insulating base material, 22 and 26 are wiring patterns,
28 is an electrical component insertion hole, 30 is an electrical component, 31 is a lead wire, 32 is a conductive material, and 41 is a conductive foil pattern.
Claims (1)
成した絶縁基板上に、第1の配線パターンの接続
部を除いて絶縁層を形成する工程と、 該絶縁基板上に、裏面に半硬化接着剤を付した
第2の導電箔を積層合体させる工程と、 前記第2の導電箔を前記第1の配線パターンの
接続部に部分的に重なるか若しくは隣接するよう
に選択的にエツチングして第2の配線パターンを
形成する工程と、 前記第1と第2の配線パターンの両接続部に対
応する部分を除いて前記第2の配線パターン上に
ソルダーレジスト層を形成する工程と、 該ソルダーレジスト層及び前記第2の配線パタ
ーンをマスクとして前記第1の配線パターンの接
続部に対応する部分の露出する半硬化接着剤を除
去させて第1の配線パターンの接続部を露出させ
る工程と、 前記第1の配線パターンの接続部に電気部品挿
入孔を形成する工程とを有することを特徴とする
多層配線基板の製造方法。[Claims] 1. A step of forming an insulating layer on an insulating substrate on which a first wiring pattern made of a first conductive foil is formed, excluding the connection portion of the first wiring pattern; , a step of laminating and combining a second conductive foil with a semi-cured adhesive applied to the back surface; and selecting the second conductive foil so as to partially overlap or be adjacent to the connecting portion of the first wiring pattern. forming a solder resist layer on the second wiring pattern except for a portion corresponding to both the connection portions of the first and second wiring patterns; using the solder resist layer and the second wiring pattern as a mask to remove the semi-cured adhesive exposed in the portion corresponding to the connection part of the first wiring pattern to connect the connection part of the first wiring pattern; A method for manufacturing a multilayer wiring board, comprising: exposing the first wiring pattern; and forming an electrical component insertion hole in a connecting portion of the first wiring pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57017742A JPS58134498A (en) | 1982-02-05 | 1982-02-05 | Multilayer circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57017742A JPS58134498A (en) | 1982-02-05 | 1982-02-05 | Multilayer circuit board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58134498A JPS58134498A (en) | 1983-08-10 |
JPH0472399B2 true JPH0472399B2 (en) | 1992-11-18 |
Family
ID=11952197
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57017742A Granted JPS58134498A (en) | 1982-02-05 | 1982-02-05 | Multilayer circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58134498A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5632480B2 (en) * | 1975-02-10 | 1981-07-28 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59774Y2 (en) * | 1979-08-20 | 1984-01-10 | 松下電器産業株式会社 | printed wiring board |
-
1982
- 1982-02-05 JP JP57017742A patent/JPS58134498A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5632480B2 (en) * | 1975-02-10 | 1981-07-28 |
Also Published As
Publication number | Publication date |
---|---|
JPS58134498A (en) | 1983-08-10 |
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