JPH0462152B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a frequency detection circuit, and is particularly applicable to a digital recording/reproducing system to detect information recorded using a predetermined modulation method in which maximum and minimum inversion periods are determined. The present invention relates to a frequency detection circuit that detects a frequency when demodulating a signal.

[Technical background of the invention] The so-called PCM method (Pulse Cord Modulation System) converts signals that are inherently analog information, such as acoustic signals (audio signals), into digital signals.
Its use has become more active in recent years due to its advantages such as improved quality of recording and reproduction signals. When recording an audio signal according to the PCM method, an analog signal is sampled, quantized, and encoded, and finally a digital signal having binary levels is stored on an information recording medium such as an optical disk (DAD:
(referred to as a Digital Audio Disk).
At this time, the signal is subjected to error correction processing and then demodulated, and the modulation method is, for example, EFM.
(Eight to Fourteen Modulation), 3PM (3
Position Modulation) etc. are applied, and the maximum and minimum inversion periods are determined.

In order to detect the above-mentioned inversion period, generally, after aligning the phases of the input pulse signal and the demodulated clock signal, the pulse edge intervals of the input signal are counted based on the demodulated clock signal, and the maximum count in a predetermined period is The value is detected as the maximum inversion period of the input signal.

FIG. 1 shows an example of the configuration of a conventional detection circuit. That is, the pulse edge of the input signal 2 is detected by the edge detection circuit 4 and is supplied to the counter 6. The counter 6 counts the interval between detected pulse edges of the input signal 2 based on the demodulated clock signal 8. Count value 1 of counter 6
0 is supplied to a comparator 12, where, for example, a maximum inversion period (Tmax) register 14
is compared with the register value 16 from . In the comparison process by the comparator 12, if the counter value 10 of the counter 6 is larger than the register value 16 of the Tmax register 14, the counter value 10 of the counter 6 is loaded into the Tmax register 14 as a new register value 18. Through this operation, the maximum inversion cycle value (Tmax) for a predetermined period is stored in register 1.
It can be stored in 4.

The Tmax register 14 is connected to the digital integration circuit 20. The reason for this is to prevent erroneous detection of the maximum inversion period value Tmax due to adverse effects such as noise and burst errors. That is, the output terminal of the Tmax register 14 is connected to the N addition register 24 via the adder 22, and the addition register value 26 of the N addition register 24 is supplied to the adder 22 and the 1/N divider 28. Ru.
Therefore, it corresponds to the maximum reversal period value for any period.
The frequency ratio output 30 from the Tmax register 14 and the addition register value 26 are subjected to N addition processing, and the addition result is input to the N addition register 24 again. After repeating the addition process N times in this manner, the register value 26 is 1/N and this is output as the final maximum inversion period value.

[Problems with background technology]

According to the conventional frequency detection circuit configured as described above, the digital integration circuit 20 is provided in order to suppress the adverse effects of noise etc., but this increases the number of circuit elements and makes the overall configuration undesirably complicated. It has the disadvantage that it becomes This problem becomes even more serious especially when the entire device is integrated into an IC and is housed on a chip. Furthermore, when a burst error occurs, the input signal is lost for a long time, so the inversion period is detected to be extremely long, and when this detection result is fed to the integrator circuit, the above-mentioned integration effect is not fully realized. As a result,
This has the disadvantage that correct frequency detection cannot be performed.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and its purpose is to develop a frequency that can simplify the circuit configuration and minimize the occurrence of false detections due to burst errors, etc. To provide a detection circuit.

[Summary of the invention]

The frequency detection circuit of the present invention includes a counter section that counts pulse edge intervals of a digital input signal having an inversion period limit value uniquely set according to a predetermined modulation method based on a predetermined clock signal, and a counter section that stores data. and a comparator section that compares the outputs from the counter section and the register section. If the outputs of the counter section and the register section satisfy a predetermined relative magnitude relationship within a predetermined period, the data stored in the register section is changed to a predetermined constant count value in response to the comparison result of the comparator section. Process increases and decreases,
The updated count data is continuously held in the register section as data corresponding to the inversion cycle limit value. Thereby, the above objective can be achieved.

[Embodiments of the invention]

First, an overview of an optical (CD type) digital audio disk (DAD) playback device to which an embodiment of the present invention is applied will be explained.

As shown in FIG. 2, an information recording medium, for example, an optical disk 54, is mounted on a turntable 52 that is rotationally driven by a disk motor 50.
It is reproduced by an optical pickup 56. In this case, the optical pickup 56 directs the emitted light from the semiconductor laser 56a to the beam splitter 56.
b, and the optical disk 5 via the objective lens 56c.
The signal recording surface of 4 is irradiated with a pit ( The reflected light from the uneven surfaces with different reflectances is transmitted to the objective lens 56c and the beam splitter 56b.
It leads to a four-part photodetector 56d. The four-division photodetector 56d is configured to be able to output the four playback signals photoelectrically converted to the outside.
It is linearly driven in the radial direction of 4.

The four reproduced signals from the four-division photodetector 56d are supplied to the matrix circuit 60 and subjected to a predetermined matrix calculation process, thereby converting them into a focus error signal F, a tracking error signal E, and a high frequency signal RF. separated.

The focus error signal F is sent to the focus servo system of the optical pickup 56 along with the focus search signal from the focus search circuit 62.
Used to drive FS. Further, the tracking error signal E is transmitted to a system controller 6 which will be described later.
The tracking servo system of the optical pickup 56 along with the search control signal provided via 4
It is used for driving the TS and controlling the linear tracking of the pick-up feed motor 58.

The high frequency signal RF is supplied to the reproduction signal processing system 66 as a main reproduction signal component. The reproduced signal processing system 66 first guides the reproduced signal to a waveform shaping circuit 70 controlled by a slice level (eye pattern) detector 68 to separate unnecessary analog components and necessary data components. only
The signal is supplied to a PLL type synchronous clock regeneration circuit 72 and an edge detector 74a of a signal processing system 74.

In this situation, the synchronous clock regeneration circuit 72
The synchronizing clock from the synchronous signal is guided to the synchronizing signal separating clock generation circuit 74b in the signal processing system 74 for data demodulation, and is used to generate a synchronizing signal separating clock signal.

On the other hand, the reproduced signal that has passed through the edge detector 74a is supplied to a synchronization signal detector 74c, where the synchronization signal is separated by the synchronization signal separation clock signal and EFM demodulated by a demodulation circuit 74d. In addition, the synchronization signal is transmitted to the synchronization signal protection circuit 7.
4e, it is guided to the input data processing timing signal generation circuit 74f together with the synchronization signal separation clock signal in a protected state to prevent malfunction.

Further, the demodulated signal is supplied to an input/output control circuit 76a of another signal processing system 76, which will be described later, via a data bus input/output control circuit 74g, and the control signal and display signal components, which are subcodes, are , control display processing circuit 74h
and is supplied to the subcode processing circuit 74i. The subcode data subjected to necessary error detection and correction in the subcode processing circuit 74i is transmitted to the system controller 64 via the system controller interface circuit 74q.

The system controller 64 includes a microprocessor, an interface circuit, a driver integrated circuit, etc., and controls the DAD playback device to a desired state based on command signals from the control switch 78, and also controls the subcode described above. It is used for displaying information (for example, index information of played songs, etc.) on the display 80.

The timing signal from the input data processing timing signal generation circuit 74f is provided for controlling the data bus input/output control circuit 74g via the data selection circuit 74j. At the same time, the timing signal is transmitted via the frequency detector 74k, the phase detector 74l, and the PWM modulator 74m to automatic frequency control (AFC) and automatic phase control for driving the disc motor 50 in a constant linear velocity (CLV) manner. Provided for control (APC).

In this case, the phase detector 74l is supplied with a system clock signal from a system clock generation circuit 74p that operates based on an oscillation signal from a crystal oscillator 74n.

The demodulated data passing through the input/output control circuit 76a of the other signal processing circuit 76 is sent to the syndrome detector 76 for error detection and correction or correction.
b, error pointer control circuit 76c, correction circuit 7
The data is subjected to necessary error correction, deinterleaving, error correction, and other processing via the data output circuit 76d and the data output circuit 76e, and then supplied to the digital/analog (D/A) converter 82.

In this case, the external memory control circuit 76f cooperates with the data selection circuit 74j to control the external memory 84 in which data necessary for correction is stored, thereby performing the correction via the input/output control circuit 76a. It is designed to capture the necessary data. In addition, the timing control circuit 76g
functions to supply timing control signals necessary for error correction and correction based on the system clock signal from the system clock generation circuit 74p.

The mutating (detection) control circuit 76h operates during error correction and on the basis of the output from the error pointer control circuit 76c or the control signal given via the system controller 64.
Performs predetermined muting control required at the start and end of operation of the DAD playback device.

The audio reproduction signal thus converted into an analog signal by the D/A converter 82 is supplied to the speaker 90 via the low-pass filter 86 and amplifier 88.

Hereinafter, one embodiment of the present invention will be described which is provided as a means for controlling the PLL circuit 72 shown in FIG. A frequency detection circuit according to an example will be described.

FIG. 3 shows a frequency detection circuit according to a first embodiment of the present invention in correspondence with the conventional circuit shown in FIG. The digital input signal 100 reproduced from the optical disk 54 (FIG. 2) by the optical pickup 56 has a known maximum inversion period Tmax and minimum inversion period Tmin determined in advance, for example, according to EFM modulation. The input signal 100 is provided to an edge detection circuit 102. This edge detection circuit 10
2 detects the pulse edge and generates a counter control signal 106 for the counter 104. The counter 104 receives the demodulated clock signal 10.
Therefore, the counter 104 receives the input signal 1 based on the demodulated clock signal 108.
It has the function of counting the interval between 00 detected pulse edges. The count value 110 is applied to a first input of a comparator 112.

The second input terminal of the comparator 112 receives, for example, the register value 11 of the n-bit counter type register 114 that stores the maximum inversion period value.
6 is supplied. The counter type register (up counter type) 114 has a maximum inversion period at the start of detection.
A value smaller than Tmax (for example, 0) is preset. The comparator 112 compares the counter value 110 and the register value 116, and only when the counter value 110 is larger than the register value 116, transmits the output pulse 118 to the counter type register 114, thereby causing the counter and other registers 114 to Increment the register value by "1", that is, count up. After repeating the above operation for a predetermined period in this manner, the counter type register 114 outputs the register value 120 as the final integrated maximum inversion period value.

According to the first embodiment of the present invention configured in this way, the counter type register 14 is configured to count up "1" to the register value in response to the output pulse 118 of the comparator 112. , this allows you to easily obtain the integral output. Therefore, the total number of components of the circuit can be reduced, making it extremely suitable for integration. Furthermore, counter type register 1
The stored value of 14 is configured to be sequentially incremented by the unit counter value 1 each time the comparator 112 compares the value, so even if a burst error occurs in the input signal, It is possible to reliably prevent the inversion period from being erroneously detected as extremely large, thereby minimizing the adverse effects of burst errors and suppressing the occurrence of false detections.

FIG. 4 shows a second embodiment of the invention. Fourth
In the figures, the same reference numerals are given to the same components as in the first embodiment described above, and the explanation thereof will be omitted. The input signal 100 is an AND circuit 124
is supplied to the first input terminal of the demodulated clock signal 1
08 is supplied to the second input terminal of the AND circuit 124. That is, in the second embodiment, as an alternative to the edge detection circuit, by performing AND processing on the input signal 100 and the demodulated clock signal 108, the "H" level section or "L" level section of the input signal 100 is detected. It is configured to detect the maximum inversion period Tmax in any one of the following. Therefore, for example, the "H" level section is Tmax
When set as the detection period, the other "L" level section can be used as a margin period for the comparator 112 and the counter type register 114.
This is particularly suitable when the comparator 112 and the counter type register 114 have no processing margin.

FIG. 5 shows a frequency detection circuit according to a third embodiment of the present invention. In this embodiment, the n-bit counter type register 114 (second
The number of bits of the counter type register and comparator is reduced by weighting m bits (where m<n) to the bits (Fig. 3 and Fig. 3). That is, by weighting m bits, the number of bits of the counter type register 130 becomes n-m bits. Along with this, comparator 1
32 is also set to nm bits. This is because the output data 1 from the counter type register 130 is
34 with the counter value 110 from the counter 104, it is sufficient to compare only the nm bit capacity. In this case, only the lower nm bits of the output of the counter 104 are input to the nm bit comparator 132. Further, the counter 104 and the nm bit comparator 132 are connected to another AND circuit 136.
By ANDing the output 138 having nm bits of the nm bit comparator 132 and the output of the upper m bits of the output of the counter 104, , the above weighting is added, and then the corresponding
The above n-m bit counter type register 1 is clocked using the output 140 of the AND circuit 136 as a clock signal.
30.

According to such a structure, the number of bits of the counter type register 130 and the comparator 132 can be reduced by weighting, which is more advantageous in simplifying the structure.

It should be noted that the present invention is not limited to the embodiments described above, and it goes without saying that various modifications may be made within the scope of the present invention by those skilled in the technical field to which the present invention pertains. For example, in the above embodiment, the frequency is detected using the maximum value (Tmax) of the inversion periods set according to the EFM, but the invention is not limited to this. The same effect can be obtained by using That is, in this case, the magnitude relationship between the data to be processed related to the comparison process by the comparator may be set to be reversed, and a down counter type register may be used as the counter type register. However, in this case, it is necessary to set the frequency of the demodulated clock signal 108 high in order to obtain a resolution substantially equivalent to that of the above embodiment using the maximum inversion period (Tmax).

As described above, according to the present invention, it is possible to provide a frequency detection circuit that can simplify the circuit configuration and minimize the occurrence of false detections due to burst errors and the like.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional frequency detection circuit.
Figure 2 shows a digital circuit to which a frequency detection circuit is applied.
Block diagrams showing the basic overall configuration of an audio disk (DAD) playback device, Figures 3 to 5
The figures are block diagrams of frequency detection circuits according to first to third embodiments of the present invention. 102... Edge detection circuit, 104... Counter, 112, 132... Comparator, 114,
130...Counter type register.

Claims (1)

[Claims] 1. Counter means for counting pulse edge intervals of a digital input signal having an inversion period limit value uniquely set according to a predetermined modulation method based on a predetermined clock signal, register means for storing data, and said counter means. and comparator means for comparing the outputs from the register means, and when the outputs of the counter means and the register means satisfy a predetermined relative magnitude relationship within a predetermined period, the comparison result of the comparator means is In response to this, the data stored in the register means is increased or decreased by a predetermined constant count value, and the updated count data is held in the register means as data corresponding to the inversion cycle limit value. frequency detection circuit.