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JPH0459636U - - Google Patents

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Publication number
JPH0459636U
JPH0459636U JP1990102344U JP10234490U JPH0459636U JP H0459636 U JPH0459636 U JP H0459636U JP 1990102344 U JP1990102344 U JP 1990102344U JP 10234490 U JP10234490 U JP 10234490U JP H0459636 U JPH0459636 U JP H0459636U
Authority
JP
Japan
Prior art keywords
output terminal
signal output
capacitor
variable impedance
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990102344U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990102344U priority Critical patent/JPH0459636U/ja
Publication of JPH0459636U publication Critical patent/JPH0459636U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第3図は本考案の積分回路の1実
施例を示し、第1図は結線図、第2図は充電時の
第1図の等価回路図、第3図a,bは第1図の動
作説明用のタイミングチヤート、第4図は本考案
の応用回路例のブロツク図、第5図、第6図のa
,b及び第7図のa,b,cは第4図の動作説明
用のタイミングチヤート、第8図、第9図はそれ
ぞれ従来例の結線図である。 1……信号入力端子、2……信号出力端子、7
……可変インピーダンス体、8……コンデンサ。
1 to 3 show one embodiment of the integrator circuit of the present invention, FIG. 1 is a wiring diagram, FIG. 2 is an equivalent circuit diagram of FIG. 1 during charging, and FIGS. Figure 1 is a timing chart for explaining the operation, Figure 4 is a block diagram of an example of an application circuit of the present invention, Figures 5 and 6 are a.
, b and a, b, and c of FIG. 7 are timing charts for explaining the operation of FIG. 4, and FIGS. 8 and 9 are connection diagrams of conventional examples, respectively. 1...Signal input terminal, 2...Signal output terminal, 7
...Variable impedance body, 8...Capacitor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 信号入力端子と信号出力端子との間に前記両端
子間の電圧差に基づく半導体のバイアス変化によ
り抵抗値がアナログ変化する可変インピーダンス
体を設け、前記信号出力端子とアースとの間にコ
ンデンサを設けた積分回路。
A variable impedance body is provided between the signal input terminal and the signal output terminal, the resistance value of which changes analogously due to a bias change in the semiconductor based on the voltage difference between the two terminals, and a capacitor is provided between the signal output terminal and the ground. integrated circuit.
JP1990102344U 1990-09-29 1990-09-29 Pending JPH0459636U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990102344U JPH0459636U (en) 1990-09-29 1990-09-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990102344U JPH0459636U (en) 1990-09-29 1990-09-29

Publications (1)

Publication Number Publication Date
JPH0459636U true JPH0459636U (en) 1992-05-21

Family

ID=31846519

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990102344U Pending JPH0459636U (en) 1990-09-29 1990-09-29

Country Status (1)

Country Link
JP (1) JPH0459636U (en)

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