JPH0458347A - Control system for shared address space - Google Patents

Abstract

PURPOSE:To reduce the overhead that is caused when an address conversion buffer is operated within a processor following the operation a shared address space of a multiprocessor system by providing a shared bit in a page table entry and an entry of the address conversion buffer. CONSTITUTION:A shared bit is set to an entry 421 of a page table 42 to show whether the page designated by the entry of the page table is shared with another processor or not. Then the contents of the shared bit are set to a data part 112 forming an entry of an address conversion buffer means 11 when the entry of the means 11 is updated. Furthermore a valid bit of the means 11 showing the validity of the entry of the means 11 is set to an associative part 111 forming the entry of the means 11. As a result, the overhead can be reduced when a TLB 21 of another processor 2 is operated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a shared address space management method, and particularly to a shared address space management method in a multiprocessor system.

[Conventional technology]

In information processing systems using multiprocessors,
There are many cases where a virtual memory method using paging is adopted.

As is well known, in this method, the main memory is divided into blocks of a size called pages, which serve as units of loading and reallocation. The program that runs this is also divided into pages of the same size and loaded one by one.

When a certain program is instructed to be executed, a page table related to that program is first created in the main storage device or the like. A page table is a correspondence table between program pages and hardware pages, and is used by the hardware to convert virtual addresses to real addresses.

An example of hardware for this purpose is an address translation mechanism including an address translation buffer (hereinafter referred to as TLB).

If there is no free space in the main storage device or the like to store the requested page, unnecessary pages or pages that are used less frequently are removed and a new page is set. At this time, the page table is also updated.

When updating page table entries (page descriptors),
If the page table entry to be updated is shared by multiple processors forming a multiprocessor, the interprocessor communication means interrupts the other processors.

A conventional shared address space management method of this type invalidates all entries in the address translation buffer.

[Problem to be solved by the invention]

The above-described conventional shared address space management method invalidates all entries in the TLB, which has the disadvantage that the overhead when using the shared address space, that is, the proportion of the execution time of the management program becomes large.

That is, the fact that a shared address space is being used can be determined from the task management information of each processor. However, since the virtual address corresponding to the actual shared page is different for each task, the affected virtual address is stored in the TLB for each processor as the page table changes.
Searching from within takes a lot of effort.

Therefore, the commonly used method is to invalidate all TLBs, which is easy from a software perspective but incurs a large overhead.

As a result, the invalidation of all TLBs has the disadvantage that the address translation speed of each processor is temporarily reduced, resulting in a reduction in the performance of the entire information processing apparatus.

[Means to solve the problem]

The shared address space management method of the present invention uses a virtual storage method using paging, and has an address translation device equipped with an address translation buffer means for converting an address from a virtual address to a real address using a page table on a main storage device. In a multiprocessor system composed of a plurality of processors, a shared bit indicating whether the page specified by the page table entry is shared with other processors configuring the multiprocessor is added to the page table entry. and setting the content of the shared bit in a data section constituting an entry of the address translation buffer means when updating the entry of the address translation buffer means, and setting the content of the shared bit to a data part constituting the entry of the address translation buffer means, and setting the content of the shared bit to the data part constituting the entry of the address translation buffer means, which indicates the validity of the entry of the address translation buffer means. A buffer means valid bit is set in an associative part constituting an entry of the address translation buffer means.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

Further, FIG. 2 is a diagram showing an example of a multiprocessor system to which the embodiment shown in FIG. 1 is applied.

In FIG. 2, a first processor 1 and a second processor 2 are connected to a main storage device via a system bus 3 to form a multiprocessor system.

The first processor 1 is an address translation buffer (hereinafter referred to as TLB).
) 11 and the second processor 2 each have a TLB 21 and use a virtual storage system using paging.

Further, the first processor 1 and the second processor 2 are connected by a communication bus 5.

In FIG. 1, the 32-bit long virtual address 12 is
From the upper bit side, 2-bit section ID/IDS, 10-bit area ID/IDA, 8-bit page ID-IDP, and 12-bit intra-page offset P.
It is composed of O.

Conversion from the virtual address 12 of each processor, for example, the first processor 1, to the real address 43 of the main storage device 4 is executed in the following procedure.

Here, 1 at the beginning of the code indicates a component that belongs to the first processor 1, and 4 indicates a component that belongs to the main storage device 4. Also, regarding the component of the second processor 2, the 1 at the beginning of the code is read as 2. shall be taken as a thing.

First, according to section ID-ID5, a corresponding register is selected from area table registers 13 in the processor.

Next, specify the area table 41 with the area table base address ATA in the area table register 13,
From this designated area table 41, area I
Area table entry (ATE) specified by D.IDA
) 411 is selected.

Next, a page table 42 is specified by the page table base address PTA in the ATE 411, and a page table entry (PTE) 421 is selected from the specified page table 42 by specifying the page ID/IDP.

Finally, the page 431 is specified using the real page number RPN in the PTE 421, and the converted real address 43 is obtained by adding the intra-page offset PO from the specified page 431.

Each processor has a TLBll, as shown in FIG.

As mentioned above, when a virtual address to real address translation is performed, the translation result is stored in TLB 11.

In other words, the upper 20 bits 208B of virtual address 12
is set in the association section 111 of the TLBII entry, and the real page number RPN of the conversion result and virtual storage management information such as protection information are set in the data section 112, and the TLBII entry becomes valid.

Next, when the same virtual address 12 is converted again, the upper 20 bits 203B of the virtual address 12 are converted to TL
It is compared with the association section 111 of each valid entry in the Bll. As a result of the comparison, if the two match, the real page number RPN is read from the data section 112, and the intra-page offset PO is read out from the data section 112.
is added to immediately obtain the real address.

FIG. 3 is a diagram showing the configuration of the page table entry 421.

The page table entry 421 is the real page number RPN
, a shared bit S, a modify bit M, a valid bit (■), and other virtual memory information.

Valid bit V indicates whether page table entry 421 is valid.

Modify bit M indicates whether writing has been performed on the page specified by this page table entry 421.

Furthermore, the modify bit M is used by the operating system of the multiprocessor system to perform virtual memory management.

The shared bit S indicates whether the page specified by this page table entry 421 is shared with other processors.

FIG. 4 is a diagram showing the configuration of TLBll.

An entry in TLBll consists of an association section 111 and a data section 112.

The associative unit 111 stores the upper 20 bits 2 of the virtual address 12.
03B and the valid bit V of the TLB 11 entry.

The data section 112 includes a real page number RPN, a TLB shared bit S, a modify bit M, and other virtual storage management information.

Next, the operation of this embodiment will be explained.

Here, an example of processing '' in which the first processor 1 writes to a page constituting a shared address space with the second processor 2 will be explained.

When the first processor 1 writes to a page for the first time, the modify bit M of the page table entry 421 is set.

However, the first processor 1
When the page table entry is read for setting, it is detected that the shared bit S is set.

Therefore, the first processor 1 communicates with other processors, that is, the second processor 2 via the inter-processor communication bus.
to notify updates of the shared address space.

When the second processor 2 is notified of the update of the shared address space via the communication bus, the valid bit 2 is cleared for the shared entry among the entries in the built-in TLB 21.

FIG. 5 shows the concept of a logic circuit for canceling the valid bit V.

In FIG. 5, the second processor 2 receives the modify bit M from the first processor 1 via the communication bus 5 for the page table entry 421 in the shared address space.
will be notified of updates. Then, the update of the shared address space modify bit M in the second processor 2 is caused by the signal A.
be notified by.

When the register 31 of the shared bit S that exists for each TLB is set, the AND gate 32 and the OR gate 33
The valid bit V is cleared through.

Signal B is used by the second processor 2 itself to operate the register 34 of the valid bit.

In FIG. 5, the register 31 for the shared bit S and the register 34 for the effective bit ■ are assumed to use standard RS flip-flops, but the actual means of implementation is not limited to this, and the gist of the present invention is Of course, it can be applied as long as there is no deviation.

As described above, by writing to the page of the shared address space, the entry of the TLB 21 of the other processor, that is, the second processor 2, is updated.

Next, a second embodiment of the present invention will be described.

The second embodiment relates to transmission of management information of a shared address space using the same hardware as the first embodiment.

When using a shared address space, from the first processor 1 to the second
Assume that it becomes necessary to transmit management information to processor 2.

In the second processor 2, processes that use the shared address space are not always running, so if the first processor 1 immediately interrupts the second processor 2, the running of processes unrelated to the shared address space will be interrupted. There is a risk of interference.

Therefore, using a communication bus router, T in the second processor 2 is
In the LB 21, the entry in which the shared bit S is set is invalidated, and at the same time, a trap bit T is set in the free area on the page table entry 421 as shown in FIG.

In the second processor 2, a process using the shared address space starts running and accesses the virtual address corresponding to the page table entry 421 with the trap bit T set. Then, as described above, since the entry in the TLB 21 has been invalidated, address translation without using the TLB as described in the first embodiment is performed.

Then, by detecting the trap bit T when reading the page table entry 421, the transmission of information regarding the shared address space from the first processor 1 is known.

Actual information transmission is executed by a separately set trap handler program.

In this embodiment, information transmission regarding the shared address space is
In fact, accessing the shared address space by the other processor can be delayed, which has the advantage of not interfering with processes running on the other processor.

〔Effect of the invention〕

As explained above, the present invention provides shared bits in page table entries and address translation buffer entries to operate address translation buffers in other processors that accompany the operation of a shared address space in a multiprocessor system. This has the effect of reducing the overhead in the case.

register, 31.34... register, 32...A
ND gate, 33...OR gate, 41...area table, 42...page table, 43...real address.

Claims (1)

[Scope of Claims] From a plurality of processors that use a virtual memory method using paging and have an address translation device equipped with an address translation buffer means that performs address translation from a virtual address to a real address using a page table on the main memory. In the multiprocessor system configured, a shared bit indicating whether or not the page specified by the page table entry is shared with other processors making up the multiprocessor is set in the page table entry, When updating the entry of the address translation buffer means, the content of the shared bit is set in a data section constituting the entry of the address translation buffer means, and an address translation buffer means valid bit indicating the validity of the entry of the address translation buffer means. is set in an associative part constituting an entry of the address translation buffer means.