JPH0457536A - Clock supply system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding the uninterrupted tarlock switching method in a digital transmission device having a duplicated clock supply source, a clock supply without instantaneous clock interruption when switching the clock supply source from the working to the standby clock supply source is provided. The purpose of the present invention is to provide a system that includes two clock generators, a working clock and a standby clock, which multiply an externally supplied basic clock and generate a master clock synchronized with the basic clock, and the two master clocks inputted thereto; When an abnormality occurs in the master clock from the working clock generator, there is a changeover switch that switches to the master clock from the backup clock generator and outputs it, and the master clock output from the changeover switch is input and outputs the same frequency that is phase-synchronized with the master clock. The apparatus includes a PLL circuit that generates a device clock and supplies it to the data processing section, and is configured to supply the device clock to the data processing section without interruption even during the switching processing time of the changeover switch.

[Industrial application field]

The present invention relates to an uninterrupted clock switching method in a digital transmission device having dual clock supply sources.

Recently, there has been a demand for duplication of communication devices in order to increase the reliability of communication systems. For this reason, even in digital transmission devices, each functional block within the device, such as a clock supply section and a multiplex conversion section, is duplicated, so that a system failure will not occur due to failure of each section.

When duplicating clock supply sources, it is required to prevent instantaneous clock interruptions due to switching.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional tarlock supply system in a duplex digital transmission device. Current use,
The spare duplicated clock generators 1-N and 1-E each receive the same reference clock from the outside,
A built-in PLL circuit creates a mask clock with a predetermined frequency synchronized with the reference clock, and the changeover switch 2-
The data is supplied to data processing units 4-N and 4-E such as digital multiplexers via N and 2-E.

Two master clocks, a working master clock and a standby clock, are input to the changeover switches 2-N and 2-H, and normally the working master clock is selected and output, but the working clock generator 1
-N, when the master clock is disconnected due to a failure, the clock monitoring section in the clock generating section 1-N detects this and outputs a switching control signal to switch the changeover switch, and the data processing section 4-N, 4 The clock supply source to -E is switched from the failed current generation unit l-N to the normal generation unit 1-H.

[Problem to be solved by the invention]

The clock monitoring section has a predetermined protection time set before it generates a switching signal in order to prevent clock pulse omissions that happen to occur due to noise or errors from being determined as a clock interruption. Only when it is not detected is it determined that there is a clock interruption that requires switching of the supply source.

For this reason, it takes time to detect a clock disconnection, and a finite amount of time is also required to operate the changeover switch, so it takes some time for the backup clock generator to resume supplying the normal master clock. Since a normal master clock is not supplied to the data processing section during the period required for this switching control, there is a problem in that errors occur in the output data of the data processing section.

The present invention was created in view of the above-mentioned problems, and an object of the present invention is to provide a clock supply system that does not cause instantaneous interruption of tarock when switching the clock supply source from the active clock to the standby clock supply source.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle configuration of the clock supply system of the present invention.

The above problem, as shown in FIG. 1, consists of two clock generating units 1-N and 1-N, a working clock generator and a standby clock generator, which multiply an externally supplied basic clock and generate a master clock synchronized with the basic clock. E and the two mask clocks are input, and the current clock generator 1-N
When an abnormality occurs in the master clock from the spare clock generator IE, a changeover switch 2 switches to and outputs the master clock from the backup clock generator IE, and the master clock output from the changeover switch 2 is input, and a clock of the same frequency that is phase-synchronized with the master clock is input. It is characterized by having a PLL circuit 3 which generates a device clock and supplies it to the data processing section 4, and supplies the device clock to the data processing section 4 without interruption even during the switching processing time of the changeover switch 2. This problem is solved by the clock supply method of the present invention.

[Effect]

If the free running time of the PLL circuit is set to be sufficiently longer than the switching processing time of the clock changeover switch, the PLL circuit will be able to run even if the regular master clock is not supplied during disconnection detection and switching operations.
Since a normal device clock is supplied to the data processing section by the action of the L circuit, data errors can be eliminated.

〔Example〕

The present invention will be explained in detail below with reference to the accompanying drawings.

FIG. 2 is a circuit diagram of one embodiment of the present invention. Note that the same reference numerals represent the same objects throughout the figures.

In Fig. 2, l-N and 1-E are active and backup tarlock generators, respectively, and are supplied with, for example, 1.5 MHz active and backup dual basic clocks ■ and -■. The generator generates, for example, 78 MHz mask clocks (1) and (2) in synchronization with either of the same basic clocks. The working clock generating section 1-N has a clock monitoring section 11, and the monitoring section 11 constantly monitors the master clock ■ outputted by the self-generating section, and the mask clock interruption continues for a predetermined period of time (for example, 50 m5) or more. Then, it is determined that the self-generating section has failed, and a switching control signal ■ is output. 2-N and 2-E are active and standby selector switches, respectively, and the master clocks ■ and ■ from two clock generators are input to each, and normally the active clock ■ is output, but this If a clock interruption occurs in
Based on the switching control signal ■, the clock is switched to the backup clock ■ and output. 3-N and 3-5 are the active and backup PLs, respectively.
It is an L circuit and outputs a device clock of the same frequency that is synchronized with the input master clock. This PLL circuit 3
-N and 3-E have two n frequency dividers, a voltage controlled oscillator, a low-pass filter, and a phase comparator, and even if the input of the master clock is interrupted due to the action of the low-pass filter, even if the input of the master clock is interrupted, even within the free running time. For example, it continues to generate a device clock (2) with the same frequency as the master clock.

4-N and 4-E are active and backup data processing units, such as digital multiplex conversion circuits, respectively;
In response to the device clock (2) supplied from the LL circuit, the input low-order group data is multiplexed and converted into high-order group data.

In a transmission device with such a duplex configuration, when a failure occurs in the currently used clock generator 1-N and the clock is cut off, the clock monitor 1-N is activated after a predetermined period of time.
1 outputs a switching control signal ■, and the working and standby changeover switch circuits 2-N and 2-E operate the working and standby PLLs, respectively.
Switch the master clock supplied to circuits 3-N and 3-E to the backup clock ■. During the time required for this switching, P
Although the master clock supply to the LL circuits 3-N and 3-E is interrupted, the PLL circuits 3-N and 3-E run by themselves.
The same device clock (2) as before the interruption of the current master clock is supplied to the data processing unit. As a result of this switching, the supply of the spare master clock ■ having the same phase as the previous master clock ■ from the spare clock generating section 1-E is restarted, so that the PLL circuits 3-N and 3-E are again supplied with the input master clock. is synchronized with and continues to generate the device clock ■. In other words, even while the master clock supply source is switched by the changeover switch, a normal device clock is supplied to the duplexed data processing section, so data errors will not occur in the multiplexed signal etc. created. Prevented.

〔Effect of the invention〕

As explained above, even if a momentary interruption occurs due to switching of the duplicated clock generation section, the momentary interruption will not occur in the device clock that is absorbed by the PLL circuit and supplied to the data processing section. This has the effect that it can be obtained.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of a clock supply system of the present invention, FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a block diagram showing a conventional clock supply system. In the figure, 1-N, 1-E clock generator, 2, 2-N,
2-E changeover switch, 3, 3-N, 3-E -P
LL circuit, 4, 4-N, 4-E data processing section, clock monitoring section. This flow..., F1 ordinary η to 〇 unilateral composition mouth Fig. 1 Conventional F day, 7 F combined supply η6 Pro shown in I7 Fig. 3
figure

Claims (1)

[Scope of Claims] Two clock generating units (1-N, 1-E), a working clock generator and a backup clock generator, which multiply a basic clock supplied from the outside and generate a master clock synchronized with the basic clock; a changeover switch (2) that receives two master clocks as input, and when an abnormality occurs in the master clock from the working clock generator (1-N), switches to and outputs the master clock from the standby clock generator (1-E); A PLL circuit (3) receives the master clock output from the changeover switch (2), generates a device clock of the same frequency phase-synchronized with the master clock, and supplies the same to the data processing section (4). . A clock supply system characterized in that a device clock is supplied to the data processing section (4) without momentary interruption even during the switching processing time of the changeover switch (2).