JPH0451348A - Dma controller - Google Patents

Abstract

PURPOSE:To accelerate processing speed by detecting abnormality in which command readout from a transfer control information table is not completed in a period to start the next block transfer by a DMAC comprehensively. CONSTITUTION:An abnormality detection circuit 30 to detect the abnormality is provided in the DMAC 1, and an abnormality reporting signal 31 to report the abnormality to an MPU 4 is provided. Therefore, since not only the abnormality can be detected by an I/O device 9, but it can be detected by the DMAC 1, processing can be immediately performed by the MPU 4. In such a way, it is possible to reduce hardware quantity in the whole system, and to easily perform system design. Also, no polling by an MPU program is required, and abnormality processing can be performed by the MPU program at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an abnormality detection mechanism of a DMA controller that performs multi-array chain transfer. The present invention relates to an abnormality detection mechanism suitable for simultaneous channel detection.

[Conventional technology]

For example, as described in Japanese Unexamined Patent Publication No. 65-259549, a conventional device has a two-sided register group for storing transfer control information for accessing memory, and a DMA controller that performs link array chain transfer. The priority order for bus acquisition rights was set in the order of DMA transfer, reading of transfer control information, and central processing unit, and link array chain transfer was performed by alternately using the register groups on the two sides.

[Problem to be solved by the invention]

The above conventional technology does not take into account an abnormality in which the operation of reading transfer control information from a table and writing it to a register group is not completed within a period until block transfer using that register group is started. For this reason, the channel device must have a built-in function for detecting an abnormality, resulting in problems such as slow processing speed and increased amount of hardware.

[Means for resolving issues]

In order to achieve the above object, the present invention solves the problem that an abnormality occurs in which the operation of reading transfer control information from a table and writing it to a register group is not completed within a period until a block transfer using the register group is started. and a means for reporting the occurrence of the abnormality to the MPU are provided inside the iDMA controller. Also, M.P.
In order to provide the iMPU with information on which channel the U program should perform abnormality processing on, a means for holding information on the DMA channel in which an abnormality has occurred is provided inside every DMA controller.

[Effect]

Since the command read has not been completed while the DMA controller is performing a link array chain transfer operation, the logical product of the signal indicating that there is a command read request and the counter overflow signal used to know the end of block transfer is the same. - Detects in the DMA channel that reading of a command from the transfer control information table is not completed before starting the next block transfer.

A p-flip 70 tab is set according to the detection signal, and the logical sum of the outputs of the 7 flip 70 tabs for each channel is used as an abnormality report signal. Report 1 for abnormality report signal tl-MPH
One of the causes of the interrupt request signal (2) is that by making it a dedicated interrupt request signal, it is possible to report all abnormalities to the MPU. By making it readable from the MPU as a flag, even if an error occurs in multiple channels at the same time, the MPU that receives the error report can immediately and correctly recognize the DMA channel to be processed in the error processing program. become.

[Example〕 Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a system configuration diagram showing an embodiment of the present invention. In the figure, 1 is a DMA controller (hereinafter referred to as DMAC), 2-1 to 2-n and 6-1 to 5-n are transfer control information, that is, DMA transfer start address (hereinafter referred to as AD), and the number of DMA transfer bytes (hereinafter referred to as AD). These are register groups A and B for taking in three types of data: a command code (hereinafter referred to as CD), and a command code (hereinafter referred to as CD). 5 is a physical address bus, 6 is a data bus, 7 is a control signal bus for reading and writing, 15 is a priority determination circuit that determines the channel to be used for buses 5, 6, and 7t, 9 is an I10 device, 18
22-1 to 22-n and 25-1-23-n are select signals for register groups A and H corresponding to channels 1 to n, and 50 is a DMA control circuit that controls DMA of I/O device R9. An abnormality detection circuit 62 indicates a control signal from the DMA control circuit 18 to the abnormality detection circuit 30. Further, 13 is a DMA transfer request signal (hereinafter referred to as DREQ) from the I10 device 9, and 14 is a DMA transfer request signal from the I10 device 9.
DMA transfer permission number I (hereinafter referred to as DACK),
4 is MPU.

61 is an abnormality report signal from the abnormality detection circuit 50, 16 is D
A signal requesting precise bus usage rights for MA operation (hereinafter referred to as B
17 is a bus use permission signal (hereinafter referred to as BUSACK) output by the MPU 4, 12 is a logical address bus, 8 is an address converter, 10 is a memory, 11 is a block within the memory 10, and 19 is also a memory. 10 shows a transfer control information table in 10. In addition, in this system, the bus usage right is prioritized from the highest priority to the DMA
It is assumed that the settings are set in the following order: transfer, reading of transfer control information (hereinafter referred to as command read), and access to the memory 10 of the MPU 4 (hereinafter referred to as MPU access).

As shown in FIG. 1, in this embodiment, all abnormality detection circuits 30 are provided in the DMAC 1 to detect all abnormalities, and the MPU 4
An abnormality report signal 61 is provided for reporting abnormalities. Therefore, the abnormality can be detected not only by the I10 device 9 but also by DMACl, so the MPU 4 can immediately detect the abnormality.
Processing becomes possible.

FIG. 4 shows the DMA control circuit 1 of the DMAC 1 according to this embodiment.
8 and details of the abnormality detection circuit 30. In the figure, 101 is a counter that counts the number of 170 DMA transfer bytes, 102 is an overflow signal that is output from the counter 101 when one block of DMA transfer is completed, and 105 holds all channel numbers of active DMA channels. 104 is a channel number output from the channel number holding circuit 105,
104-1 to 104-n are signals corresponding to channel 1 to channel n of channel number 104, and 105 is a command read condition signal 106f that determines the mode setting and whether or not it is the final block and performs a command read, and an output 107 is a register group switching F/F group, 108 is an inverter, 109 is an AND circuit, 110 is a command read request set signal, 111 is a command read request F/F group, 112 is a command read request signals, 112-1 to 112-n are signals corresponding to channels 1 to n of the command read request signal 112, 115 is a command read control circuit, 114 is a command read end signal, 115 is an AND circuit, 116-1 to
116n is an abnormality report set signal for each channel, 11
7 is a set/reset F/F, 118 is an OR circuit, 11
9 indicates an abnormal channel number signal.

Although only one channel number 104, command read condition signal 106, command read request set signal 110, command read request signal 112, and command read end signal 114 are shown in FIG. , there are the same number of channels as the number of channels.

FIG. 2 is a time chart when a DMA transfer involving the operation of a link array chain is normally performed. First, the first
The operation in this case will be explained using the diagram and the second figure sound.

Before starting DMA transfer, MPU4 uses the D
AD and CT in register groups A2 and B6 of the MA channel.
, CD, and also set the internal register of the I/O device 9 so that DMA transfer can be performed. When a DMA transfer request occurs, it notifies the t-DMAcl that the request is valid. DMACI sends a BUSR to the MPU 4 in order to request release of bus rights while determining the priority order between channels in the priority determination circuit 15.
Outputs EQ16. When MPU4 is ready to release the bus, BUSACKl 7 y&:DMAC
Output to I.

BUSACKl 7 t-The received DMACI is assigned to the corresponding channel 0DACK14 based on the priority determination result.
f: Enable and start DMA transfer. In this way, the DMA transfer of the first block is performed by register group A2't-
It is done using

When the first block transfer is completed, control is automatically transferred to register group B6, and the second block transfer is started. While the second block transfer is being executed, the DMA and CI read the command for the third block transfer. As described above, the command read path acquisition right is set to have a lower priority than that of DMA transfer, so command read is performed during a period when no DMA transfer is being performed.

AD and CT of the third block read from the transfer control information table 19 configured in the memory 10.

By writing to the CD'(il-register group A2), the command read for the third block is completed.

Thereafter, when the second block transfer is completed, DMA transfer of the third block is performed using AD, C'[', and CD set in the register group A2.

At the same time, a command read is performed for the fourth block, and the command code is read from register group B3.
is set to Similarly, the link array chain operation is repeated. DM when all block transfers are completed
ACI outputs a transfer end signal and ends the transfer.

FIG. 3 is a time chart when an abnormality occurs in DMA transfer involving link array chain operation.

The operation in this case will be explained using FIGS. 1 and 6.

Now, consider a case where the 1-1th block transfer is performed on channel 1 and the j-1th block transfer is performed on channel n. At this time, channel 1 is simultaneously reading a command for the first block transfer, and channel n is simultaneously reading a command for the j-th block transfer. After the currently executed block transfer and command read are completed, each channel starts the 1st and jth block transfer. At this time, if DMA transfers of other channels are performed at the same time and bus 5.6.7 is exclusively used for DMA transfer, channel 1 will read the command for the 1+1st block, and channel n will read the command for the j+1th block. can't do it. This is because, as described above, DMA transfer is executed with priority over command read. Therefore, channel 1 is 1+
1st block, channel n id j + 1st block cannot be transferred. At this time, I
When a transfer request occurs to the 10 device 9, a data overrun error occurs. Although it is shown in FIG. 3 that the abnormality occurs in two channels, it is possible that the abnormality occurs in three or more channels.

In this embodiment, in order to detect, report, and process such abnormalities, an abnormality detection circuit as shown in FIG. 4 is provided. Fifth
The operation of the circuit will be explained using the time chart +t- in the figure.

An AND circuit 109 performs the logical product of the overflow IP address 102, the channel signal 104, and the command read condition signal 106.
The command read request set signal 110 is generated by setting the command read request set signal 110, and the command read request signal 112 is enabled by setting the F/Fi corresponding to the channel of the command read request F/F group 111. The command read request is made in response to the command read request signal 112 from AD, CT,
When the CD settings are completed, a command read end signal 114 is sent.
reset by .

When an abnormality occurs, it can be detected by the occurrence of a counter overflow while a command read request is being issued, such as when the first block transfer is completely completed in FIG. 5. This means that the command read was not completed before the next block transfer started. The AND circuit 1 performs the AND of the command read request signal 112, channel signal 1o4, and overflow signal 102 for each channel.
15 and is used as an abnormality report set signal 116 for each channel. The set reset F/F 117 is set by this abnormality report set signal 116. OR circuit 1
At step 18, the logical interest of the output signals of all channels of the set/reset F/F 117 is calculated and used as an abnormality report signal 31 to the MPU 4.

Further, the abnormality report signal 31 is transmitted to the MPU 4 as a type of interrupt request signal, and the MPU 4 starts executing the abnormality processing program. Addresses are assigned to the F/F 117 and the OR circuit 118 as internal registers of DMACl, so that they can be accessed from the MPU 4.

In the MPU4 abnormality processing program, set reset F
The abnormal channel number signal 119 is completely read out from /F117, the channel number where the abnormality has occurred is known, and necessary processing is performed. After that, set reset F/ of the processed channel
Access F117i and reset. This process is performed for all channels in which a total abnormality has occurred.

After the abnormal processing is completed, control is performed to perform link array chain transfer starting from DMA transfer of the block that could not be processed, that is, the 1+1th block in FIG.

Although FIG. 5 shows only the DMA transfer for the negative channel, there are actually negative channels.

In addition, in this embodiment, the command read control circuit 115iD
Although the explanation has been made assuming that the MPU exists in the MAC 1, the command read control circuit 1 is installed in order for the MPU, DMAC and
15 is provided within the MPUJ.

In this embodiment, the abnormality report is performed using an interrupt signal and the processing is performed using the abnormality processing program.
, when integrated into one chip, it may be realized by software interruption to the request processing microprogram of the MPU.

According to this embodiment, the iDMAC collectively detects an error in which command reading from the transfer control information table is not completed within a period before starting the next block transfer, and the MPU
It is possible to provide the iMPU with the information necessary for abnormality processing using all interrupts. Since it is not necessary to provide a means for detecting an abnormality in all the I10 devices, the hardware of the entire system can be reduced and system design becomes easier. Further, there is no need to perform polling by the MPU program, and high-speed processing can be performed by the abnormality processing t-MPU program, which has the effect of improving the processing speed of the entire system.

〔Effect of the invention〕

According to the present invention, the abnormality 'fr' in which command reading from the transfer control information table is not completed until the start of the next block transfer is detected by the DMAC all at once, and the MP
Information t-MPU required for abnormality processing by interrupting U
can be provided to Since it is not necessary to provide a means for detecting an abnormality in all of the 10 devices, the amount of hardware for the entire system can be reduced and system design becomes easier. Further, since there is no need to perform polling using the MPU program, and abnormal processing can be processed at high speed using the MPU program, the processing speed of the entire system is improved.

[Brief explanation of the drawing]

The first figure is a block diagram of an information processing system according to an embodiment of the present invention, and the second figure is a time chart when DMA transfer using a conventional link array chain is normally performed.
FIG. 3 is a time chart when an abnormality occurs in a DMA transfer involving a link array chain according to the prior art, FIG. 4 is a system diagram of the DMAC of the present invention, and FIG. 5 is a DMA transfer involving a link array chain of the present invention. This is a time chart when all transfers are performed normally. 1...DMAC, 4...MPt), 9...I10
device, 10... memory, 11... data block,
50...Abnormality detection circuit, 61...Position information failure issue,
112... Command read request signal, 116... Abnormality report set signal, 119... Abnormal channel number signal

Claims (1)

[Claims] 1. A two-sided register that holds transfer control information is connected to each DMA.
Provided for each channel, alternately switching the register, and executing DMA transfer of the DMA channel based on DMA transfer control information held in the one register,
In a DMA controller comprising means for storing the DMA transfer control information of the next data block in the other register and performing link array chain transfer for each channel, the transfer of the next data block is started at the time of the link array chain transfer. means for detecting whether storing of the DMA transfer control information of the next data block to be stored in the register is completed by the time of each of the DMAs.
A DMA controller characterized by being provided for each channel. 2. In claim 1, if incomplete storage of the DMA transfer control information in the register is detected in any of the DMA channels,
A means for outputting to that effect, and the DM whose storage has not been completed.
A DMA controller that holds the transfer control information of the A channel and is provided with externally accessible channel information holding means for each of the DMA channels. 3. In claim 2, a memory, an input/output device, the DMA controller that controls DMA transfer between the memory and the input/output device, and instructs the DMA controller to perform the DMA transfer of the link array chain. The central processing unit and the DMA controller notify the central processing unit of the detection of incomplete storage of the DMA transfer information in the register, and the central processing unit receives notification from the DMA controller of the detection of incomplete storage of the DMA transfer information. An information processing system that, when receiving a notification, accesses the channel information holding means of the DMA controller and performs processing according to the obtained DMA channel identification information. 4. The one-chip CPU according to claim 1 or 2, comprising a built-in central processing unit that instructs the DMA controller to perform the link array chain DMA transfer.