JPH0443434B2 - - Google Patents
Info
- Publication number
- JPH0443434B2 JPH0443434B2 JP19169984A JP19169984A JPH0443434B2 JP H0443434 B2 JPH0443434 B2 JP H0443434B2 JP 19169984 A JP19169984 A JP 19169984A JP 19169984 A JP19169984 A JP 19169984A JP H0443434 B2 JPH0443434 B2 JP H0443434B2
- Authority
- JP
- Japan
- Prior art keywords
- light emitting
- emitting diode
- light
- diode array
- wiring circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000605 extraction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 238000003491 array Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
- Exposure Or Original Feeding In Electrophotography (AREA)
- Led Device Packages (AREA)
- Led Devices (AREA)
- Dot-Matrix Printers And Others (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、発光ダイオードアレイヘツド、に係
り、例えば電子写真記録式光プリンタの発光ダイ
オードアレイヘツドで、特に、これをブロツクに
分割して駆動するのに好適な発光ダイオードアレ
イヘツドに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a light emitting diode array head, for example, a light emitting diode array head of an electrophotographic optical printer, and in particular, to a light emitting diode array head that is divided into blocks and driven. The present invention relates to a light emitting diode array head suitable for use in light emitting diode arrays.
電子写真記録の光源として、最近、装置の小型
化や機械的偏向走査をなくす目的から、発光ダイ
オードアレイが用いられるようになつた。
Recently, light emitting diode arrays have come to be used as light sources for electrophotographic recording for the purpose of downsizing devices and eliminating mechanical deflection scanning.
この発光ダイオードアレイは、高画質が要求さ
れる場合には10〜60ドツト／mmの高密度になり、
これをラインヘツドとする場合、A4判当り２，
100〜３，360ドツトになる。これを駆動するドラ
イバの数も同数必要であるので、通常、ドライバ
は集積回路化するが、これをGaAs等から成る発
光ダイオードアレイのチツプ上に構成すること
は、材料的に現在不可能である。 This light emitting diode array has a high density of 10 to 60 dots/mm when high image quality is required.
If this is used as a line head, 2 per A4 size,
It will be 100 to 3,360 dots. Since the same number of drivers are required to drive this, the drivers are usually integrated circuits, but it is currently impossible due to material considerations to configure this on a light emitting diode array chip made of GaAs or the like. .
それ故、発光ダイオードアレイチツプとドライ
バチツプを、絶縁性基板上に施した配線回路を仲
介して、互いに接続し、発光ダイオードアレイヘ
ツドを構成している。 Therefore, the light emitting diode array chip and the driver chip are connected to each other via a wiring circuit provided on an insulating substrate to form a light emitting diode array head.
この場合、発光ダイオードアレイないしドライ
バと配線回路の接続が高密度になるのを抑えるた
め、発光ダイオードアレイの発光ドツトに付けら
れた発光ドツト電極（発光ダイオードの一方の電
極）の端子を、発光ダイオードアレイチツプ配列
の両側に交互に取出して配線回路に接続するよう
にしている。 In this case, in order to prevent high-density connections between the light emitting diode array or driver and the wiring circuit, connect the terminals of the light emitting dot electrodes (one electrode of the light emitting diodes) attached to the light emitting dots of the light emitting diode array to The chips are taken out alternately from both sides of the array chip arrangement and connected to the wiring circuit.
このようにして、接続の密度を半分に軽減し、
実装作業を容易にしており、これにより、歩留り
率が高く、低価格化に寄与している。 In this way, we reduce the density of connections by half,
This simplifies mounting work, which contributes to high yield rates and low prices.
しかし、さらに低価格にするには、ヘツドの時
分割駆動を行つてドライバの数を減らすことが効
果的である。 However, to further reduce the cost, it is effective to time-divisionally drive the heads to reduce the number of drivers.
時分割駆動のためには、発光ドツト電極側にお
いて、グループ化するためのマトリツクス配線の
スペースが余分に必要となり、通常、ヘツド基板
が大きくなる。 For time-division driving, extra space is required for the matrix wiring for grouping on the light-emitting dot electrode side, which usually increases the size of the head substrate.
さらに、アレイチツプ配列の両側は、ドツト電
極と配線回路に接続部が占有するので、分割駆動
用の配線布設が難しい。 Furthermore, since both sides of the array chip arrangement are occupied by connecting portions between dot electrodes and wiring circuits, it is difficult to lay wiring for divided driving.
これらの難点を克服するような時分割駆動用の
配線回路の工夫がなされていなかつた。 A wiring circuit for time-division driving has not been devised to overcome these difficulties.
発光ダイオードアレイヘツドの接続回路で関す
るものに、例えば、特開昭56−45039号公報、特
開昭57−74166号公報等が挙げられる。 Examples of connection circuits for light emitting diode array heads include JP-A-56-45039 and JP-A-57-74166.
本発明は、上記に鑑み、ドライバ数を低減し
て、低価格になる、時分割駆動可能な発光ダイオ
ードアレイヘツドの提供を、その目的とするもの
である。
In view of the above, an object of the present invention is to provide a light emitting diode array head that can be driven in a time-division manner and is inexpensive by reducing the number of drivers.
本発明に係る発光ダイオードアレイヘツドの構
成は、多数の発光ダイオードアレイチツプを一列
に配置し、そのそれぞれの発光ダイオードアレイ
チツプの発光ドツト電極の配線回路と、同発光ダ
イオードアレイチツプの共通電極の配線回路とを
有する発光ダイオードアレイヘツドにおいて、各
別の発光ダイオードアレイチツプにおける発光ド
ツト電極の発光ダイオード素子を複数のグループ
に分け、その発光ドツト電極に対し相対的位置を
同じくする発光ダイオード素子に対して並列配線
を施した発光ドツト電極の配線回路と、櫛形の形
状で、発光ダイオードアレイチツプの配列側端に
引出しリードを有し、上記のグループ数、あるい
はその複数の、共通電極の配線回路とを有するよ
うにしたものである。
The structure of the light emitting diode array head according to the present invention is that a large number of light emitting diode array chips are arranged in a line, and a wiring circuit of the light emitting dot electrode of each of the light emitting diode array chips and a wiring of the common electrode of the same light emitting diode array chip are arranged. In a light emitting diode array head having a circuit, the light emitting diode elements of the light emitting dot electrodes in each different light emitting diode array chip are divided into a plurality of groups, and the light emitting diode elements having the same relative position with respect to the light emitting dot electrodes are divided into a plurality of groups. A wiring circuit of light-emitting dot electrodes wired in parallel, and a wiring circuit of a common electrode having a comb-shape and having lead-out leads at the array side end of the light-emitting diode array chip and having the number of groups described above or a plurality thereof. It is designed to have
さらに補足すると、次のとおりである。 Further details are as follows.
分割駆動を行うためには、発光ダイオードの電
極の他方の分割数に分けて、共通接続して引出す
ことが必要であるが、この配線を発光ダイオード
の一方の電極（前記発光ドツト電極）の接続部分
を乱すことなく布設することが肝要で、このため
の工夫が必要である。これに対し、本発明は、特
殊な形状のパターン布設でもつて分割駆動用の配
線回路を形成するようにしたものである。 In order to perform split driving, it is necessary to divide the electrodes of the light emitting diode into the other divided number and connect them in common. It is important to install the cable without disturbing any parts, and it is necessary to devise ways to do this. In contrast, in the present invention, a wiring circuit for divided driving is formed even by laying a pattern of a special shape.
本発明に係る発光ダイオードアレイヘツドの各
実施例を、各図を参照して説明する。
Embodiments of the light emitting diode array head according to the present invention will be described with reference to the drawings.
まず、第１図は、本発明の一実施例に係る発光
ダイオードアレイヘツドの略示配線回路図、第２
図は、それに使用される発光ダイオードアレイチ
ツプの表面拡大斜視図、第３図は、その発光ダイ
オードアレイの結線を示す断面図、第４図は、そ
の効果説明図、第５図は、その発光ダイオードア
レイチツプの配列状態を示す断面図、第６図は、
その動作説明回路図である。 First, FIG. 1 is a schematic wiring circuit diagram of a light emitting diode array head according to an embodiment of the present invention, and FIG.
The figure is an enlarged perspective view of the surface of the light emitting diode array chip used in it, FIG. 3 is a sectional view showing the connection of the light emitting diode array, FIG. FIG. 6 is a cross-sectional view showing the arrangement of diode array chips.
It is a circuit diagram explaining its operation.
第１図は、発光ダイオード（以下、LEDとい
う。）アレイヘツド駆動するために施された配線
回路を示すものであり、１は、アルミナからなる
絶縁性基板、２は、LEDアレイチツプC1，C2、
…、の発光ドツト電極L1，L2、…（第２図）と
ドライバIC５１，５２とを接続し、かつ、時分
割駆動のためになされているマトリツクス配線に
係る、発光ドツト電極の配線回路、３は、LED
アレイチツプC1，C2、…、の共通電極K1（第２
図、これは裏面に形成されている。）と分割駆動
用のドライバ６１，６２とを接続するコモン配線
回路、すなわち、共通電極の配線回路である。 FIG. 1 shows a wiring circuit installed to drive a light emitting diode (hereinafter referred to as LED) array head. 1 is an insulating substrate made of alumina, 2 is an LED array chip C 1 , C 2 ,
A wiring circuit for the light emitting dot electrodes, which connects the light emitting dot electrodes L 1 , L 2 , ... (Fig. 2) and the driver ICs 51, 52, and relates to matrix wiring for time-division driving. , 3 is LED
Common electrode K 1 ( second
Figure: This is formed on the back side. ) and the drivers 61 and 62 for split drive, that is, a common electrode wiring circuit.
なお、第１図で、３１，３２，３３、…は共通
電極の配線回路３の歯部、３ａは引出しリード２
ａは発光ドツト電極の配線回路２における並列配
線であり、これらについては後述する。 In FIG. 1, 31, 32, 33, ... are the teeth of the wiring circuit 3 of the common electrode, and 3a is the lead 2.
Reference symbol a indicates parallel wiring in the wiring circuit 2 of the light-emitting dot electrodes, and these will be described later.
第２図は、本実施例で使用するLEDアレイチ
ツプC1、（C2、…）の表面拡大図である。 FIG. 2 is an enlarged view of the surface of the LED array chips C 1 , (C 2 , . . . ) used in this example.
GaAs等のLEDアレイチツプC1に発光ダイオー
ド素子D1，D2、…を一列に配置して形成するが、
発光ダイオード素子D1，D2、…へ通電するため
に分離して施した発光ドツト電極L1，L2、…D1，
D2、…は、交互に配列の両側に引出するもので
ある。 It is formed by arranging light emitting diode elements D 1 , D 2 , ... in a row on an LED array chip C 1 made of GaAs or the like.
Light-emitting dot electrodes L 1 , L 2 ,...D 1 , applied separately to supply electricity to the light-emitting diode elements D 1 , D 2 , ...
D 2 , . . . are drawn out alternately on both sides of the array.
発光ドツト電極L1，L2、…は、ワイヤボンデ
イングによつてLEDアレイチツプC1外の発光電
極の配線回路２に接続するが、両側に発光ドツト
電極ドツト電極L1，L2、…を引出すことは、ワ
イヤボンデイングの接続密度を軽減して実装を容
易ならしめる効果が大である。また、LEDアレ
イチツプC1の裏面は、共通電極K1になつている。 The light emitting dot electrodes L 1 , L 2 , ... are connected to the wiring circuit 2 of the light emitting electrode outside the LED array chip C 1 by wire bonding, but the light emitting dot electrodes L 1 , L 2 , ... are drawn out on both sides. This has a great effect of reducing the connection density of wire bonding and making mounting easier. Further, the back surface of the LED array chip C1 serves as a common electrode K1 .
そして。極性は、各共通電極Ｋがアノードにな
る場合と、カソードになる場合との二通りある
が、以下の説明では、発光ドツト電極L1，L2、
…がアノードで各共通電極Ｋがカソードであるカ
ソードコモンとして扱うことにする。 and. There are two polarities: when each common electrode K becomes an anode and when it becomes a cathode, but in the following explanation, the light-emitting dot electrodes L 1 , L 2 ,
... is an anode and each common electrode K is a cathode, which is treated as a cathode common.
第３図は、第１図のＸ−Ｘにおける結線状態を
示す断面図である。 FIG. 3 is a sectional view showing the wiring state along line XX in FIG. 1.
この図において、LEDアレイチツプC1の発光
ドツト電極は、共通電極の配線回路３を越えて、
ワイヤ４１，４２により発光ドツト電極の配線回
路２に接続する。そして、この発光ドツト電極の
配線回路２は、図示省略の隣接のLEDアレイチ
ツプの、相対的に同位置にある発光ドツト電極を
２層配線構成（図示せず）で並列配線２ａとする
ように延長され、他端ドライバIC５１，５２の
出力端にワイヤ４３，４４によつて接続する。 In this figure, the light emitting dot electrode of the LED array chip C1 extends beyond the wiring circuit 3 of the common electrode.
The light emitting dot electrodes are connected to the wiring circuit 2 by wires 41 and 42. The wiring circuit 2 of the light-emitting dot electrodes is extended by extending the light-emitting dot electrodes of adjacent LED array chips (not shown), which are located at the same relative position, into parallel wiring 2a in a two-layer wiring configuration (not shown). The other end is connected to the output end of the driver IC 51, 52 by wires 43, 44.
ここで、隣接のLEDアレイチツプが別のグル
ープになるように、発光ドツト電極の配線回路２
を形成したのは、第４図ｂが、例えば、LEDア
レイチツプを配列した長さ方向の中央を境にし
て、図の左右２グループに分割するようにした第
４図ａに比べると分かるように、配線スペースＡ
を最小にするためである。このように、２つの
LED素子の駆動を１つのドライバで行うことが
できるようにしている。これによつてドライバの
数は全LED素子の半数で済むものである。 Here, connect the wiring circuit 2 of the light emitting dot electrodes so that adjacent LED array chips are in different groups.
The reason for this is that Figure 4b is divided into two groups on the left and right sides of the figure, as shown in Figure 4a, where the LED array chips are divided into two groups on the left and right sides of the figure, for example, with the center of the length of the LED array chips arranged as a border. , wiring space A
This is to minimize the In this way, two
The LED element can be driven with a single driver. This allows the number of drivers to be half of all LED elements.
第５図は、第１図のＹ−Ｙ線におけるLEDア
レイチツプの配列状態を示す断面図である。 FIG. 5 is a sectional view showing the arrangement of LED array chips along the line Y--Y in FIG. 1. FIG.
LEDアレイチツプC1，C2，C3、…の共通電極
K1，K2、K3、…は、第１図の共通電極の配線回
路３の櫛の歯の一つ一つの歯部３１，３２，３
３、…に対応させて、導電性塗料等により、裏側
に接着して固定するものである。 Common electrode of LED array chips C 1 , C 2 , C 3 ,...
K 1 , K 2 , K 3 , ... are the individual teeth 31, 32, 3 of the comb teeth of the common electrode wiring circuit 3 in FIG.
3. In accordance with . . . , it is fixed by adhering to the back side with conductive paint or the like.
このとき、隣接の上記チツプ間は電気的に絶縁
されるように、ギヤツプをもつて、ないしは当該
チツプ間に絶縁物を介在させて、一直線に配列固
定するものである。 At this time, adjacent chips are arranged and fixed in a straight line with a gap or with an insulator interposed between them so that they are electrically insulated.
そして、櫛形配線でもつて、一つ置きのLED
アレイチツプをグループ化する母線は、チツプ配
列に並列して引出されるので、発光ドツト電極の
ワイヤボンデイング列を横切つて、そのスペース
を減じるような干渉障害は全く無いものである。 And even with comb-shaped wiring, every other LED
Since the busbars grouping the array chips are drawn out parallel to the chip arrangement, there is no interference across the wire bonding rows of light emitting dot electrodes to reduce their spacing.
残りのLEDアレイチツプをグループ化する、
もう一つの櫛形のコモン配線は、第１図をみて分
かるように、他方のそれと噛み合うように施さ
れ、その母線は、チツプ配列に関し反対側に在つ
て、同じく配列方向に引出される。 Group the remaining LED array chips,
As can be seen from FIG. 1, the other comb-shaped common wiring is arranged to mesh with the other one, and its busbar is located on the opposite side with respect to the chip arrangement and is also drawn out in the arrangement direction.
このようにして、奇数番目のLEDアレイチツ
プと偶数番目のLEDアレイチツプとは、電気的
に互いに分離して扱うことができる。 In this way, the odd-numbered LED array chips and the even-numbered LED array chips can be treated as electrically separated from each other.
以上のようにして構成したLEDアレイヘツド
は、第６図に示す駆動回路によつて駆動するもの
である。 The LED array head constructed as described above is driven by the drive circuit shown in FIG.
図において、SRはシフトレジスタ、Ｌはラツ
チ回路、TRはドライバであり、これらで駆動回
路を形成する。また、１０はLEDアレイチツプ
C1，C2，C3、…を配列したLEDアレイで、６１，
６２は時分割用のドライバである。 In the figure, SR is a shift register, L is a latch circuit, and TR is a driver, and these form a drive circuit. Also, 10 is an LED array chip
An LED array consisting of C 1 , C 2 , C 3 , ..., 61,
62 is a time division driver.
しかして、１ラインの画データのうち、最初に
奇数番目のLEDアレイチツプに対する画データ
をシフトレジスタSRの入力端子Ｄからシリアル
に入力し、クロツクCKにより転送し、転送終了
後にラツチ回路Ｌにパラレルに出力する。 Of one line of image data, the image data for the odd-numbered LED array chip is first serially input from the input terminal D of the shift register SR, transferred by the clock CK, and after the transfer is completed, the image data for the odd-numbered LED array chip is input in parallel to the latch circuit L. Output.
ラツチ回路Ｌは、そのデータによりドライバ
TRを動作させる。 The latch circuit L is driven by the data.
Operate TR.
このとき、駆動回路は、第４図のｂで述べたよ
うに、発光ドツト電極の配線回路２によつて、そ
の駆動範囲が隣接チツプにも及んでいるが、ドラ
イバTRの駆動に同期して分割用のドライバ６１
を動作させ、奇数番目のLEDチツプのみ選択的
に発光させるものである。 At this time, as described in FIG. 4b, the driving range of the driving circuit extends to the adjacent chip due to the wiring circuit 2 of the light-emitting dot electrode, but the driving circuit does not operate in synchronization with the driving of the driver TR. Division driver 61
, and only the odd-numbered LED chips selectively emit light.
次いで、画データの残り、すなわち偶数番目の
LEDアレイチツプに対する画データを、同様に
操作してドライバTR及び６２を駆動し、偶数番
目のチツプを選択的に発光させる。このようにし
て時分割駆動よつて１ラインの駆動を完成させ
る。 Next, the rest of the image data, that is, the even numbered
The image data for the LED array chips is similarly manipulated to drive the drivers TR and 62 to selectively cause even-numbered chips to emit light. In this way, driving of one line is completed by time-division driving.
以上に説明したように、本実施例では、櫛形の
共通電極の配線回路を適用することにより、発光
ドツト電極との接続スペースに何ら障害とならな
いように配線形成ができるので、LEDアレイヘ
ツド基板サイズを増大させることなくLEDアレ
イヘツドを構成できるものである。 As explained above, in this example, by applying a wiring circuit with a comb-shaped common electrode, wiring can be formed without any obstruction to the connection space with the light emitting dot electrodes, so the size of the LED array head board can be reduced. It is possible to construct an LED array head without increasing the size.
また、時分割駆動の構成とすることによつてド
ライバ数は半数で済み、したがつてワイヤボンデ
イングの工数も半減する。コスト低減に大きな利
点がある。 Further, by employing a time-division drive configuration, the number of drivers can be reduced by half, and the number of steps for wire bonding can also be reduced by half. There is a big advantage in cost reduction.
以上の実施例では、LEDアレイを２分割にす
る場合について説明した。 In the above embodiments, the case where the LED array is divided into two parts has been described.
これは、発光ドツト電極の配線回路での並列配
線のため、基板は二層配線構成になつているの
で、３分割および４分割用の共通電極の配線回路
布設は容易に可能なものである。その実施例を次
に述べる。 This is due to the parallel wiring in the wiring circuit of the light-emitting dot electrodes, and since the board has a two-layer wiring structure, it is easy to install the wiring circuit of the common electrode for dividing into three and four parts. An example will be described below.
すなわち、第７図のａ，ｂは、本発明の他の実
施例に係るものの配線回路である。 That is, a and b in FIG. 7 are wiring circuits according to another embodiment of the present invention.
図において、C1，C2，C3、…は、LEDアレイ
チツプ、B1，B2，B3，B4は、分割用の、共通電
極に配線回路である。 In the figure, C 1 , C 2 , C 3 , . . . are LED array chips, and B 1 , B 2 , B 3 , B 4 are wiring circuits connected to a common electrode for division.
これらの実施例においても、櫛形の共通電極の
配線回路布設により、LEDアレイの発光ドツト
電極部の接続部に対して、何ら障害になずに時分
割駆動を可能にしているから、ドライバ数低減に
よるコストダウンの効果がある。 In these examples as well, the wiring circuit of the comb-shaped common electrode enables time-division driving without any hindrance to the connections between the light-emitting dot electrodes of the LED array, reducing the number of drivers. This has the effect of reducing costs.
しかして、上記の実施例に係るものは、発光ダ
イオード素子を複数のグループに分け、そのグル
ープ数の共通電極配線回路を有するようにしたも
のであるが、これは、そのグループ数の複数の共
通電極の配線回路を有するようにすることを妨げ
ないものである。 However, in the above embodiment, the light emitting diode elements are divided into a plurality of groups, and the number of common electrode wiring circuits is equal to the number of groups. This does not preclude the provision of an electrode wiring circuit.
また、上記実施例に係るものは、電子写真記録
式光プリンタの発光ダイオードアレイに係るもの
として説明したが、本発明は、表示用の発光ダイ
オードアレイとして、広く汎用的なものである。 Although the above embodiments have been described as relating to light emitting diode arrays for electrophotographic optical printers, the present invention is widely applicable to light emitting diode arrays for display purposes.
本発明によれば、櫛形の配線を適用することに
より、発光ドツト電極の接続スペースを犠牲にす
ることなく時分割駆動用の配線布設を行うことが
できるので、ドライバ数が減り、低コストの
LEDアレイヘツドを提供できるものである。
According to the present invention, by applying comb-shaped wiring, wiring for time-division driving can be laid without sacrificing the connection space of the light emitting dot electrodes, so the number of drivers is reduced and the cost is reduced.
It can provide an LED array head.
第１図は、本発明の一実施例に係る発光ダイオ
ードアレイヘツドの略示配線回路図、第２図は、
それに使用される発光ダイオードアレイチツプの
表面拡大斜視図、第３図は、その発光ダイオード
アレイの結線を示す断面図、第４図のａ，ｂは、
その効果説明図、第５図は、その発光ダイオード
アレイチツプの配列状態を示す断面図、第６図
は、その動作説明駆動回路図、第７図のａ，ｂ
は、本発明の他の実施例に係るものの配線回路図
である。
１……絶縁性基板、２……発光ドツト電極の配
線回路、２ａ……並列配線、３……共通電極の配
線回路、３ａ……引出しリード、３１，３２，３
３……歯部、４１〜４４……ワイヤ、５１，５２
……ドライバIC、６１，６２，TR……ドライ
バ、C1，C2，C3……発光ダイオードアレイチツ
プ、D1，D2……発光ダイオード素子、L1、L2…
…発光ドツト電極、K1，K2，K3……共通電極、
SR……シフトレジスタ、Ｄ……入力端子、CK…
…クロツク、Ｌ……ラツチ回路、B1〜B4……共
通電極の配線回路。
FIG. 1 is a schematic wiring circuit diagram of a light emitting diode array head according to an embodiment of the present invention, and FIG.
FIG. 3 is an enlarged perspective view of the surface of the light emitting diode array chip used for this purpose, and FIG. 3 is a sectional view showing the connections of the light emitting diode array.
Fig. 5 is a cross-sectional view showing the arrangement of the light emitting diode array chips, Fig. 6 is a drive circuit diagram explaining its operation, and Fig. 7 a and b.
is a wiring circuit diagram of another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Wiring circuit of light emitting dot electrode, 2a... Parallel wiring, 3... Wiring circuit of common electrode, 3a... Output lead, 31, 32, 3
3... Teeth, 41-44... Wire, 51, 52
... Driver IC, 61, 62, TR ... Driver, C 1 , C 2 , C 3 ... Light emitting diode array chip, D 1 , D 2 ... Light emitting diode element, L 1 , L 2 ...
...Light-emitting dot electrode, K 1 , K 2 , K 3 ... Common electrode,
SR...Shift register, D...Input terminal, CK...
...Clock, L...Latch circuit, B1 to B4 ...Common electrode wiring circuit.
Claims (1)
配置し、そのそれぞれの発光ダイオードアレイチ
ツプの発光ドツト電極の配線回路と、同発光ダイ
オードアレイチツプの共通電極の配線回路とを有
する発光ダイオードアレイヘツドにおいて、各別
の発光ダイオードアレイチツプにおける発光ドツ
ト電極の発光ダイオード素子を複数のグループに
分け、その発光ドツト電極に対し相対的位置を同
じくする発光ダイオード素子に対して並列配線を
施した発光ドツト電極の配線回路と、櫛形の形状
で、発光ダイオードアレイチツプの配列側端に引
出しリードを有し、上記のグループ数、あるいは
その複数の、共通電極の配線回路とを有するよう
にしたことを特徴とする発光ダイオードアレイヘ
ツド。1. In a light-emitting diode array head in which a large number of light-emitting diode array chips are arranged in a row, each light-emitting diode array head has a wiring circuit for the light-emitting dot electrode of each of the light-emitting diode array chips, and a wiring circuit for the common electrode of the same light-emitting diode array chip. A wiring circuit for a light emitting dot electrode in which the light emitting diode elements of the light emitting dot electrode in another light emitting diode array chip are divided into a plurality of groups, and the light emitting diode elements having the same relative position with respect to the light emitting dot electrode are wired in parallel. and a comb-shaped light emitting diode, which has an extraction lead at the end of the array side of the light emitting diode array chip, and has a common electrode wiring circuit of the number of groups mentioned above, or a plurality thereof. Array head.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59191699A JPS6170772A (en) | 1984-09-14 | 1984-09-14 | Head of light-emitting diode array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59191699A JPS6170772A (en) | 1984-09-14 | 1984-09-14 | Head of light-emitting diode array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6170772A JPS6170772A (en) | 1986-04-11 |
| JPH0443434B2 true JPH0443434B2 (en) | 1992-07-16 |
Family
ID=16279003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59191699A Granted JPS6170772A (en) | 1984-09-14 | 1984-09-14 | Head of light-emitting diode array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6170772A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4238672A1 (en) | 2022-03-04 | 2023-09-06 | Ricoh Company, Ltd. | Lamination fabricating method |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62191437U (en) * | 1986-05-28 | 1987-12-05 | ||
| DE29913603U1 (en) * | 1999-08-04 | 1999-11-25 | Oculus Optikgeräte GmbH, 35582 Wetzlar | Slit projector |
| JP4581759B2 (en) * | 2005-03-14 | 2010-11-17 | セイコーエプソン株式会社 | LIGHT EMITTING DEVICE, IMAGE FORMING DEVICE, AND ELECTRONIC DEVICE |
-
1984
- 1984-09-14 JP JP59191699A patent/JPS6170772A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4238672A1 (en) | 2022-03-04 | 2023-09-06 | Ricoh Company, Ltd. | Lamination fabricating method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6170772A (en) | 1986-04-11 |
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