JPH0440915B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for correcting timing errors in digital data streams, which is particularly preferred for correcting errors introduced into digitized color television signals by signal recording and playback processing.

According to the invention, the digital rate of the digitized data stream is first synchronized with the rate of the reference rate signal. Following this synchronization, the digitized data stream is synchronized with the occurrence of a periodic reference time signal. To achieve these synchronizations, the digital data stream is provided with a selected sequence of periodically occurring digital data bits in phase with the digital data to control the synchronization of the two. The apparatus for achieving these synchronizations includes a first digital data memory for temporarily storing a stream of digital data. The digital data is stored in the memory at a rate determined by a first clock signal and retrieved from the memory at a rate determined by a second clock signal. One of the two clock signals is at a rate that varies according to the timing error, and the other clock signal is at a reference rate. The relative times of storage and playback in this first digital data memory are initialized according to the occurrence of a selected sequence of digital data bits contained in the digital data. As a result of the above-described control of storing and reproducing digital data in the first digital data memory, the digital data becomes at a speed synchronized with the reference speed.

Given that the digital data reproduced from said first digital data memory also has to be synchronized to a periodic reference time signal, this reproduced data is applied to a second digital data memory and said digital data of said selected sequence is synchronized to a periodic reference time signal. It is further temporarily stored for a time interval determined by the time difference between the occurrence of the data bit and the reference time signal. By using this second digital data memory, the digital data stream can be synchronized both with respect to a reference speed signal and a periodically occurring reference time signal. The apparatus of the present invention is particularly suited for correcting timing errors present in color television signals since it allows correction of timing errors with respect to the reference chrominance subcarrier signal and the reference horizontal line rate related signal. Furthermore, the apparatus of the invention provides two digital data memories for each of the data streams and controls all memories to synchronize these data streams with respect to a common reference speed signal and a common reference time signal. By doing so, timing errors of multiple digital data streams can be easily corrected.

More broadly with respect to FIGS. 1-3, the present invention relates to a recording and reproducing apparatus 70, indicated at 70 in FIG.
It has two racks 71 and 72 containing various monitoring and control elements, particularly shown on the top of rack 72, along with the electrical circuitry associated with the device 70. The device 70 also includes:
There is a pair of disk drives 73 located adjacent to the right rack 72, each drive having a disk pack 75 attached thereto. Although two disk drives are shown in FIG. 1, additional disk drives may be added to increase the on-line storage capacity of device 70. Although a single disk drive can be used, many of the functions described below cannot be achieved with a single disk drive. The operation of the device 70 is
It is controlled by one or more operators using a number of access station devices, such as the remote access station or internal access station 78 in the rack 72 shown. If desired, a video monitor 79, vector and "A" oscilloscope may be used as shown on rack 72. A "phase" control switch 81 is located above the internal access station 78.

The example device is controlled by an operator using an internal access station 78 or a remote access station 76. Both stations have a keyboard, which has numeric and function keys and bars, and a 32-character display 82, which in use provides a readout of the information necessary to perform the functional operations, as well as an address display. Displays information regarding the identity of a certain still being displayed and other information. The remote access station 76 shown in FIG. 2 is representative of each remote access station; in a preferred embodiment, up to seven remote access stations may be used to control device 70. The internal access station keyboard, shown generally as 83 in FIG. 1 and also shown in enlarged cutaway view in FIG. 3, has greater operational capabilities than the remote access station (which has fewer function keys). There is. As described later,
The keyboard has a large group of keys, generally indicated at 84, and a small group of keys, indicated on the left side of the keyboard, 8.
5. A control switch 86 may also be provided to toggle between normal and delete operations to avoid the possibility of inadvertent erasure of stills currently in use.

In the highly simplified block diagram shown in FIG.
receives a video input signal which is then processed by a recording signal interface circuit 89.
and from there all disk drives 73
A signal is given to A gating circuit in the selected disk drive 73 causes the signal to be recorded in the selected drive. More than one disk drive 73 can also be selected at the same time to record the video signal provided by recording signal interface circuit 89. A switch circuit can be used in place of the signal interface and associated gate circuits, supplying the signal provided by the recording signal processing circuit 88 only to the selected disk drive whose disk pack 75 is to record the signal. You may also do so.
During playback, a signal from one of the disk drives is applied to a playback switch circuit 90 which provides a signal to one of playback channels 91, each of which provides a video output channel. A computer control system 92 includes a recording signal processing circuit 88,
interfaced with the record signal interface circuit 89, the playback switch circuit 90 and the disk drive 73, and is connected to the remote access station 7.
6 and an internal access station 78. As will be explained below, if a disk pack is online, i.e. it is physically loaded into one of the disk drives 73, then
The operator can select a particular disk for still recording. In this regard, the embodiment device is adapted to identify up to 64 separate disk packs, only one of which can be arbitrarily placed on one disk drive. It should be understood that it addresses the disk pack rather than the disk pack. Therefore, if the embodiment system has two disk drives, only two disk packs can be brought online at a time. The operator can use the access station keyboard 83 to enter the address of one disk pack on which he wishes to record stills, and by computer interaction with the disk drive loaded with the selected disk pack, the selected online disk Recording operations can be performed on packs. Similarly, the operator can play still frames from a disk pack of one disk drive and can define the playback channel in which he wishes to play the still frames.

The example device has four main modes of operation: (1) record/delete, (2) playback, (3) sequence assembly, and (4) sequence playback.
Recording and playback operations will first be described with reference to FIGS. 6 and 7. These figures show the disk drive 73.
2A and 2B respectively show schematic block diagrams of signal paths during recording and reproduction associated with one of the following.

In the recording signal path block diagram of FIG. 6, the composite video input signal is first applied to an input stage circuit 93, where the signal is clamped and the synchronization and subcarrier components are separated from the composite video signal. taken out. The input stage circuitry also regenerates the sync and subcarrier signals for use during subsequent playback, and thus the regenerated sync and subcarrier signals serve as reference signals used in operation by the subsequent elements. is applied to a clock generator 94 which generates a clock signal. The clamped analog video signal with the color burst component is then provided to an analog-to-digital (A/D) converter 95, which
Gives an output signal at a sampling rate of 10.7MHz. In this case, each sample value consists of 8 bits of information. The output digital video signal is a non-return to zero (NRZ) code. That is, the binary code defines "1" as a high level and "0" as an equivalent low level. The digitized video signal is produced in eight parallel lines (each line corresponding to a respective bit) and then applied to an encoder and sync word inserter 96, where the digital magnetic For recording, it is converted into a special recording code (mirror code or mirror squared code) which is particularly good. This circuit also inserts synchronization words into alternate television lines for a particular phase angle of the color subcarrier represented by the color burst synchronization component. This synchronization word is used as a reference for correction of time base and skew errors that occur during playback between the eight parallel bits of data that must be combined to define the numerical value represented by each sample. The digital video information in eight parallel lines is then transferred to a recording amplifier circuit 153 and a selected disk drive which switches between two groups of eight recording heads for recording the digitized video signal by disk drive 73. 73 and associated head switch circuit 97. The disk drive is servo-controlled so that the rotational speed of its spindle is locked in vertical synchronization and the speed of the rotating disk is 3600 revolutions per minute. By locking the spindle drive to vertical synchronization, the device records one television field per rotation of the disk pack,
Eight data streams are recorded on eight disk surfaces simultaneously. Upon completion of recording one field,
Recording amplifier circuit 153 and head switch circuit 97
The television frame is recorded on another set of eight disk surfaces so that the image frame, or two scanned television fields, are recorded in two revolutions of the disk drive using 16 heads. Another set of heads is commanded to simultaneously record a second field. Each disk pack located in one disk drive has 815
cylinders, each of which is
It has 19 recording planes and therefore records 815 digital television frames. There is one read/write head for each of the 19 disk recording surfaces of a disk pack, and all heads are mounted in vertical alignment on a common carriage whose position is controlled by a linear motor. It is being It should be understood that one cylinder is defined to have all recording surfaces located on the same radius of one disk pack. but,
The term "track" is used in the text instead of "cylinder" and is therefore meant to include all recording surfaces of the same radius, ie, the entire surface on the cylinder. Thus, the addressed track for recording or playing stills actually points to the 19 individual surfaces on the cylinder available in that radius. Of the 19 surfaces available for recording, one is
It is used to record addresses and other reference information in place of valid video information, and is specifically referred to as a "data track." Two of the 19 surfaces are utilized to record one variation bit, and 16 surfaces are used to record video data as further described below. Also, one of the heads, commonly referred to as the servo head, moves over the 20th disk pack surface, which contains only servo track information previously recorded by the pack manufacturer. This servo track performs two functions: following a search command, the head staff traverses the servo track which is counted to determine the immediate position of the head, and after completion of the search mode, the servo head moves the head carriage to the appropriate servo track. Generates an error signal that is used to control the linear motor position to keep it centered on the track. By using such a field pack system, 1 inch (approx.
It is possible to achieve a radial packing density of approximately 400 tracks per disk pack (25.4 mm), or a total of 815 tracks per disk pack.

Because the device does not record analog video signals due to frequency response limitations of disk pack memory, the video signals are digitized for recording. Because a digitized signal is recorded, the video signal-to-noise ratio of the system is determined primarily by quantization noise rather than recording medium and preamplifier noise, as in conventional video tape recorders. In this way, the device has approximately
It produces a signal-to-noise ratio of 58 dB, effects such as moiré and residual timebase errors are absent, and digital random errors in the storage channel are low enough to cause incidental transmission errors that are often virtually invisible. It is.

By recording a digital data stream at a rate of 10.7 megabits per second on each of the eight disk surfaces, the device's linear packing density is approximately 6000 bits per inch, which is much higher than traditional disk drive applications in data processing. Approximately 60% larger than that used for.

During playback, in FIG. 7, the head reads or plays back digital video information from eight sides per field to obtain a recorded channel-encoded digital video signal from the two fields forming each image frame. . The reproduced signal is
amplifying a data stream of digital video information carried by eight data bit lines and providing it to an equalization and data detection circuit 99;
The signal is applied to a regenerative amplifier circuit 155 and a head switch circuit 97 associated with the selected disk driver 73. The equalization circuit compensates for phase and amplitude distortions introduced into the signal by the band-limiting effects of the recording and playback process, and ensures that the zero-crossings of the playback signal are clearly and accurately located. Following equalization, the channel encoded signals on each data bit line are processed as described below for transmission on twisted pair lines to the regeneration circuitry of the signal system. The channel encoded signal to be processed is in the form of a pulse for each zero crossing or signal state transition of the channel encoded signal. Twisted pair lines for the eight data bits of digital video information provide processed channel encoded signals to the decoder and time base correction circuit 100 of one or more playback channels 91 of the apparatus. The decoder and time base correction circuit 100 reprocesses the received signals, puts them into a channel encoded format, decodes the signals into non-zero return digital form, and time base corrects the digital signals with respect to the station reference. , eliminates time displacement errors (commonly referred to as skew errors) and timing distortions between data bit lines in each data stream carried by the data bit lines. To facilitate reproduction signal processing, a phase continuous clock signal is used to cause the decoder and time base correction circuit 100 and subsequent circuits to operate at appropriate times.
As will be discussed in more detail below, this allows the time base corrector portion of circuit 100 to accurately position the synchronization word during alternate playback of image frames.
The time base corrector portion of circuit 100 thus serves to align the eight bits defining one sample and remove timing distortion in each data bit line relative to the station reference. However, the above-mentioned error in the position of the synchronization word causes the image to shift in the horizontal direction during alternate playback, resulting in the appearance of jitter in the displayed video. Each playback channel has a decoder/time axis correction circuit 1
00 is provided and that within each playback channel each of the eight data bit streams passes through a separate decoder and time base correction circuit. The output of circuit 100 is then provided to a comb filter and saturation inverter circuit 101 which separates the chroma or chroma information, which also has a four-field
Selectively invert and recombine the signals for reconstruction of the NTSC sequence. This reconstructed digital signal is fed to a circuit 127 that adjusts for errors in the position of the synchronization word in the alternating playback of two recorded fields of video information, and the adjusted video signal provides an analog video signal. A digital to analog converter 102 is provided. The new synchronization and burst are then applied to process amplifier 103.
are summed to produce the composite video analog output signal of the desired playback channel 91.

Details of the video signal system shown in FIGS. 5 and 6 are shown in FIGS. 7A and 7B. However, the previously used reference numbers remain where the corresponding functions are performed. 7th A
The block diagrams of Figures 7B and 7B also illustrate the flow of video data through the signaling system, along with other interconnecting lines necessary to control the timing and synchronization of the circuits represented by the various blocks. Contains lines. Also shown is the interconnection of the signal system to the computer control system 92, in this case the seventh
The input and output lines from the various blocks in FIGS. A and 7B are lines that extend to computer control system 92.

In addition, the embodiment device has 525 horizontal synchronization pulses (also referred to as "H synchronization" in the text) generated at a rate of about 15.734 Hz, which means that the period between consecutive H pulses is about 63.5 microseconds. Has a television field consisting of lines of books
It shall be described regarding use in the NTSC system. Furthermore, vertical blanking in the NTSC system occurs at a frequency of 60 Hz, ie the chrominance information is modulated on a subcarrier signal having a frequency of approximately 3.58 megahertz (MHz). Because of the phase relationship of the color subcarrier with respect to the horizontal synchronization signal, the NTSC color signal has four field sequences, commonly referred to as color frames. The subcarrier frequency of 3.58Hz is 1
×Simply denoted as SC, meaning subcarrier frequency; similarly, the clocking frequencies used include 1/2SC, 3SC, and 6SC. This 3x subcarrier frequency (3SC) arises because a sampling rate of 3x subcarrier frequency, ie 10.7 MHz, is used during sampling of the analog composite video signal for digitization of the signal. NTSC composite video signals are generally known.

With respect to FIG. 7A, before discussing the function of each block shown in the figure, broad general concepts regarding the overall operation of the illustrated signaling system should be understood. First, video input circuit 93A
The video input signal sent to is an analog signal provided to an analog-to-digital converter 95 for processing. The output of the converter contains video information in digital format, and the digitized data is further processed and recorded on a disk pack in digital format. Similarly, this data is recovered from a disk pack, time-corrected, chroma-separated, processed using digital techniques, and then converted to analog by a digital-to-analog converter 102.
and sync burst insertion circuit 103 provides a composite video output.

In the analog-to-digital converter 95,
The analog composite video signal is sampled at a sampling rate of three times the nominal subcarrier cycle, or 3SC (10.7MHz), and each sample is digitally quantized into an 8-bit digital word.
A sampling clock having a frequency that is three times the NTSC subcarrier frequency or any odd multiple is necessarily an odd multiple of half the horizontal line frequency.
If such a sampling clock is phase continuous between each line, its phase at the beginning of successive lines will change. The use of such a line-to-line phase continuous sampling clock results in the instantaneous amplitude of the analog signal being sampled between successive lines a different number of times with respect to the beginning of successive lines. Therefore, the quantized samples are not vertically aligned from line to line. Vertical alignment of line-to-line samples combines the separate chroma components of the television signal by combining quantized samples from three consecutive television lines (all in odd or even fields) of the television field. is required to facilitate the use of a digital comb filter to obtain (chromaticity), where the three television lines are T (top), M (middle), and B (bottom). It is expressed as C=M-1/2(T+B) (luminance) Y=M+1/2(T+B).

If the samples of the NTSC television signal are even multiples of the subcarrier frequency, then the comb filter technique is ideal. This is because the phase of the sampling clock does not change from line to line. Thus, the digital code word or quantized sample represents the instantaneous amplitude of each line of the analog signal at the same point in time relative to the start of each line, and all of the samples in three consecutive lines range from top to middle to bottom. It is vertically aligned towards the line.

It is clear from FIG. 7C1 that there is no vertical alignment of consecutive line samples when using a 3SC line-to-line phase continuous sampling clock. The cycle of the subcarrier of television line 1 is shown, sampled at the positive transition of the 3SC sample clock (Figure 7C3), where the upward transition has an arrow representing the "X" sample point, which Every sample point is placed on the subcarrier of television line 1. As shown, there are three samples in each cycle of the subcarrier. However, television line 2
That is, during the next following line, the subcarrier is the 7th C.
Similarly, the sampling clock 3SC has opposite phases as shown in Fig.
(Fig. 7C4), so that during television line 2 the sample is on an upward transition in the position indicated by X on the subcarrier of television line 2 (Fig. 7C2). , line 1 to line 2 are offset by 60 degrees, which adversely affects the response of the comb filter, which uses the instantaneous amplitude of the analog signal in the above formula to obtain the correct chromaticity information. Therefore, samples taken on all odd lines are vertically aligned, and samples taken on all even lines are vertically aligned, but samples taken on even lines are vertically aligned. It is clear that the sample on the line is displaced by 60°.

To avoid problems caused by sampling at odd multiples of the subcarrier frequency, i.e. 3SC in the device described in the text, vertical alignment on all lines can be achieved by changing the phase of the sampling clock for alternate lines. . FIG. 7C5 shows the sampling phase for television line 2 whose phase is reversed with respect to the sampling phase for television line 2 shown in FIG. 7C4.
3SC sampling clock is shown. By sampling the upward transition at the sampling point of ``0'', ``0'' appears on the subcarrier for line 2.
A sample indicated by is generated as shown in FIG. 7C2. Therefore, the subcarrier sample point ("X") for television line 1 is 9C4.
7 than what normally occurs as shown in the figure.
It is vertically aligned with respect to the sample point ("0") sampled using the every-other phase sampling clock shown in Figure C5. This technique is called phase alternating line encoding or PALE.
is commonly referred to as, and the terms "PALEd" and "PALE
” etc. are used in the description of the device described in the text.

Although the device described here uses a comb filter technique with a 3SC or 10.7 MHz sampling rate and requires the use of a PALE sampling clock, the use of a 4SC sampling frequency eliminates the need for PALE processing. You will find that it does. The use of 4SC sampling frequency is
If the frequency response of the recording medium, ie, the disk pack of the disk drive device, is sufficient to allow operation at a frequency of 4SC, 14.3 MHz, it is within the scope of the concept of the device described in this text. in this case,
It will be appreciated that standard disk drives used for data processing applications operate primarily in the range of about 6 1/2 megabits, and recording at speeds of 10.7 MHz represents a significant improvement in the pack density of the disk pack itself. .

Another important aspect of the operation of the apparatus, which is a result of the use of PALE processing, is also described above with respect to FIG. 7C. Changes in the phase of the sampling clock on each successive line necessitate phase discontinuities with respect to the SC. During channel encoding of the signal for use in later recording, it is further advantageous to channel encode the digitally quantized samples with respect to a continuous phase clock, so that there is no line-to-line phase discontinuity. be. For this reason, during recording, the PALE'd data present at the output of the analog-to-digital converter 95 is clocked out from the channel encoder 96 using a clock with a phase of 3 SC that is continuous (i.e., unbroken) from line to line. . However, clocking the encoder 96 using a continuous phase clock from line to line will shift the data in time on alternate lines by 1/2 cycle of 3SCs, so sampling using the PALE clock will This would compromise the resulting line-to-line sample time alignment. During playback, the chroma or saturation processing circuitry requires samples of the data to be vertically aligned line by line (this is why the PALE sample clock was first used in analog-to-digital converters 95). ,
It is necessary to retime or reclock the data from the continuous phase clock to the PALE clock to remove sample time disturbances and allow the saturation comb filter to process the data without error. Simply put, the A/D converter 95 is a PALE converter with line-by-line phase discontinuity.
Sample the analog signal using a clock.
For recording, channel encoder 96 is connected to the PALE clock for use by the saturation processing circuit.
Retiming the NRZ information during playback and after decoding encodes the required PALE data using a line-by-line continuous phase clock. However, retiming from a phase-continuous clock to a PALE clock is not possible during a transfer mode of operation when video data recorded on one disk drive memory is transferred to another disk drive memory for recording and playback. Not implemented. In such a case,
Line-by-line continuous phase data clocking of the reproduced video data is preserved and data is re-recorded without disturbing the data clocking.

The above consideration applies to lines 1 and 2.
PALE data is shown in Figure 7C6 and Figure 7C, respectively.
7C as shown in FIG. Bits A1 through E1 are successive bit cells representing instantaneous samples of the analog video signal occurring on line 1 corresponding to the x shown in Figure 9C1, each bit cell representing a complete clock cycle of the 3SC clocks shown in Figure 7C3. Lasts for cycles. Similarly, bit cells A2 to E2 on line 2
for television line 2, using the PALE sample clock shown in Figure 7C5.
The data obtained by sampling at "0" in Figure C2 is shown. Continuous phase per line
In order to clock the PALE data with the 3SC clock, the arrow below the bit cell shown in Figures 7C6 and 7C7 is shifted to the relationship shown in Figures 7C8 and 7C9 to indicate the clocking point of the bit cell in that state. show. The start of each bit cell occurs at this clocking point, and the cell levels are continuous over the bit cell interval so that the bit cells maintain their coincidence during clocking.

Data from continuous phase clock line by line
Retime the PALE clock to vertically align the bit cell (sample) so that A2 aligns with A1 and B2.
In order to align vertically with B1 and so on, the retiming from the continuous phase clock to the PALE clock must be done correctly, otherwise misalignment of the bit cells will occur. In this regard, retiming or reclocking must be complementary, i.e.
Bit cells clocked in their proper portion in continuous reclocking from PALE must be clocked to the left in continuous to PALE reclocking to cause proper reproduction. Thus, given the line-by-line continuous phase clocked data shown in Figures 7C8 and 7C9, the solid arrows indicate proper complementary clocking for the two television lines, and the solid arrows in Figure 7C10 indicate proper complementary clocking for the two television lines. and results in the retiming of the data to the PALE clock with vertically aligned A1 and A2 bits as shown in FIG. 7C11. Bit cells clocked to the right from reclocking from PALE to continuous,
7C6 and 7C8 with associated clocking arrows (e.g., A
Note that, as is clear from 1), the clock is clocked to the left in the opposite conversion state.
If complementary clocking is not implemented, the bits are clocked as shown in Figures 7C8 and 7C9, resulting in the relationships shown in Figures 7C12 and 7C13.
It is not properly aligned as shown by the dotted clocking arrows in the figure. Reclocking from PALE to continuation or vice versa occurs at various locations as will become clear from the description below.

Additionally, an NTSC television signal has no specification or definition between the horizontal (H) synchronization pulse that occurs on each line and the phase angle of the subcarrier signal, except that the phase of the subcarrier varies by 180° from line to line. It will also be clear that there is no relationship. In other words, the phase angle of the subcarrier signal with respect to the H synchronization signal will change if the video signal source changes.
This variation makes the H sync signal undesirable for use for device control. Therefore, according to the invention, we use the subcarrier of the input signal represented by the color burst synchronization component as the basic timing reference for the system, and instead of the H synchronization of the signal we use the new H synchronization used for timing.
Specifies synchronization related signals. This new H sync related signal is selected to be at half the frequency of the nominal horizontal line. The reason is that this displays the total number of cycles of the subcarrier frequency (455), ie two complete horizontal lines of the subcarrier frequency. Furthermore, the H synchronization related signals are given a special relationship to the subcarriers, ie they are synchronized with respect to the phase angle of the subcarriers. In the recording portion of the signal system, a sync word is inserted into the video signal on alternate or every other television line at locations approximately corresponding to the location of the H sync in the video signal; It is phase coherent with respect to a particular phase angle of the SC resulting from the carrier synchronization component. The location of the new H sync-related signal is defined at the beginning of each image frame and maintained for the duration of the image frame to accurately and consistently define the H sync-related signal with respect to the phase of the subcarrier of the video signal. A video signal is provided having a For the regeneration part of the signal system, an H synchronization related signal, denoted H/2, is provided, which corresponds to a specific phase angle of the reference input subcarrier, the phase angle of which is selectable by the phase control of the regeneration system. is respecified so that it is coherent with respect to

This redefined H synchronization related signal H/2 is used as the basic timing reference signal of the system during playback operations.

Recording of the system using the redefined H synchronization related signals as the horizontal synchronization reference for the system,
Processing signals for playback and other operations is facilitated because a consistent time relationship exists between the subcarriers of the video signal and the redefined H-sync related signals.

Additionally, the use of time-varying internal horizontal reference signals and subcarrier reference signals with respect to the reference synchronization of the television station ensures that the television signal reaches the remote location at the appropriate point in time after undergoing the normal propagation delays that occur. It becomes possible to do so.

Referring again to the block diagrams of FIGS. 7A and 7B, the analog video signal is applied to the input side of an input circuit 93A, which performs some operations during processing of the analog video signal, before it is applied to an analog-to-digital converter 95. It will be done. Input circuit 93A is included in the video signal for use in amplifying the analog video signal, performing DC restoration, and generating timing signals for the signaling system.
Separate the Sync component, detect the level of the HSync chip, and then clip the chip level.
Additionally, HSync is isolated using precision Sync circuitry that is used in generating the regenerated Sync. This circuit also produces a regenerated SC signal derived from the H/2 reference signal generated from the burst of the video input or, in the absence of a burst, from the video input HSync.

Video input circuit 93 shown at the bottom left of FIG. 9A.
A and the reference input circuit 93B have similar functions, that is,
It serves primarily as a video input circuit for the signal recording part of the signal system and as a reference input circuit mainly for the reproduction part of the signal system. Therefore, the same circuit is used for manufacturing and service convenience. However, the input circuits are connected within the device to receive only the input signals needed to perform their respective functions, and although the same signals are produced in each circuit, not all of them are used in each circuit. The reference input to the reference input circuit is the station reference color black video signal containing all components of a color television signal except that its active video portion is at the black level. Thus, bursts, HSync, etc. are present in reference input circuit 93B when they are in video input circuit 93A. In addition, the reference input circuit 93B uses an H phase position adjustment circuit that includes an operator-operated phase control switch 81 to adjust the H phase position of the regenerated HSync used in the regeneration section of the signal system. Receives the H position control signal from a knob switch such as.

As shown, many of the output signals provided by input circuits 93A and 93B are provided to reference logic circuits 125A and 125B associated with each input circuit. Reference logic circuit 125A during recording operation mode
uses inputs from video input circuit 93A, analog-to-digital converter 95, and computer control system 92 to generate multiple recording clock and PALE flag signals at frequencies of 6SC and 1/2SC through precision phase-lock loop circuits. .
PALE flag and 3SC signal are reference logic circuit 125
A is used by A to produce a 3SC PALE sampling clock signal whose phase is set for each line of the video signal by the PALE flag at a frequency of H/2. The PALE flag signal changes state at the rate described above, although the two states of the PALE flag signal are unequal in time, ie, the two states of the PALE flag signal are unequal in time. This is done asymmetrically so that the sampling clock phase for the color burst portion of the video signal coincides with the phase of the subcarrier, and then only that portion of the television line has a sampling phase that alternates on successive lines. This PALE clock is coupled to an analog-to-digital converter 95 and the 3SC
That is, it is a sampling clock signal for obtaining samples at 10.7MHz.

The reference logic circuit 125B is the reference input circuit 93B.
and computer control system 92 to generate a clock reference signal and various other timing control signals at the frequency of the SC. These signals are used in operating the device in modes other than the input video signal recording mode.

During record and playback modes of operation, the reference logic also provides servo Sync for each disk drive to properly operate the disk drives in the proper phase.
Generate a signal.

During the playback mode and other modes of operation other than recording the input video signal, the reference clock generator 98 provides the clock generator 98 with different timings required by the various clocks and parts of the signal system used in such modes. Generate control signals. The reference clock generator includes a reference input circuit 93B,
Reference logic 125B, signal system regeneration section,
Using operator control switch input,
It generates clock signals at frequencies of 6SC, 3SC, SC and 1/2SC as well as various other timing control signals. Reference logic circuits 125A, 125B and reference clock generator circuit 98 both have a signal system clock generator 94 that provides system timing control signals.

Clamped HSync from video input boat
The stripped analog video signal is applied to an analog-to-digital converter 95 that converts the signal to an 8-bit binary encoded signal in PALE-processed NRZ (non-returning) format that is applied to encoder switch 126. This analog-to-digital converter 95 is structurally and functionally the same as that built in the Digital Swim Base Collector No. TBC-800 manufactured by Ampex Corporation, and therefore will not be shown in detail in this text. A diagram of the analog-to-digital converter 95 is shown in catalog No. 7896382-02 published October 1975. The specific circuit of the analog-to-digital converter is shown in schematic diagram No. 3-31/32 of the catalog.
1374256, and schematic diagram No. 1374259 on pages 3-37/38 of the same catalog. These and other schematic diagrams are cited in the text for reference.

The output from the analog-to-digital converter is then sent to an encoder switch 126 which receives data from the converter or from the data transfer circuit 129.
The switching circuit typically receives 8-bit digitized video data from a computer. As described below, data transfer circuit 129 allows video information to be transferred from one disk drive to another, as described above with respect to operation of the device using remote or internal access stations. . In the transfer mode of operation, digitized information is read from the disk drive and
It is decoded to NRZ digital format, timebase corrected, and then provided to an encoder switch that can select any source of digitized video information for encoder 96. Because the channel encoded data recorded on disk drive 73 was clocked with a continuous phase clock, the NRZ data received by data transfer circuit 129 is also timed with respect to the continuous phase clock. Normally, the data transfer circuit 129 is
to the PALE clock signal so that the data provided to the chroma separator and processing circuit 101 is in the proper PALE processed format.
Provided with a PALE flag signal used to perform retiming of NRZ digital data.
During the transfer mode of operation, this retiming is not necessary. Encoder switch 126 includes circuitry that interrupts the coupling of the PALE flag signal to data transfer circuit 129, thereby preventing retiming of the NRZ data with respect to the PALE clock during the data transfer mode.

Encoder switch 126 is controlled by computer control system 92 and gates video data from either the input video or transfer path. This switch also toggles between video and reference 6SC and 1/2SC timing signals since the reference timing signal is used during data transfer mode and the video timing signal is used during record mode. The encoder switch also controls the TV image so that it is visible that the still location or address for the still is unoccupied and therefore available for recording and for providing signals to perform diagnostic functions. It is also used to generate a signal that produces a blanking cross. With respect to the sync word inserter, encoder switch 126 combines the 8-bit digital video signal from the analog-to-digital converter and the timing signal sent to encoder 96 from the timing reference.

The 8-bit data from encoder switch 126 is then applied to encoder 96, which first generates a variation bit and then converts it into a mirror square channel code form, which is a self-clocking, DC-less, non-zero type code. Encode the data that has been PALE-processed to the mat.

While the PALE processed data is provided to the encoder, the output of the encoder is a 9-bit data stream with phase continuity for 3SCs (if integrity is included). Data clocked with continuous phases is easier to process, especially during decoding operations. DC-free codes can occur because one logical state predominates for a period of time that can have the effect of perturbing the data in the playback process.
Avoid DC components.

In controlled band information that does not carry DC, the binary waveform is subject to distortions at zero crossing locations that cannot be removed by linear response compensation circuits. Such distortion, commonly referred to as baseline wander, acts to reduce the effective signal-to-noise ratio, modify the zero crossings of the signal, and thus degrade the bit reliability of the decoded signal. The common transmission format or channel data code used in recording and reproducing systems was established on October 22, 1963.
Miller, U.S. Pat. In Miller's code, a logical 1 is represented by a signal conversion at a particular location, ie, the mid cell, and a logical 0 is represented by a signal conversion at a particular early location, ie near the leading edge of the bit cell. The mirror format provides a damping effect on any transformations occurring at the beginning of a one-bit interval following an interval containing a transformation at the center. Asymmetries in the waveforms produced by these rules can introduce DC into the encoded signal, and the codes used in this device, commonly referred to as mirror "squared" codes, are similar to the original mirror format.
It effectively removes the DC component and does this without the need for any large memory capacity or speed changes in encoding/decoding.

Encoder circuit 96 also generates a unique Sync word in the form of a 7-digit binary number, 6SC.
Sync on alternate lines at precise locations determined by the and 1/2SC clock signals.
Insert word. In recording operation mode,
The clock signal generated from the sync component of the input video signal by reference logic circuit 125A is provided to encoder circuit 96 by encoder switch 126 at a location approximately corresponding to where the horizontal Sync pulse of the video signal was previously located. inserted
Causes Sync. In other operating modes,
The 6SC and 1/2SC clock signals are supplied to the reference logic circuit 12.
5B and reference clock generator 98 from the synchronous component of the station's reference color black video signal. The encoder is
HSync related Sync words are gated to the data stream on alternate television lines at appropriate times with respect to the regenerated subcarrier phase.

Data track information recorded on the data tracks of disk drive 73 is also encoded by encoder 96 prior to re-recording. This data track information is provided by computer control system 92 via its data track interface 120.

In FIG. 9B, the encoded digital data stream produced at the output of encoder 96 is applied to an electronic data interface 89, which is simply a splitting and buffering circuit, which interface is connected to disk pack 75. The encoded data is coupled to three disk drives 73 for permanent recording. Each disk drive receives encoded digital data from an electronic data interface 89 and includes a recording amplifier circuit 153 and a head switch circuit 97 for recording it on the associated disk pack 75.
At the same time, it receives reproduced or detected data from the reproduction amplifier circuit 155 and the head switch circuit 97, and sends it to the data selection switch 128.
send to Furthermore, disk drive interface 1
1 receives multiple servo reference signals through an electronic data interface and sends them to the timing generator (39th servo reference signal) of the disk drive control circuit.
Figure). This signal is selected by computer control system 92 from either reference logic circuit 125A or 125B. The timing generator coordinates the operation of the disk drive system using multiple servo reference signals so that the recording and playback operations and rotational position of the disk pack 75 within the disk drive 73 are synchronized to the appropriate signal system timing reference. time.

The disk drive control circuit returns pre-record timing signals and data timing signals to the electronic function data interface 89 of the signal system via the disk drive data interface 151. In the particular embodiment of the device described herein, four fields
Only two of the color code sequences of the NTSC color television signal are recorded, each of the two fields being recorded during a separate revolution of disk pack 75. Immediately prior to the recording of the two fields of video signal, a pre-recorder timing signal is generated and coupled electronically to data interface 89. This interface sends a pre-record timing signal to encoder 96 to cause generation in the apparatus described herein for an interval corresponding to two fields of data corresponding to a color black defined digitally by a logical zero. Two field intervals of color black data are returned via the interface for recording into the data bag at the selected track location for recording the video data and its associated data track information. The recording of the two fields of color black data occurs during the two revolutions of the disk back 75 immediately before the two revolutions in which the two fields of video data are recorded. This conditions the track location for subsequent dual recording of video and data track data. Double recording of the previously recorded digital data with new digital data is performed to erase the previously recorded digital data and leave a recorded signal that provides a sufficient S/N ratio to be simultaneously reproduced. Therefore, the pre-record operation cycle can be eliminated from the recording of two fields of video data and associated data track data, which takes place in only two revolutions of the device and disk pack 75.

The data timing signal is returned to the electronic data interface to time the generation and recording of data track information during the second or last of the two fields of video data. The signal is a pulse that starts after the vertical Sync that occurs between two fields of video data and ends at the end of the second field.
It is during this interval that data track information is recorded on the disk tracks of disk pack 75. Electronic data interface 8
9 couples the returned data timing signal to a data track interface 120 of computer control system 92 for identifying data track recording intervals to the system. In response, computer control system 92 performs functions related to data track information, including providing data track information associated with recorded video data on specified tracks of specified disk packs to the signaling system. do. encoder 96
receives the data track information and processes it as described in the text for sending to disk drive 73 for recording simultaneously with the last field of video data.

The recording and reproducing amplifier circuits 153, 155 and the head switch circuit 97 of the device described in the main text,
The disk drive unit control circuit includes a regenerative amplifier circuit 155.
and switch circuit 97 are configured to be activated to reproduce data from the associated disk pack 75 at all times except when a recording operation is in progress. Therefore, except during recording operations, the reproduced data is always transferred to the disk drive interface 15.
1, and this interface also constantly transfers the reproduced data to the data selection switch 12.
Give to 8. To record data, a recording command given by the disk drive control circuit is coupled to the recording/reproduction amplifier circuits 153 and 155 to activate the recording amplifier circuit 153 and disable the reproduction amplifier circuit 155. The disk drive control circuit also provides a 30 Hz head switch signal to the head switch circuit 97 during a recording operation, causing the head switch circuit to direct the data stream to a certain set of heads during the first of two consecutive fields of data to be recorded. and also to a second set of heads during a second field. The 30 Hz head switch signal is continuously available and is similarly used during playback operations to control the head switch circuit 97 to direct the playback amplifier circuit 155 to two sets of signals for playback of both fields of the desired video data signal. Switch between heads.

Returning to FIG. 9A, during a regeneration operation, reference input circuit 97B, in conjunction with reference logic circuit 125B, produces a regenerated subcarrier frequency for application to reference clock generator 98, which in turn produces a regenerated subcarrier frequency for application to reference clock generator 98. It has outputs of 6SC, 1/2SC, and H/2 and other timing signals to provide base timing for. Clock and timing signals, including the reference H/2 signal, are synchronized with the reference color subcarrier to facilitate processing of the reproduced video signal. The reference H/2 signal is determined with respect to the particular phase of the reference color subcarrier in the first line of alternating fields of the reference color black video signal. The output of the reference clock generator inserts blanking, performs selective bit muting, and generates signals when the disk drives and associated heads coupled to the playback channel are moved between track locations. A data detector, time base collector 100, data transfer circuit 12, in addition to a blanking insertion dot mutating circuit 127 that provides the selected image frame video signal for output by the system.
9. To use the redefined reference H/2 signal provided to the saturation separator and processor 101 in the data decoder and time base collector 100, the synchronization word included in the alternating playback of the two video signals is the static reference HSync. incorrectly located with respect to. This is a source of jitter in the displayed video image if not corrected. The above-mentioned synchronization error occurs when the blanking insertion bit muting circuit 127 at the front stage of the digital-to-analog exchange appropriately inserts a correction delay into the signal line when reproducing two field video signals alternately. It will be corrected accordingly. Reference clock generator 98 determines the color frame rate, H drive and field index signals provided by reference logic circuit 125B, and the reference color subcarrier signal. Determine which playback of a sequence of two field video signals requires a delay. In response to this confirmation, the reference clock generator generates a frame delay switch signal which is applied to the blanking insertion bit mutating circuit 127 to control correction delay insertion. The 8 bit digital information is then provided to a digital to analog converter and Sync and burst insertion circuits 102,130. Additionally, during the transfer and diagnostic mode of operation, reference clock generator 98 provides a base timing clock to encoder 96 via encoder switch 126 as shown.

During a playback operation, a 10-bit parallel data stream comprising 8-bit video data, a variation bit, and data from a data track being played from the disk pack is generated as shown in FIGS. 24-28.
amplified, equalized and detected by the circuitry shown and described with respect to FIGS. 53 and 54, and then the disk drive data interface circuit 15.
1 to a data selection switch 128 which can switch the outputs of the three disk drives to one or more of three channels. in this way,
A data selection switch can switch information from disk drive No. 1 to channel A while simultaneously providing a data stream from another disk drive to another channel. Information from two drives cannot be applied to one channel at the same time, but vice versa. The data selection switch 128 is comprised of a known switching circuit that will not be described in detail in this text.

Each of the detected 9-bit streams of video data and integrity data from data selection switch 128 is then provided to nine separate data decoders and timebase collectors 100, which decode the data and then individually The nine data streams are time-base corrected with respect to a common H/2 reference that is defined with respect to the phase of the regenerated reference subcarrier to eliminate timing errors that may be present in the nine lines of data, i.e., each nine
Align all Sync words so that the parallel bytes of bits consist of the correct 9 bits of data. The other bitstream from the data track is coupled only to the decoder portion of the decoder/time base collector circuit 100 by the data selection switch 128, and the recovered data track information is
It is coupled to data track interface 120 for delivery to CPU 106. The time base corrector uses a continuous phase clock to perform its correction. However, this data is again retimed with respect to the PALE clock by the data transfer circuit 129, ie the phase of the signal is changed by reclocking on each horizontal line, so that the 8-bit data stream coming from the data transfer circuit is valid. This results in a PALE processed signal gain. The data transfer circuit 129 also performs validity checks on the off-disk data and individually identifies when an error occurs by substituting bytes detected as being in error with the most likely previous byte. Perform error masking for byte errors. Thus, the substituted byte is the third previous byte, which is the most recent sample assumed to have the same phase relationship to the SC.

The output of the data transfer circuit 129 is transferred to the encoder switch when the video information needs to be viewed in the opposite direction to be recorded on another disk drive (transfer). 126) is provided to the chroma separator and processing circuit 101. The chroma separation and processing circuit 101 operates in a digital state and separates chroma information from luminance using a comb filter technique and inverts the chroma information in alternate frames to form a four-field composite NTSC signal. This signal is then applied to a video playback output circuit 127, which inserts a reference black level during blanking periods, a gray level signal during intervals between playing successive stills, and outputs signals as necessary. to perform bit muting operations. This bit muting effectively mutes which bits of the 8-bit television signal by blocking the data bitstream, and by doing so, the result is exaggerated tones, ghost-like images, etc. Achieving extraordinary visual effects in television signals. The output from the blanking insertion and bit muting circuit 127 is the output from the digital-to-analog converter 1 after this point.
Given to 02. Digital to analog converter includes blanking insertion and bit output circuit 1
27, converts the data to its analog form, and inserts the Sync and burst components of the signal to produce a total composite analog television signal.

While the foregoing generally describes the general operation of the signaling system, FIGS. 9A and 9
A more detailed description of each block included in Figure B is as follows:
Each circuit is described in terms of its own separate functional block diagram or specific electrical diagram. Also, when functional block diagrams are used to describe the operation of the separate blocks of FIGS. 9A and 9B, electrical operational diagrams corresponding to the more detailed block diagrams are also included.

8 video data bitstreams (columns),
It consists of one parity bit stream (if parity bits are added), one data track bit stream, and one transmission line bus
54 to the disk drive 75 (Figure 7B).
The channel encoded data of the 10 data bit streams transmitted by the playback channel 91 selected by the data selection switch 128
(FIG. 4). At the input of each playback channel, each of the ten transmitted data bitstreams is processed by a separate data decoder and time base correction circuit included in circuit 100 that demodulates (decodes) the channel encoded data into a digital code in NRZ-L form. received by the device. According to the present invention, this data decoder and time base corrector are configured to remove inter-channel bit time deviation errors present in the received data stream.
Correct the time axis of the NRZ-L data. Bit time deviation errors result from the data transmission channel acting on the transmitted data, inducing intersymbol interference and reflections caused by impedance discontinuities in the transmission channel. This disturbs the timing of data transmitted on that channel. In the data transmission channel of a video recorder, bit time deviation errors are typically caused by changes in the recording medium dimensions caused by changes in the environment, the heads being moved relative to each other, and the relative head-to-media recording and playback speeds. This occurs as a result of machine-to-machine mechanism changes as a result of geometric differences between the head and the recording medium. Video disk recorders using rigid recording media, such as the disk pack 73 used in the device described herein, are typically used in transmission equipment, especially common in the analog type video disk recorders widely used today. The data rate does not result in large time deviation errors. The rigid recording medium used in such recorders is dimensionally stable and the servomechanism used controls the relative movement of the head and the rigid recording medium within sufficient margins so that time deviation errors are kept small. can be maintained. In some applications of video disc recorders, the time offset error is small enough to be inconsequential and no time base correction is required.

However, as noted here,
The example device in which the time base correction circuit is used employs a highly reliable (less deformable) disk drive specifically designed and manufactured for computer data processing. Unfortunately, computer disk drives are not sufficiently developed to avoid inducing intolerable bit-time deviation errors in the data bitstream for such disk drives to be used in embodiment devices for processing video data. Does not maintain stable relative head-to-disk speed. This means that the disk pack spindle in the drive is not servo-operated, but is instead driven by an ordinary three-phase AC motor referenced to a relatively unstable line voltage, and the rotational position of the disk pack is This is because it is not controllable with respect to external standards. The resulting position errors and bit time deviation errors are particularly detrimental at the high data bit rates, 10.7 MHz, required to adequately process broadcast quality video data without degrading the video information. Therefore, in order to take advantage of the mechanical reliability of currently used computer disk drive designs, the embodiment device includes a data bitstream induced To eliminate unacceptable time deviation errors, a position servo for the AC motor and a time base correction circuit according to the invention are provided.

As mentioned above, before the received data bitstream is time-corrected, each channel encoded data bitstream is decoded back to the original NRZ-L digital signal. For this reason,
In the 9th A and 9B, the data decoder and time base correction circuit 100 selects the data selection switch 128 (7A and 7B) for each data bit line.
B) has a channel decoder circuit portion 525 having a pair of input terminals 526 coupled to B). This pair of input terminals receives channel encoded data in the form of channel encoded transition related pulses. A pair of input terminals 526 eliminates common mode noise in a pair of complementary transition-related pulses received from a transmission line pair included in transmission line bus 154 after passing through data selection switch 128 (FIG. 7B). A differential amplifier line receiver circuit 527 is coupled to the differential amplifier line receiver circuit 527. Furthermore,
The differential amplifier line receiver circuit 527 regenerates a single transition-related pulse from each transmitted pair of complementary transition-related pulses such that the regenerated pulse initially encodes the video NRZ-L data. have a well-defined leading edge that is correctly positioned in accordance with the code regulations of the channel code selected for the purpose. In particular, the differential amplifier line receiver circuit 527 provides a single regenerating transition pulse with leading and trailing edges occurring when the leading and trailing edges of the received complementary pulses are at the same level. By checking the edges of the complementary pulses transmitted in this manner, the leading edges of all regenerated pulses are properly positioned according to the channel encoding rules. This is because the positive and negative leading edges of each pair of complementary pulses are used to define the occurrence of the leading edge of each reproduced transition-related pulse. Decoder circuit 525 for transition-related pulses
Since the channels sent to act identically on the same pulse edge, any time distortion induced in that pulse edge will not affect the re-occurrence of the transition-related pulse.

Following regeneration of transition-related pulses, these pulses are routed over line 528 to clock one-shot multivibrator 529 on each occurrence of a regeneration pulse using the defined leading edge to cause clocking. It is coupled to a lever multivibrator. The one-shot multivibrator 529 is rapidly switched from its stable state to its quasi-stable state, giving a precisely defined leading edge of the transition-related pulse. One output of one-shot multivibrator 529 is connected to line 530a which extends to the clock input of ÷2 flip-flop 531. On the occurrence of each regeneration transition-related pulse, flip-flop 531 is rapidly switched between its two stable states by the leading edge of the regeneration pulse, thereby transmitting the pulsed channel encoded data, as described below. Convert to level format. This is useful for later decoding to return the data to the original NRZ-L digital format.

One shot multivibrator 529 provides complementary outputs of channel encoded data on lines 530a and 530b. Its complementary output is
Output line 5 used by data decoder circuit 525 to demodulate or decode received data.
It is coupled to a 6SC clock generator 532 which generates 33,534 complementary 6SC clock signals. The clock generator is controlled by a phase detector 535 to
It has a 6SC voltage controlled oscillator 537 locked to the phase of the data clock carried by the channel encoded data. Lines 530a and 530b
The complementary transition-related pulse outputs output by the one shot multivibrator 529 above are coupled to the input of a phase detector 535 whose output on line 536 is coupled to the control input of a 6SC voltage controlled oscillator 537. Phase detector 535 connects oscillator 53 with respect to received and regenerated transition related data pulses.
7 and provides an error correction signal to the oscillator via a phase error smoothing capacitor 538. A change in the phase of the received data causes phase detector 535 to change the average voltage level on capacitor 538 by a corresponding amount, thereby causing the phase of the 6SC clock provided by voltage controlled oscillator 537 to be conveyed in the channel encoded data. Adjustable against the clock.

This phase detection operation is performed using a pair of matched current sources 54.
0.541 and each current source has an output line 542 and 543 respectively connected to line 536 which is coupled to an error averaging capacitor 538. If no metastasis-related data pulse exists,
Line 530b extending from one-shot multivibrator 529 goes high, energizing or enabling current source 541. Since the base electrode of each differential transistor pair forming current switch 545 is grounded at the output of current source 541, the current provided by current source 541 flows through two current paths defined by current switch 545. divided equally into A current in a path defined by a current switch 545 connected to output line 543 flows through line 536 and outputs an error smoothing capacitor 538 to a predetermined level, i.e. when no data stream is input to decoder circuit 525, the voltage controlled oscillator Charge the 537 to a level that causes it to generate a 6SC clock of nominal frequency and phase. Therefore, the decoder circuit 525
The 6SC clock is generated at its nominal frequency even when no data bitstream is present at the input of the 6SC clock. This allows oscillator 537 to rapidly synchronize to the data clock when the data bitstream is first received, allowing proper demodulation of the channel encoded data.

When transition-related data pulses are received on input line 526, the one-shot multivibrator responsively provides a high level signal on line 530a and a low level signal on line 530b at intervals determined by time constant circuit 529a. occurs, and this interval is approximately 17 nanoseconds for the decoder circuit described here. A low level signal on line 530b deactivates or disables current source 541, thereby terminating the supply of charging current to error smoothing capacitor 538 through current switch 545. However, the high level signal on line 530a enables the other current source 540. This current source provides a charging current to the error smoothing capacitor 538 according to the relative conduction periods of one 544a and the other 544b of current switches 544 formed by transistors as a differential transistor pair. Two parts of the current switch 544a and 5
The transistors forming line 533
have respective base electrodes coupled to receive a 6SC clock provided through the 6SC clock. When that clock is low, transistor 544a is disabled. However, the other transistor 544b has a long time constant RC circuit 547.
6SC keeps its base electrode voltage at an average voltage level that is more positive than the low level of the clock, so
It is made conductive. Eventually, the total current provided by current source 540 is
42, one enabled transistor 5
44b.

When the 6SC clock goes high, the base of transistor 544a becomes more positive than the base of transistor 544b. Therefore, transistor 54
4a is enabled and transistor 544b is disabled. This removes the current to error smoothing capacitor 538. If current source 5
If the transition related data pulses received by 40 are timed and positioned relative to the 6SC clock provided to current switch 544 such that a low to high level transition of the 6SC clock occurs at the center of the pulse. , current switch transistors 544a and 544b are enabled at equal intervals to maintain the voltage on error smoothing capacitor 538 at an average level corresponding to the correct phase of the 6SC clock. Any change in the data bit rate of the received channel encoded data bit stream changes the position of the transition-related pulse at the input to current source 540 and the low level versus high level of the 6SC clock at the input to current switch 544. Change for level transition. When this occurs, one transistor of current switch 544 is enabled for a period during which current source 540 is enabled (by the transition-related pulse) at a longer interval than the other transistor, in which case one transistor transistors are enabled at longer intervals depending on whether the data bit rate increases or decreases. This causes a corresponding change in the current applied to error smoothing capacitor 538, and a corresponding correct change in the average voltage level across that capacitor. The change in voltage level on the capacitor imparts the phase and frequency of voltage controlled oscillator 537 to current source 540.
until the transition-related pulses are centered with respect to the low versus high level changes in the 6SC clock.
be forced to change. The two portions 544a and 544b of the current switch individually pass current from the current source 540 at equal intervals, with the low to high level variation of the 6SC clock adjusted to be centered with respect to the duration of the transition-related pulse. urge Therefore, the average voltage on capacitor 538 is maintained at the level required to lock the frequency and phase of 6SC oscillator 537 to the data clock rate of the received channel encoded data.

If the 6SC voltage controlled oscillator 537 fails to lock on the received data or the data is not received by one of the decoders and time base correctors 100 included in one of the 10 bit lines of the playback channel, the frequency An out-of-lock signal is generated on output line 550 which extends to reference clock generation circuit 98. All lines 550 from the playback channel's ten decoders and timebase correctors couple frequency unlock commands to the computer control system 92 when one or more frequency unlock signals are generated in the playback channel. Therefore, the reference clock generation circuit 98 performs an OR combination. In response to the frequency unlock command, computer control system 92 provides a video erase command to the blanking insertion and bit erasure circuitry which prevents the transmission of data to the requesting station. In this channel decoder 525, a frequency unlock signal is generated by detecting the failure of the channel decoder to provide data bits for 16 cycles of 6SC. The frequency out-of-lock signal is applied to line 5 each time channel decoder 525 fails to detect a data bit at intervals of four cycles of 3SC and eight cycles of 6SC.
48 with a clock input provided to receive clock pulses applied to
2) generated by circuit 546; If a second clock pulse occurs on line 548 before divide-by-2 circuit 546 is reset by NAND gate 549, divide-by-2 circuit 546 generates a frequency unlock signal on line 550.
NAND gate 549 generates a signal every time there is a match between the low level of the 6SC clock provided by oscillator 537 and the low level on line 530b that occurs when transition-related pulses are received at input 526 of the channel decoder. Reset the 2-split circuit.

After the two-way flip-flop 531 converts the channel-encoded data from the transition-related pulse form to the channel-encoded NRZ-L form, the data is transferred to a pair of latches 55 at the input of the decoder circuit 525.
1 and 552 (FIG. 9B) by line 531a. The decoder circuit is capable of decoding or demodulating channel encoded data. FIG. 9 E1 shows data encoded into a mirror code by the encoder 96,
FIG. 9E2 shows data encoded in the Miller square code. The latches are clocked by 3SC clocks φ1 and φ2 derived from the 6SC clock generated by oscillator 537, respectively.

The 6SC clock on line 534 is coupled to one input of each NAND gate 553a and 553b. The other input of each NAND gate receives from a 6SC clock on line 534 a complementary 3SC square wave generated by a divide-by-two flip-flop 534a. NAND gate is latch 552
is enabled when the input is low to provide a positive φ1 (FIG. 19E) clock pulse to clock the latch 551 and a positive φ2 (FIG. 9E 3) clock pulse to clock the latch 551. . φ1 and φ2 clock pulses are 3SC
is displaced in time by half a cycle. Therefore, the channel encoding on line 531a
The time at which the data level of NRZ-L is latched by the latch 551 is 3SC from the time at which the level is latched by the latch 552.
(Fig. 9E, 5)
and 6). Both latches are exclusive OR gates 554a
is connected to the two inputs of the This exclusive OR
The gate is connected to the displaced φ1 and φ2 clocks (9th
During the time clocked by EFigure 7),
It operates to detect the occurrence of a change in the level of channel encoded NRZ-L data at the inputs of latches 551 and 552. To determine whether the change in state at the input of the latch represents a logic one bit, the output of exclusive OR gate 554a is
Connected to one input of NAND gate 555. The other input of this NAND gate receives the inverted .phi.1 3SC clock pulse coupled from NAND gate 553a by inverter 555a. If the state change at the input of these latches represents a logic 1 bit, then the exclusive
The output of the OR gate 554a is the inverted φ1 3SC
The generation of clock pulses is at a low level.
NAND gate 555 is enabled, driving its output high. To ensure safe latching of the detected logic 1-bit pulse at the output of NAND gate 555, delay circuit 556
The output of the NAND gate is connected to the input of a NAND gate 555 which receives the inverted φ1 clock so that it is held high for a longer interval than the φ1 3SC clock pulse (FIG. 9E). This allows the next latch 557 to be clocked at the positive trailing edge of the 3SC clock of φ1, and the NAND gate 555
Delayed high level (9th E) given by
Figure 9) is latched. If the input data is channel encoded according to the coding rules of US Pat. No. 3,108,261, the output of latch 557 will be channel decoded NRZ-L data. This is represented by the dotted line in the timing diagram shown in Figure 9E. However, Figures 9A and 9B
In the decoder shown in the figure, an additional latch 558 is required to enable demodulation of the data channel encoded according to the Miller square code rule. However, for mirror codes, the additional latch 558 is
It only delays the output of demodulated data by one cycle of 3SC.

When data is encoded with the Miller-square encoding rule such that a particular logic 1 bit related transition is suppressed, if the logic 1 bit related transition is suppressed, then an interval greater than 1 1/2 cycles of 3SC There will be no data transfer during this period. This is because the clock input of this counter is detected by modulo 4 counter 559. It receives the φ0 clock pulse provided by NAND gate 553b, and the reset input is connected to edge detection exclusive OR gate 554.
connected to the output of a. exclusive OR gate 554
a generates a reset pulse to clear counter 559 each time a transition occurs in the channel encoded data (FIGS. 9E and 10). The output of modulo 4 counter 559 is AND gate 560
The other input receives the φ0 clock pulse. Corresponding to the absence of data transfer during 2 1/2 cycles of 3SC, the modulo 4 counter is reset to φ1 without resetting.
After counting four 3SC clock pulses,
Both inputs of AND gate 560 go low in 1/2 cycle of 3SC (Fig. 9E, 11, 12 and 1).
3). Typically, this indicates that a logical 1 bit has a suppressed bit in the channel encoded data. To ensure that no errors have been introduced into the data stream, the next NAND gate 561 examines the output of latch 558 when AND gate 560 generates a low signal representing an inhibited logic one bit. If the test output of latch 558 is low, indicating that a logic 1 bit has been inhibited, latch 558
A pulse is output on line 562 by NAND gate 561, which is wired ORed with the output of 57 (FIG. 9E, 14). FIG. 9E represents the state of NAND gate 561 as if it were not wired-ORed with the output of latch 557. A second pulse 563 (FIG. 9E) provided by NAND gate 561 occurs at the 3SC clock of φ1 and is thereby latched into latch 568. This is Latsuch 5
This prevents the output of line 58 from returning to a low level, thereby forcing the inhibited logic 1 bit to
66 (FIG. 15). At the data track bit line, demodulated data is coupled to computer control system 92 by line 566. The demodulated data clock or synchronization word from the first shift register and synchronization word detection circuit 572 provided by flip-flop 534a on lines 574 and 1D is coupled to computer control system 92.

If the phase of the 3SC demodulation clock provided by flip-flop 534a is incorrect, one shot multivibrator 534b is enabled by matching the 6SC clock on line 534 with the pulse on line 564. . This pulse occurs before line ID is first detected by the sync word detection portion of circuit 572. If the level of the demodulated data is then low and therefore inaccurate, the pulse on line 564 is 3 of 3SC
Occurs in cycles. Counter 590 (8th A
and 9C) receive the 3SC demodulation data clock and provide the advanced end of the H/2 rate count pulse (advanced EOC pulse) on line 591. Because of the well-known data bit pattern of the sync word interval, where the interval typically occurs at the leading edge of the count pulse, the demodulated data level is checked in the shift register portion of circuit 572 to determine if demodulation is occurring correctly. can be done. Gating circuit 592 enables one-shot multivibrator 534b to generate a deactivation signal at the clock input of flip-flop 534a for one cycle of 6SC when the demodulated data level tested is low. 56
Pulse at 4. This results in a phase shift of the φ1 and φ2 clocks by 1/2 cycle of 3SC, setting the correct phase for correct demodulation of the channel encoded NRZ-L data.

During playback operation, the channel encoding NRZ- applied to the output line 566 of the decoder circuit 525
Each bitstream of L data contains a time base error in the form of a bit time offset error, as described above. Furthermore, a bitline-to-bitline or skew time deviation error exists in a nine data bitstream consisting of eight parallel bits of digitized video and one parity bit if included. In order to remove these time deviation errors from the NRZ-L data, a time axis corrector 565 is provided for each data bitstream.
Such errors are corrected by electronically adjusting the variable delay means through which the NRZ-L data passes.
Each time base corrector processes the received data such that the data bit rate in all video data and parity bit lines is frequency and phase coherent with respect to the reference 3SC provided by the reference clock generator 98 for the playback channel 91. Contains circuitry to do this. Furthermore, each time axis corrector 565
aligns the data bits in the data bit lines with respect to a common redefined H/2 reference provided by reference clock generator 98 of the reproduction channel. The result of these combined functions is that relative time offset errors between data bits in nine bit lines are eliminated, line-to-line or skew errors are eliminated, and bit time offset errors within a bit line are corrected. . However, as mentioned earlier, the redefined H/2 signal is synchronized with the specific phase of the SC, thus facilitating the processing of the reproduced video data, but the reference H/2 signal
Regarding synchronization, there is no change. Therefore, when this H/2 signal is used in the time base corrector 565, the synchronization word in the video data output by the time base corrector may be incorrectly positioned in order to alternately reproduce image frames of the video data. Resulting in.

The operation of the time base corrector 565 included in each data bit line is described below with respect to the block diagram shown in FIG. 8A and the timing diagram of FIGS. 8B and 8C. The circuitry used to implement the timebase corrector operation is shown in Figures 9B, 9C and 9D. Decoder 525 to line 56
The demodulated data on each data bit line received via The data bit lines are time-corrected independently of other data bit lines by using a periodically occurring time reference. In a video recording and playback device as described above, the horizontal line-related H/2 signal derived from periodically occurring synchronization words inserted synchronously into each data bit stream in the horizontal blanking interval is processed at a higher rate. (H/2
455x) signal color subcarrier components and 3SC
It is defined in relation to the frequency and phase of the data clock (1365 times H/2) and can be used for periodically occurring timing references.

To provide time base correction of the regenerated channel demodulated data, the data on each data bit line is retimed to a common reference 3SC clock by passing it through a phaser 567. All phasers in all data bit lines are clocked by a common stable reference 3SC clock generated by reference clock generator 98 (FIG. 7A), thereby aligning the data to the stable clock signal. In the illustrated embodiment, multi-port shift register 568 is connected to channel decoder 5.
25 on line 574
Retiming is accomplished by writing data to an address determined by write address generator 569, which is clocked by the 3SC data clock. The data is read from register 568 under the control of read address generator 570 which is clocked by the reference 3SC clock provided on line 571. Phaser read address generator 5 for all 9 data bit lines
70 is clocked by the same reference 3SC clock, the data on every data bit line is 10.7M according to the NTSC television signal standard.
Retimed to the desired stable 3SC reference clock in Hz.

Write and read address generators 569 and 5
70 are respectively preset and reset to their starting addresses by the synchronization word contained in the data being corrected. The write start address precedes the read start address by 4 addresses.
Each time a sync word is detected in the received demodulated data by the first register and sync word detection circuit 572, a reset signal is generated and provided to reset the read address generator 570.
The demodulated data on line 566 enters a 7-bit shift register contained in circuit 572 and
The occurrence of a 7-bit sync word pattern is tested by logic circuitry forming the sync word detection portion of 72.
After passing through the shift register, the data is clocked into multi-port shift register 568. Register 568 has an 8-bit capacity and is first activated to read its address in four 3SC cycles following a write of data. Since the write address generator 569 is clocked by the 3SC data clock and the read address generator 570 is clocked by the reference 3SC clock, the data bit excursion error in the received data is proportional to the time the address is read. to change the time an address is written to an address. This time change between writing data at an address and reading data from that address results in the received data being retimed to a stable 3SC reference. In addition, the phase shifter 5
67, even if the synchronization word is the first synchronization word detection circuit 57
2, the received data is appropriately retimed with respect to the stable 3SC reference, unless a large time deviation error exceeds the storage capacity of register 568. Even if a large time deviation error occurs, the video data output from phaser 567 will not be correctly positioned phasewise.
Appropriate standard 3SC speed.

The synchronization word detection circuit 572 connects the first input gate circuit 592 each time a synchronization word is detected in the demodulated data.
(Figure 9B). The 7-bit shift register is clocked with the demodulated data clock on line 574 and accepts demodulated data received on line 566 for testing by the logic circuitry. Syncword detector 572 is enabled for syncword detection by syncword enable pulse generator 600. This generator is on line 574
clocked by 3SC data clock
It is enabled by a 1/1364 division counter 590. Generator 600 generates a synchronization word detection enable pulse (FIG. 8B, 3) on line 601, which
Started by a preceding EOC pulse (FIG. 8B 2) issued by counter 590 on line 591 three counts prior to the scheduled sync word generation in first sync word detection circuit 572 (FIG. 8B 16). be done. This advanced EOC pulse is also on line 591
In response to this pulse, gate circuit 592 tests the output of the shift register to determine the data logic level and therefore the phase of the demodulated data clock. Upon detection of a sync word by second sync word detector 575 (FIG. 8B), a reset signal is provided to generator 600 via line 608. This reset signal is
Termination occurs when an enable pulse is received on line 601 before counter 590 reaches 15 counts.
Counter position 15 of counter 590 terminates the enable pulse if the sync word is not detected by second sync word detector 575 (FIG. 8B). Shift register 604 provides an automatic EOC reset pulse to counter 590 via line 610 on the occurrence of the third 6SC clock pulse following the advanced EOC reset pulse (FIGS. 2 and 5 of FIG. 8C). The shift register 604 and pulse generator 605 enable the synchronization word enable pulse to follow the time change of successive synchronization word occurrences by an amount of ±1 cycle of 3SC. The three outputs are tested simultaneously and a gating waveform (Figure 8B, Figure 4) is generated. This gating waveform prevents the sync word enable pulse from resetting the counter when it occurs within one clock time of the occurrence of the automatic EOC reset pulse generated by shift register 604. If the reset enable pulse derived from the sync word reaches one count before the automatic EOC reset pulse, counter 590 is not reset (FIGS. 4 and 8). If the reset enable pulse is applied one count after the occurrence of the EOC reset pulse, the count 590 will not be reset again (coincident with the second positive pulse of the gating waveform applied by pulse generator 605). If a sync word is not detected between the sync word enable pulses, counter 590 registers shift register 604.
and through line 610 (FIG. 8B), thereby causing generator 600 to
Information about when to generate a synchronization word enable pulse is held in memory until a synchronization word is detected. Unless the detected sync word matches the positive gating waveform provided by generator 605 (FIG. 8B), NAND gate 612 outputs counter 59.
A sync word is enabled on line 613 to reset to zero.

Vertical blanking signal on line 606 (eighth
FIG. 1) enables the synchronization word enable pulse generator 600 for an interval of 10 horizontal lines by disabling gate 611;
Additionally, coupling the count 15 position of counter 590 to generator 600 is prevented. As a result, the decoder and time base correction circuit are connected to the synchronization detector 57.
2 and 575, thereby enabling operation in synchronous word time;
Phaser 568 and error gate 582 are set for proper operation.

Data is transferred from the multi-port shift register 568 to the second synchronization word detection circuit 575 using the 3SC reference clock.
(FIG. 9B) is read out to the shift register section. The shift register section has three output lines coupled to the data inputs of serial-to-parallel converter 577. The multiplex clock provided by reference clock generator 98 on line 578 is at SC speed and latches data in blocks of three data bit cells from the shift register portion of circuit 575 to converter 577. The contents of the serial-parallel converter are transferred to the next RAM 579 every SC cycle. Three output lines 5 of converter 577
80 is extended to the input of RAM579. The final time base correction is performed in RAM 579, whose write address generator 614 is clocked at the reference SC since the data rate at the input of the RAM is SC. Read address generator 62
3. The latch and subtraction circuit 615 is clocked with reference SC to read the RAM address. The read/write mode and write enable signals from reference clock generator 98 control read/write RAM addresses such that read cycles occur during part of a subcarrier cycle and write cycles occur during another part of that cycle. and control writing.

The amount of time deviation error that needs to be corrected is determined by the error gate 58.
Determined by 2. Upon detection of a syncword by second syncword detector 575, the signal on line 608 opens an error gate, allowing the reference 3SC clock pulse provided on line 571 by reference clock generator 98 to be sent to divide-by-3 counter 583. It becomes possible. One output of counter 583 goes to read error address generator 623, which provides clock pulses at SC rate. When reference H/2 is received on line 581 from reference clock generator 98, error gate 582 is closed, terminating the supply of reference 3SC clock pulses to counter 583. Therefore, the clock pulse at SC rate is no longer supplied to the read error address generator 623, and the number supplied at this point is the time deviation between the sync word of the video signal and the reference H/2 in the total number of SC cycles. represents. Further, in response to the opening of the error gate 582, the delay pulse is delayed and the pulse generator 62
Generated by 1. This delayed pulse is supplied to the read error address generator 623, which latches it. Subsequently, a reset pulse is generated from the latch pulse, and the 1/3 binary counter 58
3 and resets the error address generator 623. That counter or standard H/2 and divided into three
The second synchronization word detector 57 is measured in 3SC cycles.
The read address is set according to the timing difference with the synchronization word detected by 5. This timing difference measurement is provided to a latch and reducer 624 which reduces the write address to generate the correct read address. Since the clock representing the error is divided into three, RAM 579 adjusts for the integer error in the subcarrier cycle. The 3-bit shift register 617, error latch 618, and gate 619 correct for the 3SC one cycle portion of the error remaining after the data passes through the RAM 579. Parallel to serial converter 62 at the output of RAM
0 receives the demultiplexed clock from reference clock generator 98 and shifts the data rate to shift register 617.
Convert back to 3SC at input. FIG. 8C shows the correction performed by phaser 567 and the subsequent time axis correction by RAM 579 and shift register 617. The corrected output of time base corrector 565 appears at terminal 622. However, if the reference H/2 signal, redefined with respect to a particular phase of the subcarrier, is used to measure the time deviation error by operation of the error gate 582, the video signal provided by the time base corrector 565 46 nanoseconds of 15Hz jitter occurs. The 9-bit parallel output of time base corrector 565 is connected to data transfer circuit 129.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing the general appearance of an apparatus embodying the invention, including an internal access station and two disk drive units, and FIG. FIG. 3 is an enlarged perspective view of a portion of the keyboard of the internal access station of FIG. 1, particularly showing the various keys and bars used by the operator during operation; FIG.
The figure is a simplified functional block diagram of the overall configuration of the embodiment device, FIG. 5 is a functional block diagram showing a simplified signal path passing through the embodiment device during recording operation, and FIG. 6 is a functional block diagram of the embodiment during playback operation. FIGS. 7A and 7B are functional block diagrams showing simplified signal paths through the device; FIGS. 7A and 7B are more detailed block diagrams of the signal system of the example device; and FIG. 7C is a functional block diagram showing various positions of the signal system of the example device. FIG. 8A is a functional block diagram of a data decoder and time base correction circuit that is part of the signal system shown in FIG. 7A and incorporates the present invention. 8B and 8C are timing diagrams for the data decoder and time base correction circuit shown in FIG. 8A, and FIGS. 9A, 9B, 9C, and 9D are shown in FIG. 8A. Detailed electrical circuit diagram of the data decoder and time base correction circuit shown in Figure 9E is shown in Figure 9A.
FIG. 9B is a timing diagram showing the operation of the data decoder portion shown in FIGS. In the figure, 565 is a digital time axis corrector, 568
is a register, 572 is a first synchronization word detector, 575
579 is a RAM, 582 is an error gate, 583 is a 3-division counter, 623 is a read error address generator, and 624 is a latch and a subtracter.

Claims (1)

Claims: 1. Digital data occurring at intervals and at a rate determined by a data clock signal comprises a selected sequence of digital data bits occurring periodically in the stream in phase therewith. In an electronic time base corrector for correcting a timing error in the digital data stream, the electronic time base corrector comprises:
(b) a second clock signal generator for generating a second clock signal at the reference speed; (c) the first clock signal at the reference speed; a first detector for receiving said digital data stream and generating a first indicating signal upon detecting an occurrence of said selected sequence of digital data bits in response to a signal; (d) said first detecting signal; temporarily storing the digital data at a time after receiving the digital data by the device, and in response to one of the first and second clock signals, at a rate determined by the one clock signal. accepting digital data for storage and retrieving the stored digital data in response to the other of the first and second clock signals at a rate determined by the other clock signal; (e) a first digital data memory for initially setting the relative time for accepting and retrieving digital data in response to an instruction signal; (e) a digital data memory retrieved from the first digital data memory in response to the second clock signal; (f) a second detector receiving the data stream and generating a second indication signal responsive to and representative of the time difference between the occurrence of the selected sequence of digital data bits and the reference time signal; temporarily storing the digital data retrieved from the first digital memory at a time after receiving the digital data by the second detector; and and a second digital data memory for storing the digital signal for a time interval corresponding to a time difference.