JPH043978A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the breakdown strength of a polysilicon film and to improve the reliability of an element by forming the polysilicon film of a polyside lower layer by heat treating amorphous silicon. CONSTITUTION:Polysilicon solid grown on a polysilicon in the underlying polycide is used. That is, it is performed by including a step of forming an amorphous silicon film 4 on a semiconductor substrate 1, a step of solid growing the film 4 by heat treating and converting it to a polycrystalline silicon film 5, a step of laminating a metal silicide film 6 on the film 5, and a step of patterning the films 6, 5 and forming a gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a manufacturing process of a semiconductor device. Regarding the growth method of gate materials.

The purpose of this study is to obtain a method in which the gate oxide film breakdown voltage does not deteriorate even when the gate polycide electrode is made thinner.

A step of forming an amorphous silicon film on a semiconductor substrate, and a step of converting the amorphous silicon film into a polycrystalline silicon film by solid phase growth through heat treatment.

The method is configured to include a step of stacking a metal silicide film on the polycrystalline silicon film, and a step of patterning the metal silicide film and the polycrystalline silicon film to form a gate electrode.

[Industrial application field]

The present invention relates to a manufacturing process of a semiconductor device. Relating to a method for growing gate materials.

As recent LSI semiconductor devices become more highly integrated, gate materials are required to be made thinner.

For this reason, it is necessary to develop a method that does not deteriorate the withstand voltage of the 9-gate oxide film, although attempts are being made to thin the polycide made of polycrystalline silicon (poly-Si) and metal silicide used as the gate material.

[Conventional technology]

In a conventional method of manufacturing an LSI semiconductor device.

The lower polySi film of polycide as a gate electrode has
Silane (
A film formed by thermal decomposition of SiHi) was used.

[Problem to be solved by the invention]

However, when this poly-Si film is made thinner to 600 Å or less, a problem arises in that the withstand voltage of the gate oxide film deteriorates.

The present invention is provided for the purpose of obtaining a material or a method in which the gate oxide film breakdown voltage does not deteriorate even when the gate polycide electrode is made thin.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention, and FIG. 2 is a diagram showing the relationship between the polycide gate electrode lower layer poly-Si film thickness and the breakdown voltage non-defective product rate.

In the figure, 1 is a semiconductor substrate, 2 is a field oxide film,
3 is a gate oxide film, 4 is an amorphous silicon film, 5 is a polycrystalline silicon film, and 6 is a metal silicide film.

The present invention uses poly-Si grown in solid phase as the lower poly-Si layer of the gate polyside.

That is, the third object of the present invention is to provide a process for forming an amorphous silicon film 4 on a semiconductor substrate 1, as shown in FIG. 1(a).

As shown in FIG. 1(b), the amorphous silicon film 4 is grown in a solid phase by heat treatment to convert it into a polycrystalline silicon film 5.

As shown in FIG. 1(C), a step of laminating a metal silicide film 6 on the polycrystalline silicon film 5.

As shown in FIG. 1(d), this is achieved by including the step of patterning the metal silicide film 6 and the polycrystalline silicon film 5 to form a gate electrode.

[Function] In the present invention, Fig. 2 shows the percentage of non-defective products when non-defective products have a breakdown voltage of +8 MV/cm or more with respect to the thickness of the lower poly-Si film of the polycide gate electrode. As conventional poly-Si films are formed by CVD using vapor phase growth at a relatively high temperature, the yield rate decreases for film thicknesses of 500 Å or less, whereas solid phase growth of amorphous St from a relatively low temperature Since the poly-Si film has a high density and forms a dense crystal lattice,
Even if the film is made as thin as 0 people, it has a withstand voltage of 8 MV/cs+ or more, and has the advantage that no deterioration of the withstand voltage occurs.

〔Example〕

FIG. 3 is a schematic cross-sectional view of an embodiment of the present invention in the order of steps.

In the figure, 8 is the field 5iOz film, 9 is the gate 5
iOz film, 10 is amorphous Si film, 11 is poly-Si
film.

12 is a WSiz film, 13 is a polycide gate electrode, 14
15 is the source/drain diffusion layer, 15 is the cover oxide film, and 16 is the source/drain diffusion layer.
Hahe! It is an electrode.

As shown in FIG. 3(a), a silicon nitride (SiJ4) film (not shown) is placed on a p-type Si substrate 7 as a mask.
Field 5iO by selective isolation oxidation (LOGO5) method
z film 8 is formed to a thickness of 6,000 nm, followed by gate 5.
An iOz film 9 is formed to a thickness of 200 mm by oxidation with hydrochloric acid.

As shown in FIG. 3(b), by low pressure CVD method.

・μm at 550″C by low-temperature pyrolysis of silane gas
An amorphous Si film 10 is grown to a thickness of .

As shown in FIG. 3(c), heat treatment is performed at 600° C. for 180 minutes in a nitrogen (N2) gas atmosphere to convert the amorphous Si film 10 into a poly-Si film 11.

As shown in FIG. 3(d), a tungsten silicide (WSiz) film 12 is laminated to a thickness of 2,000 wafers on the poly-Si film 11 by the CVD method.

As shown in FIG. 3(e), WSi2
The film 12 and poly-Si film 11 are patterned to form a polycide gate electrode 13.

As shown in Figure 3(f), polycytoge 1/electrode 1
3 as a mask, arsenic ions (
As'') at an accelerating voltage of 50 KeV and a dose of 4
The source/drain diffusion layer 14 is formed by implantation under the condition of xlO''/am''.

Thereafter, as shown in FIG. 3(g), a cover oxide film 15, etc. is coated by a normal step 2, and the film for the source and drain is covered. Electrodes 16 and the like are formed to complete the device.

C. Effects of the Invention] As explained above, according to the present invention, the polySi film underlying the polycide layer is formed by heat treatment of amorphous silicon, so that the withstand voltage of the polySi film is increased.

It also greatly contributes to improving the reliability of the device.

FIG. 3 is a schematic cross-sectional view of an embodiment of the present invention in the order of steps.

In fig.

1 is a semiconductor substrate, 2 is a field oxide film.

3 is a gate oxide film, 4 is an amorphous silicon film, and 5 is a polycrystalline silicon film.

6 is a metal silicide film.

7 is a Si substrate, 8 is a field SiO□ film.

9 is a gate 5in2 film, and 10 is an amorphous Si film.

11 is a poly-Si film, 12 is a -5i2 film 13 is a polycide gate electrode.

14 is a source/drain diffusion layer.

15 is a cover oxide film, 16 is an l electrode

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a diagram showing the relationship between the polycide gate electrode lower layer poly-Si film thickness and the breakdown voltage good product rate. Invitation (Fig. 250 500 '750 +000 Polycide'γ-to Kusunoki (L-layer polysilicon) Kishirihaya C-ba) 2nd
Figure 3 Schematic cross-sectional drawing of Sadaaki Kazuo's ax f'1

Claims (1)

[Claims] A step of forming an amorphous silicon film (4) on a semiconductor substrate (1), and growing a polycrystalline silicon film (5) by growing the amorphous silicon film (4) in a solid phase by heat treatment. ), a step of stacking a metal silicide film (6) on the polycrystalline silicon film (5), and a step of patterning the metal silicide film and the polycrystalline silicon film (4) to form a gate electrode. A method for manufacturing a semiconductor device, comprising the steps of: