JPH0436673A - Electronic component testing instrument - Google Patents

Abstract

PURPOSE:To make easy to simulate the execution environment of a device to be measured without applying the execution of a test to the load of a CPU by generating operating sequence by receiving the output of a second sequencer which outputs the test sequence of a mixture signal device (MSD) in parallel by plural first sequencers. CONSTITUTION:The test 1 is programmed by the CPU 100. A test series is programmed by the CPU 100, and a required microprogram is inputted to the sequencers 122, 132, 143, and 153, etc. The test is progressed by a master sequencer 122 independently from the CPU 100. Also, all subsystems 12-15, 17 and a time measuring module 16, etc., are operated synchronizing with a clock signal supplied from a master clock subsystem 11. A reference clock generator 111 inputs output synchronized with the output to clock generators 112, 113, which generates a clock mask, and both clocks can be synchronized with the master clock of the device to be measured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to the testing of electronic devices, and in particular to an electronic component testing device suitable for testing mixed signal devices that use many types of signals in various relationships. It is related to electronic component testing methods.

[Prior art and its problems]

Recent advances in electronic components can be seen in the diversity of their functions and improvements in performance while suppressing the increase in physical size. A typical example is a large scale integrated circuit (LSI).

An explanation will be given below using an example of a test using an LSI as a device under test (DIIT). Of course, the tests described are also applicable to testing smaller integrated circuits (ICs) and individual components (transistors, FETs, resistors, capacitors, inductors, etc.).

A feature of recent LSIs is that they incorporate what used to be the peripheral circuits of the LSI, expanding their functions, and achieving faster speeds as the manufacturing process is improved. As a result, the human output signal of the LSI includes all direct current signals (DC), digital signals, and analog signals.

The time relationship between these input and output signals includes both synchronous and asynchronous signals, and the signal modulation rate is 100 MH2 or more. In this specification, these input/output signals are collectively referred to as mixed signals. Conventional LSI
Testing equipment was often realized by expanding previous IC testing equipment, and even those that were not were often based on the concept of IC testing equipment. Therefore, LSI
The basic idea was to divide the inside of the system into functional blocks and conduct tests for each functional block.

For example, functional blocks that handle digital signals are tested in the same way as digital IC testers, and functional blocks that handle analog signals are tested in the same way as analog IC testers. An LSI that passes the tests of all functional blocks is determined to be a good product. Such a divide-and-conquer type test can be said to be an efficient system when the above-mentioned parts are highly independent, but when the independence between each functional block is low, as in recent LSIs, the LSI
This is not a test that guarantees operation in the actual usage environment.

For example, in the case of a high-speed analog-to-digital converter, simply evaluating the input/output conversion characteristics using direct current does not equate to evaluation in an actual usage environment. In a real environment, problems include the relationship between input signal frequency and conversion error, the relationship between input waveform and conversion error, and the relationship between input waveform and conversion clock and conversion error.

Furthermore, in the communication interface IC, data is input/output to a synchronous digital circuit while input/output is performed asynchronously, and analog signals may be received for input/output.

Digital filters also have analog input/output and internal digital circuits, and an analog-to-digital converter (ADC) and digital
Connected via an analog converter (DAC). Transfer function errors, noise, and spurious characteristics that depend on the relationship between the input signal and internal clock must be evaluated.

Furthermore, in testing an LSI that has an external feedback circuit, it is necessary to calculate and supply a control input immediately after measuring and evaluating a certain output signal. For example, there are many errors in ADCs.

Furthermore, when the results of calculations made by combining the outputs of the respective pins of the LSI are used for evaluation, there is a problem in that the calculation speed is slow. For example, in a configuration in which a signal generation and signal measurement module or a signal generation and signal measurement shared module (hereinafter simply referred to as GM module) connected to each pin and a signal processing module are connected via memory, data to the memory is The acquisition of data, storage of calculation results, and communication between mountains and signal processing modules must be done through the intervention of a higher-level processing device or sequential communication from the signal processing device, which is slow, and the programs for these procedures are complicated. was to be determined.

[Purpose of the invention]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an electronic component testing apparatus that performs a test that simulates the actual usage environment of an electronic component under test that inputs and outputs mixed signals.

[Summary of the invention]

According to one embodiment of the present invention, a test series (test tse
In order to execute the GM module, the sequencer controlling the GM module is structured in a hierarchical manner, and a long test series is executed without the intervention of a central processing unit.

The hierarchical configuration reduces wiring to the GM module controlled by the lowest sequencer. That is, by providing some sequencers with memories and providing predetermined sequences therein, the amount of information to be transmitted through wiring can be reduced.

Furthermore, in one embodiment of the present invention, the above sequencer and GM
All modules are configured to be synchronized by the same clock source, and desired input/output signals of OUT can be synchronized.

In addition, by using multiple clock sources, the above sequencer and GM
When the modules are associated in time, the local coincidence of their waveforms is used to change the sequence within one effective minimum clock, so there is no latency or disruption of the sequence. Furthermore, it is also possible to perform pseudo asynchronous control by selecting the mutual frequencies of a plurality of clock sources in a rational ratio. In this case, the state control of the sequencer can also be executed within the next one clock period by detecting a matching point of clock edges.

By using a signal processing device (referred to as a DSP) together with the OM module controlled by the sequencer, the signal from the module is preprocessed by the DSP and fed back to the upper sequencer or central processing unit. Furthermore, since the DSPs have dedicated buses and can be programmed to communicate with each other, it is also possible to mutually process the DSP outputs at high speed. Since the communication of these DSPs and the calculation processing accompanying the communication are performed in synchronization with the same clock source as those for the sequencer and 0M module, their outputs and operations are also predictable and reproducibility is guaranteed. Therefore, D
Stable and accurate simulation of the actual OT environment is possible.

In particular, it is characterized in that real-time testing of OUT can be performed easily.

[Embodiments of the invention]

FIG. 1 is a block diagram of an electronic component testing device (referred to as a tester) 1 according to an embodiment of the present invention, and FIG. 2 is a functional block diagram of a generalized model 2 of the component under test (DUT) 186 in FIG. 1. be.

The generalized model (referred to as GM) 2 is a general-purpose model of a mixed signal electronic component (referred to as DOT), and a model lacking some of its functional blocks is also eligible as a DUT in the present invention. The functional blocks of GM2 include a timing generator 21 that performs clock signal input/output and internal timing control, and a digital pattern interface (
(referred to as D-IF) 22, standardization of analog signal reception;
An analog circuit 26 and an analog-to-digital converter (referred to as 800) 24 perform digitization, respectively, and a digital-to-analog converter (referred to as 800) performs analogization of digital signals and standardization transmission of analog signals to output analog signals. (referred to as DAC) 25, analog circuit 2
7 and a digital signal processing device (referred to as DSP) that is connected to the D-I P 22, ADC 24, and DAC 25 and performs input/output and processing of digital signals.

FIG. 1 shows the configuration of a tester 1. Each part indicated by a rectangle is realized by hardware, but it is also possible to realize it by software.

However, it is difficult to say that this is preferable because the speed is generally slow.

The tester 1 is programmed by a central processing unit (referred to as CP port) 100. A test series (referred to as test sequence TS) is programmed by the CPU 100, and the necessary microprograms are sent to the sequencer 122.
132.143.153, etc., the test is performed by a mask sequencer (referred to as MSS) 122.
It is run independently of the central processing unit. Further, each subsystem 12, 13, 14, 15, 17, time measurement module 16, etc. all operate in synchronization with a clock signal supplied from a master clock (referred to as MCLK) subsystem (MCLK-SS) 11.

The configuration and operation of the tester 1 will be explained below.

Tester 1 is MCLK-SSII, subsystem group (digital mask subsystem 12: DM-5S12
, Digital Slave Subsystem 13: DS
-SS13, waveform generator subsystem 14: KG
-SS14, waveform digitizer subsystem 15:
WD-SS15, time measurement module 16: T
MM16, DC subsystem 17: DC-SS17
) and pin electronics and DOT
186 and a test head 18 that interfaces with a group of subsystems.

MCLK-SSII inputs the DUT's mask clock from the timing generator 21 of the DUT 186 or the DSP 23 via the buffer 181, and generates a first master clock MCLK1 and a second mask clock MCLK2 synchronized with the input. . The reference clock generator 111 that receives the output of the buffer 181 inputs outputs synchronized with the output to the first and second clock generators 112 and 113 to generate first and second mask clocks. MCLK
1, MCLK 2 can both be synchronized to the DOT master clock. Of course, it is easy to configure the reference clock to be generated even when there is no CUT mask clock, when the OUT mask clock is not used, or when the reference clock generator is synchronized with another signal.

With MCLK 1? ICLK 2 have different frequencies, but these frequencies are preferably chosen in a rational ratio.

Timing handler 114 includes MCLK 1 and MCIJ
A signal for controlling the mask sequencer (mask sequencer 122 in FIG. 1) of the tester 1 is generated.

For example, a mask sequencer sequence or test sequence is initiated.

The uncertainty of the match is Ins in one embodiment.

DUT 186 typically includes a DM-5S12 as a subsystem that provides signals to digital patterns and digital signal locks to define test sequences.

[1? f-5S12 is a digital timing generator CD
121 (referred to as ETG) 121, a mask sequencer 122 which outputs the test sequence timed and programmed by the ETG 12, mask sequencer 1
A vector memory 124a controlled by 22, an engineering generator (referred to as EG) 124b, a formatter (
It has a prior art DM-SS bar bin resource (referred to as PPP) 124 that generates a digital signal for each bin of a DUT 186 consisting of a DUT 186 (referred to as FMT) 124c, the output of which is outputted via a bin driver 182a to a 0UT 186.
is input.

Additionally, in one embodiment of the present invention, data processing resources 123
have. Data processing resource (referred to as DPR) engineering 2
3 consists of a DSP 123b and a data memory 123a that stores data operated by the [1SP 123b.

DPR 124 can change the output of DPR 12 by performing arithmetic processing on the test vector in vector memory 124a. Additionally, the DSP 123b can input and output data by communicating with other subsystems (for example, the DSP 133b of the DS-SS13.
3 is controlled by mask sequencer 122.

DS-5S13 has the same configuration as DM-SS12,
The slave sequencer 132 is the mask sequencer 12
The only difference is in place of 2. DGTG131, slave sequencer 132, DPR133, PPR1
34, data memory 133a, DSP133b,
Vector memory 134a, EG134b, FMT
134c and the bin driver 183a are each DGT
G121, master sequencer 122, DPR1
23. Correspondingly, perform similar operations.

The υG-8S14 basically generates arbitrary waveforms using a well-known method, but it has a DSP 144b inside and can perform calculations on stored waveforms and output them.

The WG-SS 14 includes an AWG sequencer 143 that is timed by a timing generator WGTG 141, and a waveform generator 144 that generates a waveform according to a sequence stored in and output from the AWG sequencer 143. These constitute a bar channel resource (PCR) 142 that is normally prepared for the desired channels of the tester 1.

The waveform generation unit 144 performs waveform generation using the conventional technology, which is composed of a waveform memory 144a and a DAC 144C that converts the digital output of the waveform into an analog waveform, and performs calculations on the waveform stored in the waveform memory 144a using a DSP 144b to generate a DAC.
The waveform generation method according to the present invention can be implemented using 1440 inputs.

- The output of G-SS14 is routed through output amplifier 184 to r13.
given to the UT186 bin.

-WD-SS15, which operates in the opposite manner to G-5S14, is
A signal is input from the signal output bin of the UT 186 via the input amplifier 185, digitized by the AD (J54c), and then subjected to calculations by the DSP 154b as required and stored in the waveform memo 54a. These constitute a PC!?152 prepared for the desired channels.The timing of the digitizer/sequencer 153 is controlled by a timing generator W.
Performed by DTG151.

Timing of each output of CUT 186 is performed by conventional timing module 16. Timing control is performed by mask sequencer 122.

DC-SS17 is controlled by a timing generator DCTG171 which is controlled by mask sequencer 122.

The DC characteristics of the OUT 186 are measured by the DC units 182b and 183b for each of the 186 digital input/output bins and the analog SMU 172. Conventionally, DC measurements were performed asynchronously by the central processing unit CPUOO, but in one embodiment of the present invention they are performed synchronously by the mask sequencer 122. Therefore, input and output are analog signals, internal operations include digital signal processing, and all LIT186 tests are performed in synchronization with digital signals, increasing test stability and test reliability. .

Each timing generator DGTG121, DETG131
, IIGTG141, WDTG151, DCtG17
The clock supplied to MCLK1 is set to either MCLK1 or MCLK2 by the central processing unit CPUOO. Even if the master clocks differ between the subsystems, the control signal of the mask sequencer 122 clocked by the matching signal of the timing handler 114
All subsystems can be controlled completely at the same time. Further, if MCLK 1 and MCLK 2 have different frequencies, asynchronous operation can be simulated in a pseudo manner.

The mask sequencer 1220 control signal is introduced to each subsystem's timing orderer 131.141.151.171 and each subsystem's slave sequencer 132.143.153 via control line 122a, as shown in FIG. , Sequence Block (referred to as SBK) based commands to these subsystems are supported.

An example of SBK is shown below.

Generation of a series of digital patterns and digital signals to DS-SS13, generation of a series of waveforms to WG-3S14, WD-SS15
A series of waveform sampling, time measurement module 16
One time measurement is commanded to the DC-SS 17, and a series of voltage and current settings and measurements are commanded to the DC-SS17. In accordance with the instructions, the subsystem generates timing within the SBK and orders sequences in accordance with the internal microprogram in synchronization with the mask clock used.

On the other hand, when the sub-sequence ends, the result of each flsP, D
The evaluation result of the output waveform of the UT 186 is immediately fed back to the mask sequencer 122 via the signal line 122b.

Response to commands from CPU 100, evaluation of returned signals, change of test sequence (program branching)
is determined to end within one cycle of the mask clock.
The change function is also applied to actual execution by hardware and sequence changes based on DSP calculation results. That is, mask sequencer 122 and slave sequencer 132.1.
43.153 can also be interpreted as executing a pre-stored sequence by the CPU 100 and performing a master-slave operation.

Furthermore, since all changes in the execution of sequences within the sequencer are completed within one clock period, there is an advantage that no dead time occurs.

Figure 3 shows the waveform generator subsystem WG-SS14 and D
This is an example showing the relationship between the waveforms of M-SS12 or DS-SS13.

Programs 31.32 are mask sequences and slave
This is a software display showing each of the sequences, and an example of an actual waveform is shown in an actual waveform group 33.

33a indicates a vector address of the DM-SS 12 or DS-SS 13, and 33b is a waveform obtained by clocking, formatting, and outputting the vector at the vector address.

The sequence given from the mask sequencer 122
When block SBK is waveform 1 and waveform 2, the AWG sequencer generates a combination of waveform pieces ■, ■, ■, ■, ■ in order to synthesize waveform 2 defined by SBK. 33c is the output of WG-SS14, 33d and 33
e shows the corresponding waveform pieces and waveforms used. A waveform without dead time is generated in synchronization with the digital vector.

Next, the DSPs 123, 133, 144b, and 154b will be explained. The functions within these DSP subsystems have already been described.

These local DSPs can communicate with each other via a shared data path 19 independently of the CPU 100 and synchronously with the clock. It also transmits and receives data from the CPU 100. The control command is transferred in advance from the CPU 100, and the operation is started by a synchronization command of the CPUloo or a synchronization signal of the sequencer of each subsystem. The DSP executes data input, operation, and output according to control instructions. Connection of the DSP to data path 19 is also made by control commands or directly from CPU 100.

For example, by connecting the DSP 154b and DSP 144b to the data path 19 and communicating with each other, the WD-8S15
The measurement results can be immediately fed back to the ws-ss 14 to change the waveform.

Furthermore, by having each DSP perform parallel processing, the processing speed decreases approximately in proportion to the number of parallel processing.

For example, there is an example in which the average of the output signals of each DUT bin is determined. Communication using data path 19 can also be configured as a serial communication device.

Further, it is possible to speed up the Fourier transform by sampling the waveform at N points. Multiple channels of WD-3SI5 can be connected in parallel to reduce the sampling rate of each channel while increasing the final conversion rate.

When N=LxM, Discrete Fourier Transform (DFT) of L points
When calculating M pieces in parallel, (multiplying number of L point DFT) x
M+ (M-1) x (N/2) multiplications are required.

Also, the number of multiplications for L-point DFT is L2 when FFT is not used.
．． When FFT is performed with L being a power of 2 (L/'2
) I o gx(L).

Therefore, as in the embodiment of the present invention, M=2 or M=4
If you choose , the multiplication numbers are (N/2)log, (
N) , (N/2) 1 o gz(N) + (N
/2), and when performing distributed processing with two or four DSPs, the number of multiplications per device is reduced, and even if the data transfer time between DSPs is exceeded, it is possible to significantly shorten the time.

Note that the slave sequencer in the subsystem is configured to use a decoder and index register synchronized with the clock to designate the start address of the microprogram so as to activate the SBK in synchronization with the clock. Therefore, multiple branches can be performed within one clock cycle according to commands from the mask sequencer, and dead time is not introduced into the waveform due to branching. In one embodiment of the present invention, the tester l is MCLK! , 2 as 64 m
Hz-128mHz is used.

〔Effect of the invention〕

Implementation of the present invention produces the following effects.

1) The central processing unit only decodes and directs the execution of the test program and does not affect the progress of the test execution procedure. Therefore, test execution is not affected by the load on the central processing unit, and it is easy to simulate the execution environment of the DUT.

2) DC characteristic measurements, which were conventionally controlled by a central processing unit and operated asynchronously, are now performed by a mask sequencer in synchronization with other DUT signals, improving measurement stability and
Clarity and repeatability are improved.

3) Functional blocks of mixed signal equipment can be evaluated in parallel in an environment closer to the usage environment regardless of their type (analog, digital, synchronous, asynchronous), improving evaluation accuracy and reliability and reducing test time. is also shortened.

4) All subsystems are clocked by a synchronized mask clock, and each subsystem has a “next operation”
and "where to operate" are written in advance, and test programs can be created using a high-level language.

5) With synchronized decoders and index registers, multiple branches and activations of the sequencer occur within one clock cycle, so there is no dead time in subsystem operation.

6) Since a multiple sequencer configuration is adopted, wiring is reduced in terms of hardware configuration.

7) Although it has a multiple sequencer configuration, all of them are synchronized, so parallel and independent operations of subsystems can be performed while maintaining good stability and repeatability.

8) By synchronizing each subsystem using multiple clocks synchronized with the DUT clock, it is possible to generate synchronous signals and simulate asynchronous operation by using the frequency difference between multiple clocks. and mixed synchronous and asynchronous D
The UT exam can be done in an integrated manner.

9) Local DSP for each subsystem or channel
It parallelizes signal processing and speeds up the overall test.

10) Local DSPs can communicate with each other and perform calculation processing and control of multiple DUT pin signals independently of the central processing unit, allowing complex input/output environments to be accurately clocked. be able to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an electronic component testing apparatus according to an embodiment of the present invention. FIG. 2 is a functional block diagram of a generalized model of electronic components. FIG. 3 is a diagram for explaining an example of waveform generation according to the present invention. 100: Central processing unit ll: Mask clock subsystem (MCLK-
8S) 111: Reference clock generator 114 timing handler 12: Digital mask subsystem (DM-3S
) 122: Mask sequencer (MSS) 13: Digital slave subsystem (DS-3S) Two-waveform generator subsystem (WG-8S) Two-waveform digitizer subsystem (WD-8S) Two-time measurement module (TMM) ): DC subsystem (DS-8S) 18: Test head 186: Electronic device under test: Device under test

Claims (1)

[Claims] 1. To test mixed signal devices (referred to as MSD),
A subsystem consisting of a functional module that generates an input signal to the MSD and/or measures the output of the MSD, and a first sequencer that controls the operational sequence of the functional module.
An electronic component testing device comprising a plurality of systems, wherein the plurality of first sequencers receive in parallel the outputs of second sequencers that output test sequences of the MSD to generate the operation sequences.