JPH04340724A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To obtain a transistor which has large mobility and is excellent in electric characteristics by using a superior polycrystalline silicon thin film having no defects at a process temperature capable or using a grass substrate, by a method wherein, after a silicon layer stuck and formed on an insulative substrate is irradiated with an energetic beam, said layer is patterned. CONSTITUTION:After a silicon layer 103 is stuck and formed on an insulative substrate 101, the silicon layer 103 is irradiated with an energetic beam 104, and heat treatment is performed, the silicon layer 103 is patterned. An insulative thin film is stuck and formed so as to cover the silicon layer 103. A gate electrode is stuck and formed on the insulative thin film. After impurities are implanted in the silicon thin film 103 through the insulative thin film, a laser beam is applied, thereby activating the impurities. For example, a silicon dioxide film 102 is formed on a glass substrate 101, and the silicon layer 103 is formed on the film 102 by a low pressure CVD method. Next excimer laser is projected and heat treatment is performed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing thin film transistors used in active matrix liquid crystal displays, image sensors, liquid crystal shutter arrays, three-dimensional integrated devices, and the like.

0002

2. Description of the Related Art Conventionally, semiconductor thin films on insulating substrates have been applied to picture elements of active matrix liquid crystal displays, and are known to have the following advantages.

(2) A transistor with uniform characteristics can be formed on a transparent substrate that transmits visible light, which is difficult to achieve with a silicon substrate. (2) Stray capacitance can be reduced by reducing the PN junction area.

[0004] In addition, by applying bulk semiconductor technology, a thin film transistor is formed on a quartz substrate, and a picture element transistor is formed on the same substrate, and a C-MOS circuit using a thin film transistor for driving the picture element is formed on the same substrate. There are also examples where it is configured. However, this C-MOS circuit has 100
Because the gate insulating film is formed at a temperature of 0°C or higher and the impurities are activated after ion implantation, the strain point is 800°C.
There was a drawback that the following inexpensive large-area glass substrates could not be used.

[0005] Furthermore, since single-crystal insulating substrates such as sapphire are expensive for driving, as an alternative, fused quartz plates and amorphous Si substrates formed by oxidizing Si substrates at temperatures of 1000°C or higher are being used. A method has been proposed in which a SiO2 film, an amorphous SiO2 film or an amorphous SiN film deposited on a Si substrate is used, and a semiconductor thin body is formed thereon. However, since these SiO2 films and SiN films are not single crystal, if a silicon layer is deposited thereon and crystallized in a process at a temperature of 1000° C. or higher, polycrystals will grow on the substrate. The grain size of this polycrystal is several tens of nanometers, and even if a MOS transistor is formed on top of it, its carrier mobility will be a fraction of that of a MOS transistor on bulk silicon.
That's about it.

[0006] Furthermore, for MOS transistors on inexpensive glass substrates with strain points of 850°C or lower for active matrix substrates of liquid crystal displays, it is not possible to use processes at temperatures of 1000°C or higher, so low-pressure chemical vapor phase processing is required. Even if a silicon layer is deposited using a growth method, the grain size of the polycrystal is only a few nanometers at most, so even if a MOS transistor is formed on it,
Its carrier mobility is about a few tenths of that of a MOS transistor on bulk silicon.

[0007]Recently, therefore, a method of increasing the crystal grain size and forming a single crystal by scanning a silicon thin film with a laser beam, an electron beam, or the like and melting and resolidifying the thin film has been studied. According to this method, it is possible to form a high-quality silicon single crystal phase or high-quality polycrystal on an insulating substrate, and the characteristics of devices fabricated using it are also improved, and the characteristics are similar to those of devices fabricated in bulk silicon. improved to a certain degree. Furthermore, this method allows elements to be stacked, making it possible to realize a so-called three-dimensional IC. As a result, circuits with characteristics such as high density, high speed, and multifunction can be obtained.

The first conventional example of applying a laser beam to the crystallization of the silicon layer in the active region of a MOS transistor to improve the performance of a MOS transistor is published in Japanese Patent Publication No. 61-78119, ``Method of Manufacturing a Semiconductor.'' can be mentioned.

In order to obtain a self-aligned structure for the formation of tertiary element elements and thin film transistors for liquid crystal displays, impurities are implanted by ion implantation, and the source region and drain of the thin film transistor are formed by laser beam irradiation. Attempts are being made to form regions. According to this method, a self-aligned thin film transistor can be formed by a low temperature process of 600° C. or less.

As a second conventional example in which a laser beam is applied to the activation of impurities implanted into the source/drain regions of a MOS transistor, Extended Abst
racts of the 22nd (1990 In
International) Conference o
n Solid State Devices and
Materials, Sendai, 1990, pp.
．． 971-974 “Large Area Dopi
ng Process for Fabricatin
g of p-SiTFT's Using Buck
et Ion Source and XeCl Ex
"cimer laser annealing".

The first conventional example mentioned above will be explained with reference to FIG. A polycrystalline silicon layer is formed on a heat-resistant glass 601 with a lower melting point than quartz by the CVD method, and the surface portion of the polycrystalline silicon layer is crystallized by irradiation with a short wavelength laser 604 as shown in FIG. 6a, and then, As shown in FIG. 6b, silicon ions are implanted 605 to make the lower region 607 of the laser-irradiated silicon layer amorphous, and then this silicon layer is heat-treated at 600° C. for about 15 hours to solidify the amorphous portion. An attempt is being made to increase the grain size 608 of crystal grains by phase growth. It is a well-known fact that when the active region of a thin film transistor has a thickness of 100 nm or less, particularly 20 to 50 nm, good electrical characteristics with high effective mobility can be obtained. In the conventional example, in order to obtain a thin silicon layer with a thickness of several tens of nanometers, the surface of the polycrystalline silicon layer that has undergone the solid-phase growth process shown above is etched with phosphoric acid, as shown in FIG. 6e. are giving. In general, it is known that polycrystalline silicon layers subjected to solid-phase growth have large crystal grains with a grain size of several μm when observed using a TEM (electron transmission microscope).
Not only that, but an extremely large number of minute defects exist inside the crystal grains. For this reason, in order to increase the electrical properties of thin film transistors, such as effective mobility, conventional examples attempt to hydrogenate the polycrystalline silicon layer after solid phase growth. In the conventional example, this hydrogenation treatment is performed as shown in Fig. 6d or Fig. 6e.
Attempts are being made to improve the quality of the polycrystalline silicon layer by applying it at the stage where the above process has been completed.

Furthermore, in the conventional example, the polycrystalline silicon layer manufactured as described above is applied to the formation of a thin film transistor, but a self-alignment method using the gate electrode formed of the impurity-doped polycrystalline silicon layer as a mask is used. A source region and a drain region are formed to form a thin film transistor as shown in FIG. 6g.

However, the above conventional example has the following problems. That is, a polycrystalline silicon layer formed by the CVD method is irradiated with short wavelength laser light to crystallize only the surface portion, and the lower region of the silicon layer is made amorphous by implantation of silicon ions, and then solid phase is formed. Attempts are being made to obtain large-sized crystal grains through growth processing. However, the crystal grain size of the silicon layer 606 annealed by excimer laser beam annealing is 100n.
m, and in the solid phase growth process after ion implantation, each crystal of the silicon layer 606 becomes a nucleus and the amorphous layer 607 is crystallized. The grain size of the crystal is limited by the size of the silicon layer 606, and the grain size of the crystal obtained by solid phase growth is at most 1.
00 nm, and it is not possible to obtain crystals with a large grain size, which is the objective of the conventional example. Further, since crystals produced by solid phase growth have many fine defects inside, conventional methods can only obtain crystals with a grain size of 100 nm that have many crystal defects inside.

Furthermore, in order to improve the electrical characteristics of thin film transistors, the silicon layer crystallized by the above method is etched with phosphoric acid to make it thin, but the etching rate with phosphoric acid is only 0.2 to 0. Since the rate is .3 Å/min, it takes 160 minutes to 400 minutes to increase the initial film thickness from 100 nm to 20 nm to 50 nm. 17
Not only is it difficult to control changes in the state of the phosphoric acid solution at 0° C. over time, but also the so-called throughput is extremely low.

Furthermore, since the glass substrate is exposed to a phosphoric acid solution at 170° C., the constituent components of the glass, such as aluminum ions, calcium ions, and sodium ions, are dissolved in the phosphoric acid solution from the back side where the polycrystalline silicon film is not formed. However, there is a problem in that the ions adhere to the surface of the polycrystalline silicon film etched with phosphoric acid, significantly degrading the quality of the polycrystalline silicon layer. Therefore, the subthreshold characteristics of thin film transistors manufactured by applying this method are degraded.

In addition, after the solid phase growth process shown in FIG. 6d or after the thin film process of polycrystalline silicon layer using phosphoric acid shown in FIG. Hydrogenation treatment is performed to reduce the amount of hydrogen, and after this process is completed, a gate electrode is formed using impurity-doped polycrystal. Although a temperature of about 600° C. is required to form impurity-doped polycrystalline silicon, hydrogen atoms are dissociated from silicon atoms by heat treatment at a temperature of 450° C. or higher. Therefore, in the conventional method for forming thin film transistors, the hydrogen atoms in the polycrystalline silicon film escape, resulting in extremely poor electrical characteristics despite attempts to increase the grain size of the crystals through solid phase growth. There was a problem in that it resulted in a low-quality thin film transistor.

In the second conventional example, impurity ions are implanted into the silicon thin film in the source/drain regions exposed by peeling off the insulating film using a bucket ion source device, and the impurities are activated by beam annealing with an argon laser. The source/drain regions are formed in a self-aligned manner with respect to the gate electrode. In the ion implantation method, ions implanted in the depth y direction of the silicon thin film perform so-called two-dimensional channeling in a direction oblique to the y axis. Impurities are also implanted at the boundary between the source region and the channel region, and at the boundary between the drain region and the channel region, but as in the second embodiment, the impurities implanted into the silicon layer are removed by laser beam irradiation. When activated, the impurity in the boundary region described above is not activated, leaving a region 710 where the impurity is not activated and defects exist, as shown in FIG. 7b. Therefore, the thin film transistor manufactured according to the second conventional example has the problem that the leakage current between the source and drain increases when the gate voltage is off due to the defect at the boundary between the drain region and the channel region under the gate electrode. There was a point.

[0018]

SUMMARY OF THE INVENTION In view of the above points, the present invention is directed to manufacturing a thin film transistor in which a source region and a drain region are formed in a self-aligned manner with respect to a gate electrode at a process temperature that allows the use of an inexpensive glass substrate. The present invention provides a method. Further, the present invention provides a method for manufacturing a thin film transistor in which a source region and a drain region are formed uniformly over the entire surface of a substrate in a self-aligned manner. Further, the present invention provides a method for manufacturing a thin film transistor with high mobility and excellent electrical characteristics using a high-quality polycrystalline silicon thin film having no defects. Further, the present invention provides a method for manufacturing a self-aligned thin film transistor in which leakage current between the source and drain is reduced at a process temperature that allows the use of an inexpensive glass substrate.

[0019]

[Means for Solving the Problems] The present invention includes the steps of depositing and forming a silicon layer on an insulating substrate, irradiating the silicon layer with an energy beam, and performing heat treatment after irradiating the energy beam. , after the heat treatment, a step of patterning the silicon layer, a step of depositing an insulating thin film to cover the silicon layer, a step of depositing and forming a gate electrode on the insulating thin film, and a step of forming a gate electrode through the insulating thin film. The silicon thin film is characterized by comprising a step of implanting an impurity into the silicon thin film, a step of activating the impurity by irradiating it with a laser beam, and a step of performing heat treatment after the step of activating the impurity is completed. This is a method for manufacturing a thin film transistor.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be explained below with reference to illustrated embodiments. 1 and 2 explain the core part of the embodiment of the present invention, and FIGS. 3, 4, and 5 show first, second, and third thin film transistors to which the method of FIGS. 1 and 2 is applied. Examples of the manufacturing method are shown below.

FIG. 1 is a cross-sectional view showing the manufacturing process of a polycrystalline silicon layer of a thin film transistor according to the present invention. Figure 1
On an insulating substrate 101 that has been cleaned in advance as shown in a.
For example, a silicon dioxide film 102 is deposited to a thickness of 200 nm on a transparent glass substrate by atmospheric pressure chemical vapor deposition at a substrate temperature of 200 to 350°C.

Next, a silicon layer 103 having a thickness of 10 nm to 50 nm is deposited at a substrate temperature of 550 to 650° C., for example, by low pressure chemical vapor deposition. In order to control the threshold value of the thin film transistor, impurities may be introduced into the silicon layer 103 by ion implantation or the like.

Next, the silicon layer is irradiated with an energy beam as shown in FIG. 1b. An example of the energy beam is a XeCl excimer laser with a wavelength of 308 nm. The beam annealing conditions for a silicon layer formed by low pressure chemical vapor deposition are that the pulse width of the pulsed laser is 50 nsec, and the silicon layer 103 is
The energy intensity of the individual pulses of the pulsed laser just before is 200-700 mJcm-2, more preferably 300-600 mJcm-2. The number of pulses applied to the same location on the silicon layer 103 may be multiple times. During beam annealing, the partial pressure of oxygen around the silicon layer 103 is 10-5 m
mHg or less. Alternatively, during beam annealing, the periphery of the silicon layer 103 may be He, Ne, Ar.
, Kr, Xe, or a mixture thereof.

This is because, if oxygen exists on or near the surface of the silicon layer 103, when the temperature of the silicon layer 103 increases due to beam annealing, oxygen or nitrogen reacts and is incorporated into the silicon layer as an impurity, resulting in poor performance. A good silicon layer cannot be obtained. Therefore, when annealing the silicon layer, it is preferable to anneal it in a vacuum or in an inert gas atmosphere as much as possible. However, when removing the surface of the crystallized silicon layer with hydrofluoric acid or the like after laser annealing, beam annealing can be performed in an oxygen atmosphere, nitrogen atmosphere, or air.

The laser beam 104 is not limited to the XeCl excimer laser, and ArF excimer laser, KrF excimer laser, YAG laser, etc. can also be used.

By the beam annealing, the silicon layer becomes a polycrystalline silicon layer 105 having a chevron structure as shown in FIG. 1c.

Since the potential barrier at the interface between the silicon layer and silicon dioxide is about 3.1 eV, if the energy beam used for beam annealing is ultraviolet light such as an excimer laser with a wavelength of 308 nm, the electrons in the silicon layer Injected into the silicon dioxide film 102, positive charges are held at the interface of the silicon layer opposite to the silicon dioxide interface. Therefore, unless this positive charge is eliminated, the characteristics of the drain current with respect to the gate voltage of the completed thin film transistor will show a tendency to depletion. Therefore, especially when ultraviolet light is used as the energy beam, it is necessary to annihilate the holes in the silicon. A similar phenomenon occurs when ultraviolet light is irradiated on a silicon layer deposited on silicon nitride or silicon nitride oxide instead of silicon dioxide, or on a silicon layer deposited directly on a glass substrate. For this reason, it is necessary to eliminate holes generated in silicon.

Next, the stress remaining in the polycrystalline silicon layer, the polycrystalline silicon layer 105 and the silicon dioxide film 10
In order to reduce or eliminate the large number of mismatches that exist between 2 and the grain boundaries of the crystal grains that make up the polycrystalline silicon layer, and the point defects and holes that exist in the polycrystalline silicon grains. , heat treatment. The heat treatment conditions include, for example, a temperature of 300 to 650° C., a time of 10 minutes to 20 hours, and an atmosphere surrounding the sample in nitrogen gas, inert gas, or inert gas containing hydrogen. As long as there are no problems with the substrate, such as expansion/contraction or warping, it may take more than 20 hours. Or 700-800
A rapid thermal annealing method of 5 to 10 minutes at a temperature of .degree. C. has a sufficient effect, and furthermore, an inexpensive glass substrate can be used under the above conditions. Through this heat treatment, it is possible to obtain a high-quality polycrystalline silicon layer 106 that has almost no crystal defects in the polycrystalline silicon layer 105 and has excellent electrical characteristics with few crystal grain boundaries or mismatch between the silicon layer and silicon dioxide. can.

Next, after completing the process of ion-implanting impurities into the silicon layer in a self-aligned manner with respect to the gate electrode, the impurities in the silicon layer are activated by a laser beam, and the impurities channeled two-dimensionally are heat-treated. Regarding the second invention of this patent regarding the activation process, FIG.
I will explain by showing.

As shown in FIG. 2a, impurity ions are implanted into the silicon layer 203 through the insulating film 204 in a self-aligned manner with respect to the gate electrode 205. As shown in FIG. For example, silicon layer 2
The film thickness of the insulating film 204 is 50 nm, and the film thickness of the insulating film 204 is 150 nm.
The conditions for ion implantation when the impurity is phosphorus are that the ion implantation amount is 3×10 15 cm −2 and the acceleration voltage is 120 KeV.

By the above ion implantation, impurity-implanted regions 207 and 208 are formed as shown in FIG. 2b. A region 208 is a region where impurity ions are implanted under the gate electrode to form a channel in an oblique direction.

Next, in order to activate the implanted impurities, a laser beam 209 is irradiated from the side of the substrate where the gate electrode is formed, as shown in FIG. 5c. The impurities in the region 207 are activated by laser beam irradiation, and an impurity-doped polycrystalline silicon 210 is formed.
The impurities in the region 208 under the gate electrode are not irradiated with the laser beam, and the heat generated in the region 207
The impurities in region 208 are not activated or are in an insufficiently activated state because heat conduction to the region 208 is also insufficient. If there is a region 208 in which impurities are not activated, this region 208 acts as a resistance, which reduces the on-current of the thin film transistor.Furthermore, since there are many defects at the boundary between the drain region and the channel region, A problem arises in that the source/drain leakage current becomes extremely large in the voltage off region.

Next, a heat treatment step is performed to activate the impurities in the region 208. The conditions for the heat treatment step are a temperature of 300 to 650° C., a time of 10 minutes to 20 hours, and an atmosphere surrounding the sample in nitrogen gas, inert gas, or inert gas containing hydrogen. If the substrate has no problems such as expansion/contraction or warping, it may be heat-treated for more than 20 hours. Or 700-800
A rapid thermal annealing method of 5 to 10 minutes at a temperature of .degree. C. has a sufficient effect, and furthermore, an inexpensive glass substrate can be used under the above conditions. By this heat treatment, the impurities in the region 208 are activated and a high quality silicon layer with extremely few crystal defects is obtained. As a result, according to the present invention, it is possible to manufacture a thin film transistor with excellent electrical characteristics, which has a large on-current and a small source/drain leakage current in the off-region of the gate voltage.

Since the crystal in the region 210 crystallized by the laser beam serves as a growth nucleus for crystallization, in fact 30
Heat treatment at a temperature of 0 to 650° C. for a time of 10 minutes to several hours is sufficient.

Next, a method for manufacturing a thin film transistor using the above-described process will be described.

FIG. 3 shows an embodiment of the first method for manufacturing a thin film transistor. FIG. 4 shows an example of the second method for manufacturing a thin film transistor. FIG. 5 shows an example of a third method for manufacturing a thin film transistor.

FIGS. 3a to 3i are cross-sectional views showing the manufacturing process of a thin film transistor according to the present invention. As shown in FIG. 3a, a silicon dioxide film 302 is deposited on an insulating substrate 301 that has been cleaned in advance, for example, on a transparent glass substrate by atmospheric pressure chemical vapor deposition at a substrate temperature of 200 to 350°C.
The film is deposited to a thickness of nm.

Next, an n-type silicon layer having a thickness of 150 nm is deposited at a substrate temperature of 550 to 650° C., for example, by low pressure chemical vapor deposition. Examples of impurities contained in the n-type silicon layer include phosphorus, arsenic, and antimony. Next, the n-type silicon layer is patterned to form island regions 303 and 304 that will become the source and drain regions of the thin film transistor.

The source region 303 and drain region 3
The method for forming 04 is not limited to the above, but for example, an i-type silicon layer is formed on the silicon dioxide film 302 by low pressure chemical vapor deposition to a thickness of 150 nm at a substrate temperature of 450 to 650°C. Form the adhesion. As the raw material gas for forming the i-type silicon layer, SiH4 or Si
2H4 or a mixed gas of SiH4 and Si2H4 can be used. Then, for example, 1015
Impurities are introduced at a concentration of ~1016 cm-2. Next, in order to activate the impurities ion-implanted into the silicon, thermal annealing is performed for 2 hours in a nitrogen atmosphere at a substrate temperature of 600°C. The impurity implanted into the i-type silicon can also be activated by an energy beam such as a laser beam. Then, the silicon layer is patterned to form a source region 303 and a drain region 30.
form 4. When forming a p-type thin film transistor, the source region 303 and the drain region 304 can be formed by ion-implanting p-type impurities such as boron instead of n-type impurities in the ion implantation process described above. good.

Next, for example, the weight concentration of 3 diluted with pure water is
% HF solution to remove the native oxide film formed on the surfaces of the source and drain regions.

Next, the silicon layer which will become the active region of the thin film transistor is formed by, for example, low-pressure chemical vapor deposition at a substrate temperature of 600° C. to a film thickness of, for example, 15 nm to 70 nm, on which the source region 303 and drain region 304 are formed. Form an adhesion so as to cover it. SiH4 or Si2H4 is used as a raw material gas for forming the silicon layer.
Alternatively, a mixed gas of SiH4 and Si2H4 can be used.

The method for forming the silicon layer 305 is not limited to the above-described low pressure chemical vapor deposition method, but may also be an amorphous silicon layer containing hydrogen formed by the decomposition of monosilane by glow discharge, or a sputtering method. The present invention can also be applied to a silicon layer.

In order to control the threshold value of the thin film transistor manufactured in this example, after forming the silicon layer, a required amount of impurity is implanted by, for example, ion implantation.

Next, the silicon layer is attached to the source region 303.
A silicon layer 305 is formed by patterning on an island as shown in FIG. 3B so as to bridge the drain region 304. Next, as shown in FIG. 3c, the silicon layer 305 is irradiated with a laser beam 306 to crystallize it. As the laser beam 306, a XeCl excimer pulse laser with a wavelength of 308 nm is used. The beam annealing conditions for a silicon layer formed by low pressure chemical vapor deposition are as follows:
The pulse width of the pulsed laser is 50 nsec, and the energy intensity of each pulse of the pulsed laser immediately before the silicon layer 305 is 200 to 600 mJcm-2, and a more suitable intensity is 300 to 500 mJcm-2.
It is. The number of pulses applied to the same location on the silicon layer 305 may be multiple times. During beam annealing, the partial pressure of oxygen around the silicon layer 305 is less than 10-5 mmHg. Alternatively, during beam annealing, the periphery of the silicon layer 305 is
The atmosphere is an inert gas such as e, Ne, Ar, Kr, Xe, or a mixture thereof.

This is because if oxygen exists on or near the surface of the silicon layer 305, when the temperature of the silicon layer 305 rises due to beam annealing, oxygen or nitrogen reacts and is incorporated into the silicon layer 305 as an impurity. A good silicon layer cannot be obtained. Therefore,
When annealing the silicon layer, it is preferable to anneal it in a vacuum or in an inert gas atmosphere as much as possible. However, when removing the surface of the crystallized silicon layer 305 with hydrofluoric acid or the like after laser annealing, beam annealing can be performed in an oxygen atmosphere, nitrogen atmosphere, or air.

The laser beam 306 is not limited to the XeCl excimer laser, and ArF excimer laser, KrF excimer laser, YAG laser, etc. can also be used.

By the beam annealing, the silicon layer 305 becomes a polycrystalline silicon layer 306 as shown in FIG. 3d.

Next, the stress remaining in the polycrystalline silicon layer 306, the numerous mismatches existing between the polycrystalline silicon layer 306 and the silicon dioxide film 302, and the crystal grains constituting the polycrystalline silicon layer are Inconsistency existing at grain boundaries,
Heat treatment is then performed to reduce or eliminate point defects and holes present in the polycrystalline silicon particles. The conditions for the heat treatment may be the same as those shown and explained with reference to FIG. 1 of the embodiment.

Next, as shown in FIG. 3e, a gate insulating film 308 is formed by, for example, atmospheric pressure chemical vapor deposition so as to cover the source region 303, the drain region 304, and the polycrystalline silicon layer 307. Substrate temperature 300
A silicon dioxide film having a thickness of, for example, 150 nm is deposited at .degree. The method and material for forming the gate insulating film 308 are not limited to those described above. For example, SiO2 can be deposited and formed by electron cyclotron resonance CVD and used as the gate insulating film 308. Furthermore, first, SiO by electron cyclotron resonance method (ECR method)
2 is deposited to cover the source region 303, the drain region 304, and the polycrystalline silicon film 307, and SiO2 is further deposited by atmospheric pressure chemical vapor deposition. But it's okay. Also, EC
A single layer of SiO2 formed by the R method may be used as the gate insulating film 308. Next, a gate electrode 309 is formed as shown in FIG. 3f. For example, a silicon thin film doped with impurities is deposited to cover the gate insulating film 308, and then patterned. The silicon layer into which the impurity is introduced includes a silicon layer formed by low pressure chemical vapor deposition using phosphorus as an impurity, an amorphous silicon layer containing phosphorus or a microcrystalline silicon layer formed by PECVD, etc. There is. The thickness of the gate electrode is 300 to 400 nm.
It is. As shown in FIG. 3F, the gate electrode 309 and the source region 303 have a so-called offset structure in which they do not overlap in the stacking direction of the thin films. Similarly, the i-drain region 304 has an offset structure from the gate electrode.

Next, as shown in FIG. 3G, ions are implanted 330 into the offset structure portion of the polycrystalline silicon layer 307 through the gate insulating film 308 in a self-aligned manner with respect to the gate electrode 309. When the thin film transistor to be manufactured is an n-type, phosphorus or the like is used as the ion species. For example, in the case of phosphorus, when the thickness of the gate insulating film 306 is 150 nm, the conditions for ion implantation are an acceleration voltage of 120 keV and an ion implantation amount of 1×10 15 to 1×10 16 cm −3 . Further, when the thin film transistor to be manufactured is of a p-type, boron or the like is used as the ion species to be ion-implanted. For example, in the case of boron, the conditions for ion implantation are an acceleration voltage of 40 keV and an ion implantation amount of 1×1015 to 1×
It is 1016 cm-3. As shown in FIG. 3g, regions 311 and 312 are formed in which impurities are implanted in a self-aligned manner with respect to the gate electrode 309.

Next, the impurities contained in the regions 311 and 312 are activated.

[0052] 311 and 3 which are the areas of the offset
12 When the thickness of the silicon layer is about 25 nm, the ion-implanted impurities can be activated by thermal annealing, for example, under the above-mentioned ion implantation conditions in a nitrogen atmosphere.
Annealing conditions of 60 hours or more at .degree. C. or 2 hours at 700.degree. C. are required. Under these annealing conditions, even if the impurity is implanted in a self-aligned manner with respect to the gate electrode, the lateral diffusion of the impurity into the channel becomes large, and eventually the impurity spreads between the gate electrode and the source electrode, and between the gate electrode and the drain electrode. Parasitic capacitance will occur. In order to manufacture a thin film transistor on an inexpensive glass substrate with a strain point of around 600° C., the above activation conditions by thermal annealing are not appropriate.

As shown in FIG. 3h, the impurities implanted in the regions 311 and 312 are activated by a laser beam. The laser beam conditions were a XeCl excimer laser with a wavelength of 308 nm and a half width of 50 ns,
The substrate is irradiated in air with a beam energy intensity of 00 mJcm-2. The number of pulses of the laser beam irradiated to the thin film transistor may be appropriately plural. The 309 and 3 activated by the laser beam
The sheet resistance of No. 10 is 0.01 to 0.05 Ωcm −1 , which is a resistance value sufficient for use as a thin film transistor. The laser beam is not limited to the above-mentioned XeCl excimer laser, but also includes ArF excimer laser, KrF excimer laser, and YAG having a wavelength in the same region as ultraviolet rays.
Laser harmonics can be used to activate impurities. By irradiating the laser beam, the area 311
and 312 become polycrystalline silicon films 314 and 315 containing impurities.

Furthermore, by the laser beam irradiation for activating the impurity, the gate electrode formed of the silicon layer containing the impurity is also annealed at the same time, and its resistance is reduced. Since the thickness of the gate electrode formed of a silicon layer is about 300 nm, the laser beam energy does not reach the silicon layer in the active region.

Next, heat treatment is performed by the method shown in FIG. This heat treatment also activates the obliquely channeled impurities under the gate electrode, resulting in a high-quality silicon layer with extremely few crystal defects. As a result, according to the present invention, it is possible to manufacture a thin film transistor with excellent electrical characteristics, which has a large on-current and a small source/drain leakage current in the off-region of the gate voltage.

Since the source/drain regions have already been crystallized by the laser beam, they serve as crystal growth nuclei, so in fact, the time is 1 at a temperature of 300 to 650°C.
Heat treatment for 0 minutes to several hours is sufficient.

Next, the interlayer insulating film 316 is attached to the gate electrode 30.
9 is formed on the substrate. As a material for the interlayer insulating film, there is, for example, SiO2 with a film thickness of 500 nm formed by atmospheric pressure chemical vapor deposition. Furthermore, the interlayer insulating film 316 may be made of SiO2, PSG, or SiNx formed by electron cyclotron resonance, sputtering, low pressure chemical vapor deposition, or the like.

Next, as shown in FIG. 3i, the source region 3
03 and the interlayer insulating film 316 in the drain region 304.
After providing a window for a contact so as to penetrate through the gate insulating film 308, a metal thin film, such as an aluminum thin film, which will become an electrode is deposited and patterned to form a source electrode 317.
and a drain electrode 318 are formed, respectively. When a thin film transistor is used as a picture element of an active matrix type liquid crystal display, the drain electrode 318 may be made of, for example, indium-tin oxide (IT).
A transparent electrode made of O) can be used. Said I
A TO thin film is deposited by sputtering and pattern etched, and then an aluminum thin film, which is a source electrode material, is deposited by sputtering and a source electrode is formed by pattern etching.

Next, a passivation film 319 made of, for example, a nitride film with a thickness of 50 nm is formed so as to cover the substrate on which the source electrode 317 and the drain electrode 318 are formed. The passivation film is not limited to one layer, and may be a plurality of stacked layers of thin films made of different materials. For example, first, a thickness of 20 mm was formed by sputtering.
It is also possible to deposit 0 nm of SiO2 to cover the source electrode 317 and drain electrode 312, and then deposit an organic polymer film to use it as a passivation film. The passivation film 313 is used to prevent contamination of the thin film transistor from the outside world, and when the thin film transistor is used as a picture element of an active matrix liquid crystal display, it prevents the application of DC voltage generated by the thin film transistor to liquid crystal molecules. The purpose is to reduce

Further, a heat treatment is then performed in a gas containing hydrogen at, for example, 300° C. for one hour to obtain the desired thin film transistor as shown in FIG. 3i. However, if an organic polymer film that decomposes at 300° C. is used as the passivation film, it is necessary to perform the above hydrogen treatment before forming the organic polymer film.

The above embodiment is an example of manufacturing a self-aligned thin film transistor, but an n-type thin film transistor and a p-type thin film transistor are manufactured.
A C-MOS circuit can be constructed by forming thin film transistors of the same type on the same substrate and wiring and connecting the gate electrode and source electrode or drain electrode of each thin film transistor with an appropriate wiring material.

FIGS. 4a to 4i are cross-sectional views showing steps of a second method for manufacturing a thin film transistor according to the present invention. Figure 4
401 on an insulating substrate that has been cleaned in advance as shown in a.
For example, a silicon dioxide film 402 is formed on a transparent glass substrate by, for example, an atmospheric pressure chemical vapor deposition method at a substrate temperature of 200℃.
It is deposited to a thickness of, for example, 200 nm at a temperature of ~350°C.

Next, a silicon layer 203 is deposited to cover the silicon dioxide film 402 with a thickness of 15 nm to 70 nm at a substrate temperature of 450 to 650° C., for example, using a low pressure chemical vapor deposition method. As a raw material gas for forming the silicon layer 403, SiH4, Si2H4,
Alternatively, a mixed gas of SiH4 and Si2H4 can be used.

The method for forming the silicon layer 403 is not limited to the above-described low pressure chemical vapor deposition method, but may also be an amorphous silicon layer containing hydrogen formed by the decomposition of monosilane by glow discharge, or a sputtering method. The present invention can also be applied to a silicon layer.

Next, the silicon layer 403 is irradiated with a laser beam 404 to crystallize it, as shown in FIG. 4b. The laser beam 404 includes Xe-
A Cl excimer pulse laser is used. The beam annealing conditions for a silicon layer formed by low pressure chemical vapor deposition are that the pulse width of the pulsed laser is 50 nsec, and the energy intensity of each pulse of the pulsed laser immediately before the silicon layer 403 is 200 to 600 mJcm.
-2, and a more appropriate strength is 300 to 500 m.
It is Jcm-2. The number of pulses applied to the same location on the silicon layer 403 may be multiple times. For the same reason as in Example 1, the partial pressure of oxygen around the silicon layer 403 is 10-5 mmH during beam annealing.
g or less. During beam annealing, the partial pressure of oxygen on and around the surface of the silicon layer 403 is 10-5 m
mHg or less. Alternatively, during beam annealing, the periphery of the silicon layer 403 may be He, Ne, Ar.
, Kr, Xe, or a mixture thereof.

The laser beam 404 is not limited to the XeCl excimer laser, and ArF excimer laser, KrF excimer laser, YAG laser, etc. can also be used.

After beam annealing, the polycrystalline silicon layer 405 is patterned into an island shape as shown in FIG. 4c. In this embodiment, the silicon layer 403 is patterned after beam annealing, but the polycrystalline silicon layer 405 can be formed by patterning the silicon layer into an island shape in advance and then beam annealing as described above. You can also do it.

Next, by the method shown in FIG. 1, heat treatment is performed to improve the quality of the silicon layer 405.

Next, as shown in FIG. 4c, a gate insulating film 406 is formed to cover the polycrystalline silicon layer 405 by, for example, atmospheric pressure chemical vapor deposition at a substrate temperature of 30°C.
A silicon dioxide film having a thickness of, for example, 150 nm is deposited at 0°C. The method and material for forming the gate insulating film 406 are not limited to those described above. For example, SiO2 can be deposited and formed by electron cyclotron resonance CVD and used as the gate insulating film 408. The gate insulating film 40 is made of one layer of silicon dioxide film formed by ECR method.
8 may be formed.

Next, as shown in FIG. 4e, the gate electrode 40
form 7. For example, a silicon thin film doped with impurities is deposited to cover the gate insulating film 408, and then patterned. Examples of the silicon layer into which the impurity is introduced include a silicon layer formed by low pressure chemical vapor deposition using phosphorus as an impurity, and an amorphous silicon layer containing phosphorus formed by PECVD. The thickness of the gate electrode is 300 to 400 nm.

Next, as shown in FIG. 4f, the gate electrode 407
Ions are implanted 408 through the gate insulating film 406 in a self-aligned manner. When the thin film transistor to be manufactured is an n-type, phosphorus or the like is used as the ion species. for example,
In the case of phosphorus, the thickness of the gate insulating film 406 is 150 nm.
In this case, the conditions for ion implantation are an acceleration voltage of 120 keV and an ion implantation amount of 1×10 15 to 1×10 16 cm −3 . Also, if the thin film transistor to be manufactured is p-type,
Ion species to be ion-implanted include boron and the like. For example, in the case of boron, the conditions for ion implantation are an acceleration voltage of 40 keV and an ion implantation amount of 1 x 1015 to 1 x 10
It is 16 cm-3. As shown in FIG. 4f, a region 4 where impurities are implanted in a self-aligned manner with respect to the gate electrode 407.
09 and 410 are formed.

Next, the impurities contained in the regions 409 and 410 are activated.

[0073] 409 and 4 which are the areas of the offset
When the thickness of the silicon layer No. 10 is about 25 nm, in order to activate the ion-implanted impurities by thermal annealing, for example, under the above-mentioned ion implantation conditions, at 600° C. for 60 hours or more in a nitrogen atmosphere, Alternatively, annealing at 700°C for 2 hours is required. Activation by thermal annealing is not suitable for manufacturing thin film transistors on inexpensive glass substrates with a strain point of around 600°C.

As shown in FIG. 4g, the impurities implanted in regions 409 and 410 are activated by a laser beam. The laser beam conditions were a XeCl excimer laser with a wavelength of 308 nm and a half width of 50 ns,
The substrate is irradiated in air with a beam energy intensity of 00 mJcm-2. The number of pulses of the laser beam irradiated to the thin film transistor may be appropriately plural. The 409 and 4 activated by the laser beam
The sheet resistance of No. 10 is 0.01 to 0.05 Ωcm −1 , which is a resistance value sufficient for use as a thin film transistor. The laser beam is not limited to the above-mentioned XeCl excimer laser, but also includes ArF excimer laser, KrF excimer laser, and YAG having a wavelength in the same region as ultraviolet rays.
Laser harmonics can be used to activate impurities. By irradiating the laser beam, the area 409
and 410 are a source region 412 and a drain region 413 made of a polycrystalline silicon film containing impurities.

Next, in order to activate the impurity implanted into the silicon layer in the active region under the gate electrode with a diagonal channel, heat treatment is performed by the method described with reference to FIG.

Furthermore, by the laser beam irradiation for activating the impurity, the gate electrode formed of the silicon layer containing the impurity is also annealed at the same time, and its resistance is reduced. Since the thickness of the gate electrode formed of a silicon layer is about 300 nm, the laser beam energy does not reach the active silicon layer.

Next, the interlayer insulating film 414 is connected to the gate electrode 40.
7 is formed on the substrate. As a material for the interlayer insulating film, there is, for example, SiO2 with a film thickness of 500 nm formed by atmospheric pressure chemical vapor deposition. Furthermore, the interlayer insulating film 414 may be made of SiO2, PSG, or SiNx formed by electron cyclotron resonance, sputtering, low pressure chemical vapor deposition, or the like.

Next, as shown in FIG. 4h, the source region 4
12 and the drain region 413 with the interlayer insulating film 414
After providing a window for a contact so as to penetrate through the gate insulating film 405, a metal thin film, such as an aluminum thin film, which will become an electrode is deposited and patterned to form a source electrode 415.
and a drain electrode 416 are respectively formed. When a thin film transistor is used as a picture element of an active matrix liquid crystal display, the drain electrode 416 may be made of, for example, indium-tin oxide (IT).
A transparent electrode made of O) can be used. Said I
A TO thin film is deposited by sputtering and pattern etched, and then an aluminum thin film, which is a source electrode material, is deposited by sputtering and a source electrode is formed by pattern etching.

Next, a passivation film 417 of, for example, a 50 nm thick nitride film is formed to cover the substrate on which the source electrode 415 and the drain electrode 416 are formed. The passivation film is not limited to one layer, and may be a plurality of stacked layers of thin films made of different materials. For example, first, a thickness of 20 mm was formed by sputtering.
It is also possible to deposit 0 nm of SiO2 to cover the source electrode 415 and drain electrode 416, and then deposit an organic polymer film to use it as a passivation film. The passivation film 417 is used to prevent contamination of the thin film transistor from the outside world, and when this thin film transistor is used as a picture element of an active matrix type liquid crystal display, it prevents the application of DC voltage generated by the thin film transistor to liquid crystal molecules. The purpose is to reduce

[0080] Further, a heat treatment is then performed in a hydrogen-containing gas at, for example, 300° C. for one hour to obtain the desired thin film transistor as shown in FIG. 4h. However, if an organic polymer film that decomposes at 300° C. is used as the passivation film, it is necessary to perform the above hydrogen treatment before forming the organic polymer film.

The above embodiment is an example of manufacturing a self-aligned thin film transistor, but an n-type thin film transistor and a p-type thin film transistor are manufactured.
A C-MOS circuit can be constructed by forming thin film transistors of the same type on the same substrate and wiring and connecting the gate electrode and source electrode or drain electrode of each thin film transistor with an appropriate wiring material.

FIGS. 5a to 5h are cross-sectional views showing the steps of a third method for manufacturing a thin film transistor according to the present invention.

FIGS. 5a to 5d of the third embodiment of the thin film transistor manufacturing process of the present invention are the same as FIGS. 3a to 3d of the first embodiment of the thin film transistor manufacturing process of the present invention.

A third embodiment of the present invention will be explained below, starting from FIG. 5e.

A gate electrode 507 is formed as shown in FIG. 5e. For example, a metal thin film such as Cr is formed by sputtering or vapor deposition to cover the gate insulating film, and then patterned. When the tensile internal force of the metal thin film is large, for example, in the case of Cr, the thickness is 30 mm.
A thin film of 0 nm has a large tensile stress, which causes problems such as wire breakage at stepped portions. Therefore, in the case of such a gate electrode, it is necessary to appropriately reduce the thickness. For example, the thickness of a gate electrode made of Cr is preferably about 150 nm. However, in the next ion implantation process shown in FIG. 5f, the ions cannot be blocked sufficiently. For this reason, the resist 508 on the gate electrode is left behind after patterning. The remaining resist has a thickness of 500 nm or more and serves as a sufficient mask for ion implantation.

Next, as shown in FIG. 5f, the gate electrode 507
Ions are implanted 509 through the gate insulating film 506 in a self-aligned manner. When the thin film transistor to be manufactured is an n-type, phosphorus or the like is used as the ion species. for example,
In the case of phosphorus, the thickness of the gate insulating film 506 is 150 nm.
In this case, the conditions for ion implantation are an acceleration voltage of 120 keV and an ion implantation amount of 1×10 15 to 1×10 16 cm −3 . Also, if the thin film transistor to be manufactured is p-type,
Ion species to be ion-implanted include boron and the like. For example, in the case of boron, the conditions for ion implantation are an acceleration voltage of 40 keV and an ion implantation amount of 1 x 1015 to 1 x 10
It is 16 cm-3. As shown in FIG. 5f, a region 5 in which impurities are implanted in a self-aligned manner with respect to the gate electrode 507.
10 and 511 are formed.

Next, the resist 5 on the gate electrode 507 is
Peel off 08. Next, the impurities implanted into regions 510 and 511 are activated.

[0088] The offset area is 510 and 5.
When the thickness of the silicon layer No. 11 is about 25 nm, in order to activate the ion-implanted impurities by thermal annealing, for example, under the above-mentioned ion implantation conditions, at 600° C. for 60 hours or more in a nitrogen atmosphere, Alternatively, annealing at 700°C for 2 hours is required. Activation by thermal annealing is not suitable for manufacturing thin film transistors on inexpensive glass substrates with a strain point of around 600°C.

As shown in FIG. 5g, the laser beam 51
2 activates the impurities implanted into the regions 510 and 511. Beam annealing condition is wavelength 308nm
, a XeCl excimer laser with a half-value width of 50 ns,
The substrate is irradiated with a beam energy intensity of 0 to 600 mJcm-2. If the gate electrode is made of a material that reacts with gas molecules in the atmosphere when irradiated with the laser beam 512, the substrate is irradiated with the laser beam in vacuum or in an inert gas. The number of pulses of the laser beam 512 applied to the thin film transistor may be appropriately plural. The sheet resistance of the sheets 510 and 511 activated by the laser beam 512 is 0.01 to 0.05 Ωcm −1 , which is a resistance value sufficient for use as a thin film transistor. The laser beam is not limited to the above-mentioned XeCl excimer laser,
ArF excimer laser, KrF excimer laser, YAG laser having a wavelength in the same region as ultraviolet light, etc. can be used to activate impurities. By irradiating the laser beam, the regions 510 and 511 become a source region 313 and a drain region 514 made of a polycrystalline silicon film containing impurities.

Next, by the heat treatment method shown in FIG. 2, impurities channeled obliquely in the silicon layer under the gate electrode are activated, and crystal defects in the silicon layer under the gate electrode are eliminated. .

Next, the interlayer insulating film 515 is connected to the gate electrode 50.
7 is formed on the substrate. As a material for the interlayer insulating film, there is, for example, SiO2 with a film thickness of 500 nm formed by atmospheric pressure chemical vapor deposition. Furthermore, the interlayer insulating film 515 may be made of SiO2, PSG, or SiNx formed by electron cyclotron resonance, sputtering, low pressure chemical vapor deposition, or the like.

Next, as shown in FIG. 5h, the source region 5
13 and the drain region 514 with the interlayer insulating film 515
After providing a window for a contact so as to penetrate through the gate insulating film 507, a metal thin film, such as an aluminum thin film, which will become an electrode is deposited and patterned to form a source electrode 515.
and a drain electrode 516 are formed, respectively. When a thin film transistor is used as a picture element of an active matrix liquid crystal display, the drain electrode 517 may be made of, for example, indium-tin oxide (IT).
A transparent electrode made of O) can be used. Said I
A TO thin film is deposited by sputtering and pattern etched, and then an aluminum thin film, which is a source electrode material, is deposited by sputtering and a source electrode is formed by pattern etching.

Next, a passivation film 518 of, for example, a 50 nm thick nitride film is formed to cover the substrate on which the source electrode 516 and the drain electrode 517 are formed. The passivation film is not limited to one layer, and may be a plurality of stacked layers of thin films made of different materials. For example, first, a thickness of 20 mm was formed by sputtering.
It is also possible to deposit 0 nm of SiO2 to cover the source electrode 516 and drain electrode 517, and then deposit an organic polymer film to use it as a passivation film. The passivation film 518 is used to prevent contamination of the thin film transistor from the outside world, and when the thin film transistor is used as a picture element of an active matrix liquid crystal display, it prevents the application of DC voltage generated by the thin film transistor to liquid crystal molecules. The purpose is to reduce

[0094] Furthermore, heat treatment is then performed in a hydrogen-containing gas at, for example, 300°C for one hour to obtain the desired thin film transistor as shown in FIG. 5h. However, if an organic polymer film that decomposes at 300° C. is used as the passivation film, it is necessary to perform hydrogen treatment before forming the organic polymer film.

The third embodiment described above is an example of manufacturing a self-aligned thin film transistor, in which an n-type thin film transistor and a p-type thin film transistor are formed on the same substrate, and the gate electrode and source electrode or drain of each thin film transistor are A C-MOS circuit can be constructed by wiring and connecting the electrodes with a suitable wiring material.

[0096]

[Effects of the Invention] As explained above, in the method for manufacturing a thin film transistor of the present invention, defects in the silicon layer can be eliminated by performing a heat treatment process after crystallizing the silicon layer by irradiation with an energy beam. For,
Since a thin film transistor with excellent subthreshold characteristics can be manufactured, a high-speed operation C-MOS circuit can be constructed using this thin film transistor. As a result, the drive circuit of the active matrix type liquid crystal display can be formed on the same inexpensive glass substrate as the picture elements, so that a high-definition liquid crystal display can be manufactured at low cost.

[0097] Also, after activating the impurity ion-implanted into the gate electrode in a self-aligned manner through the gate insulating film with a laser beam, a heat treatment process is performed to eliminate defects caused by the ion implantation in the silicon layer. When the gate voltage is in the off range, there is no leakage current between the source and drain, which increases the retention of charge in the pixel electrodes of the liquid crystal display, making it possible to manufacture excellent liquid crystal displays with no flicker and high contrast. .

A thin film transistor that is self-aligned with respect to the gate electrode and has high dielectric strength between the source electrode and the gate electrode and between the gate electrode and the drain electrode can be formed by a process at 600° C. or lower.

Furthermore, since the activation of impurities by laser has a short lateral diffusion distance of the channel, the parasitic capacitance generated between the gate electrode and the source electrode and the parasitic capacitance generated between the gate electrode and the drain electrode are extremely large. Since it is small, a thin film transistor capable of high-speed operation can be formed.

Furthermore, when the thin film transistor according to the present invention is used as a pixel in an active matrix type liquid crystal display band, since the thin film transistor is a self-aligned thin film transistor with a small parasitic capacitance, color unevenness will not occur over the entire screen. ,
You can obtain high-quality images without flicker or gate signal delay.

Furthermore, in the method for manufacturing a thin film transistor of the present invention, inexpensive glass can be used for the insulating substrate, so a large-area liquid crystal display can be manufactured.

Furthermore, the present invention is applicable to the production of high-performance tertiary elements.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an invention related to improving the quality of a silicon layer by a heat treatment process after crystallizing the silicon layer by irradiation with an energy beam according to the present invention.

FIG. 2 is a diagram showing an invention related to activation of impurities channeled in an oblique direction by a heat treatment process after activating impurities in a silicon layer by laser beam irradiation according to the present invention.

FIG. 3 is a process diagram of a first embodiment of the method for manufacturing a thin film transistor of the present invention.

FIG. 4 is a process diagram of a second embodiment of the method for manufacturing a thin film transistor of the present invention.

FIG. 5 is a process diagram of a third embodiment for realizing the thin film transistor manufacturing method of the present invention.

FIG. 6 is a cross-sectional view showing a conventional method for manufacturing a thin film transistor.

FIG. 7 is a diagram showing the problem of impurity activation by a laser beam after ion implantation in a conventional example.

[Explanation of symbols]

101, 201, 301, 401, 501
Insulating substrates 102, 202, 3
02, 402, 502
Silicon dioxide film 103, 305, 403, 503
Silicon layers 104, 206, 209, 306, 313, 404,
411, 504, 512 Laser beam 105, 203, 307, 405, 505
Polycrystalline silicon layer 106
Improved quality polycrystalline silicon layers 204, 308, 406, 506
Gate insulating film 205, 309
, 407, 507
Gate electrodes 207, 311, 312, 409
, 410, 510, 511 impurity implanted region 208
Region 210 where impurities are implanted into the channel in an oblique direction
Region 211 where impurities are activated
Regions 303, 412, 513 where impurities are activated
source areas 304, 413,
514
Drain regions 314, 315
Polycrystalline silicon films 316, 414, 518 containing impurities
Interlayer insulation film 317, 415,
516
Source electrodes 318, 416, 516
Drain electrodes 319, 417, 518
passivation film

Claims (4)

[Claims] 1. A step of depositing and forming a silicon layer on an insulating substrate, a step of irradiating the silicon layer with an energy beam, a step of performing heat treatment after irradiation with the energy beam, and a step of performing heat treatment on the silicon layer after the heat treatment. a step of patterning the silicon layer, a step of depositing an insulating thin film to cover the silicon layer, a step of depositing and forming a gate electrode on the insulating thin film, and a step of implanting an impurity into the silicon thin film through the insulating thin film. A method for manufacturing a thin film transistor, comprising the steps of: activating the impurity by irradiating the impurity with a laser beam. 2. The method for manufacturing a thin film transistor according to claim 1, wherein the energy beam according to claim 1 is ultraviolet light. 3. The method for manufacturing a thin film transistor according to claim 1, wherein the ultraviolet light according to claim 2 is an excimer laser. 4. A step of depositing a silicon layer on an insulating substrate, a step of irradiating the silicon layer with an energy beam, a step of patterning the silicon layer, and a step of forming an insulating thin film to cover the silicon layer. A step of forming an adhesion;
A step of depositing and forming a gate electrode on the insulating thin film, a step of implanting an impurity into the silicon thin film through the insulating thin film, a step of activating the impurity by irradiating the impurity with a laser beam, and a step of activating the impurity. 1. A method for manufacturing a thin film transistor, the method comprising: a step including heat treatment after the step of converting the thin film transistor.