JPH04348434A - Virtual computer system - Google Patents
Virtual computer systemInfo
- Publication number
- JPH04348434A JPH04348434A JP12076191A JP12076191A JPH04348434A JP H04348434 A JPH04348434 A JP H04348434A JP 12076191 A JP12076191 A JP 12076191A JP 12076191 A JP12076191 A JP 12076191A JP H04348434 A JPH04348434 A JP H04348434A
- Authority
- JP
- Japan
- Prior art keywords
- main memory
- virtual
- lpar
- computer system
- virtual computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 79
- 238000000638 solvent extraction Methods 0.000 claims description 12
- 230000007246 mechanism Effects 0.000 claims description 11
- 230000010365 information processing Effects 0.000 claims description 6
- 102000004137 Lysophosphatidic Acid Receptors Human genes 0.000 abstract description 35
- 108090000642 Lysophosphatidic Acid Receptors Proteins 0.000 abstract description 35
- 238000000034 method Methods 0.000 description 12
- 230000005012 migration Effects 0.000 description 10
- 238000013508 migration Methods 0.000 description 10
- 101001038001 Homo sapiens Lysophosphatidic acid receptor 2 Proteins 0.000 description 9
- 102100040387 Lysophosphatidic acid receptor 2 Human genes 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 230000008859 change Effects 0.000 description 6
- 101000966782 Homo sapiens Lysophosphatidic acid receptor 1 Proteins 0.000 description 5
- 102100040607 Lysophosphatidic acid receptor 1 Human genes 0.000 description 5
- 238000005192 partition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000008521 reorganization Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000000996 ion projection lithography Methods 0.000 description 2
- 101150113952 Svs5 gene Proteins 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45541—Bare-metal, i.e. hypervisor runs directly on hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
- G06F2009/4557—Distribution of virtual machine instances; Migration and load balancing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
- G06F2009/45579—I/O management, e.g. providing access to device drivers or storage
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、仮想計算機システムに
関し、特にLPAR(Logically Parti
tioned:論理的区画化)機能を備えた仮想計算機
システムにおいて、各仮想計算機における主記憶の動的
再編成による主記憶オリジンの指定エリアへの移動が可
能とされる仮想計算機システムに適用して有効な技術に
関する。[Field of Industrial Application] The present invention relates to a virtual computer system, and in particular to LPAR (Logically Part
It is effective when applied to a virtual computer system equipped with a tioned (logical partitioning) function, where it is possible to move the main memory origin to a designated area by dynamic reorganization of the main memory in each virtual machine. related to technology.
【0002】0002
【従来の技術】従来、仮想計算機システムにおける主記
憶の再編成技術としては、仮想計算機の主記憶の拡張お
よび縮退を行う機能を備えたものが知られている。2. Description of the Related Art Conventionally, as a main memory reorganization technique in a virtual computer system, a technique having a function of expanding and degenerating the main memory of a virtual computer is known.
【0003】0003
【発明が解決しようとする課題】ところが、前記の従来
技術においては、主記憶のオリジンを変更するものでは
ない。However, in the above-mentioned prior art, the origin of the main memory is not changed.
【0004】たとえば、1つの仮想計算機が物理的な主
記憶の中心部分を割り当て、既に基本ソフト(OSなど
)を使用中で、もう1つの仮想計算機にとって必要な主
記憶が連続して割り当てられなかった場合、従来技術で
は最初の仮想計算機を停止させて主記憶オリジンを再設
定し、システム初期設定後にOSなどを再IPL(In
itial Program Loader)する必要
があった。[0004] For example, if one virtual computer allocates the central part of physical main memory and is already using basic software (such as an OS), the main memory necessary for another virtual computer cannot be allocated contiguously. In this case, the conventional technology stops the first virtual machine, resets the main memory origin, and re-IPLs the OS etc. after the system initialization.
initial Program Loader).
【0005】そこで、本発明者は、仮想計算機に主記憶
および仮想記憶の動的再編成を開発するにあたり、使い
勝手の面から有効な機能を検討した結果、物理的に搭載
された主記憶を分割して、分割された主記憶毎に仮想計
算機を構築することが可能とされることを見い出した。[0005] Therefore, in developing dynamic reorganization of main memory and virtual memory for a virtual computer, the present inventor investigated effective functions from the viewpoint of usability and decided to divide the physically installed main memory. We discovered that it is possible to construct a virtual machine for each divided main memory.
【0006】すなわち、本発明の目的は、他方の仮想計
算機に主記憶が割り当てられない場合に、最初の一方の
仮想計算機の状態をそのままにし、主記憶オリジンを指
定エリアに移して他方の仮想計算機を使用可能状態とす
ることにより、情報処理装置の効率化および使い勝手の
向上を図ることができる仮想計算機システムを提供する
ことにある。That is, an object of the present invention is to leave the state of the first virtual machine as it is, move the main memory origin to a specified area, and transfer the main memory to the other virtual machine when main memory is not allocated to the other virtual machine. An object of the present invention is to provide a virtual computer system that can improve the efficiency and usability of an information processing device by making it usable.
【0007】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
【0008】[0008]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions will be as follows.
It is as follows.
【0009】すなわち、本発明の仮想計算機システムは
、少なくとも情報処理装置とこの情報処理装置のオペレ
ータインタフェースを提供するサービスプロセッサとを
備えた仮想計算機システムであって、複数の仮想計算機
を制御するハードウェア機構と、このハードウェア機構
を排他的または時分割で論理的に区画化する論理区画手
段と、複数の仮想計算機の論理区画手段による指定仮想
計算機の主記憶オリジンを変更して主記憶エリアを移動
する主記憶移動手段とを備えるものである。That is, the virtual computer system of the present invention is a virtual computer system that includes at least an information processing device and a service processor that provides an operator interface for the information processing device, and includes hardware that controls a plurality of virtual computers. a mechanism, a logical partitioning means for logically partitioning this hardware mechanism in an exclusive or time-sharing manner, and a logical partitioning means for multiple virtual machines to change the main memory origin of a specified virtual machine and move the main memory area. and a main memory moving means.
【0010】また、前記複数の仮想計算機が物理的主記
憶をすべて使用している場合に、動的に少なくとも2つ
以上の仮想計算機の主記憶エリアを交換するようにした
ものである。[0010] Furthermore, when the plurality of virtual machines are using all of the physical main memories, the main memory areas of at least two or more virtual machines are dynamically exchanged.
【0011】さらに、前記複数の仮想計算機が稼働中に
一方の仮想計算機の主記憶エリアを拡張する場合に、他
方の仮想計算機の主記憶エリアを自由に移動するように
したものである。Furthermore, when the main storage area of one of the virtual computers is expanded while the plurality of virtual computers are in operation, the main storage area of the other virtual computer can be freely moved.
【0012】0012
【作用】前記した仮想計算機システムによれば、ハード
ウェア機構、論理区画手段および主記憶移動手段を備え
ることにより、たとえば複数の仮想計算機が物理的主記
憶をすべて使用している場合には、動的に少なくとも2
つ以上の仮想計算機の主記憶エリアを交換し、また複数
の仮想計算機が稼働中に一方の仮想計算機の主記憶エリ
アを拡張する場合には、他方の仮想計算機の主記憶エリ
アを自由に移動させて、ハードウェア機構で稼働中の複
数の仮想計算機の各割り当て主記憶オリジンを自由に変
更することができる。[Operation] According to the above-mentioned virtual computer system, by providing a hardware mechanism, a logical partition means, and a main memory moving means, if a plurality of virtual machines are using all of the physical main memory, for example, the operation at least 2
When exchanging the main memory areas of two or more virtual machines or expanding the main memory area of one virtual machine while multiple virtual machines are running, you can freely move the main memory area of the other virtual machine. As a result, it is possible to freely change the main memory origin assigned to each of the multiple virtual machines running on the hardware mechanism.
【0013】すなわち、論理区画手段で区画化された指
定仮想計算機の主記憶オリジンを主記憶移動手段により
操作すると、サービスプロセッサからこのオペレーショ
ンが読み出され、指定仮想計算機の制御部に対して主記
憶オリジンを変更することを連絡する。そして、制御部
は論理的に接続されている命令プロセッサ制御部を停止
させる。That is, when the main memory origin of a designated virtual machine partitioned by the logical partitioning means is operated by the main memory moving means, this operation is read out from the service processor, and the main memory is sent to the control unit of the designated virtual machine. Notify us that you wish to change your origin. Then, the control section stops the logically connected instruction processor control section.
【0014】次に、指定された主記憶オリジンの妥当性
を、全仮想計算機の物理資源を管理している資源管理部
に確認し、指定エリアに移動できることが確認できた後
、仮想計算機の制御部はデータ移動をページ単位に行う
。そして、入出力プロセッサに、この仮想計算機の新し
い主記憶エリアの範囲をSALE(Set Addre
ss Limit Extendes)命令により連絡
し、最後にSIE(Start Interpreti
ve Execution)命令のパラメータ内主記憶
オリジンのエリアを変更して命令プロセッサ制御部を再
開させる。Next, the validity of the specified main memory origin is confirmed with the resource management unit that manages the physical resources of all virtual machines, and after confirming that it can be moved to the specified area, the virtual machine is controlled. The section moves data page by page. Then, SALE (Set Address) the range of the new main memory area of this virtual machine to the input/output processor.
ss Limit Extendes) command, and finally SIE (Start Interpretation).
(Execution) Change the area of the main memory origin in the parameter of the instruction and restart the instruction processor control unit.
【0015】これにより、指定仮想計算機の主記憶移動
を、この仮想計算機の使用ユーザに対して影響を与える
ことなく実現することができる。[0015] This makes it possible to move the main memory of the designated virtual machine without affecting the users of this virtual machine.
【0016】[0016]
【実施例】図1は本発明の一実施例である仮想計算機シ
ステムのハードウェア資源構成をを示すブロック図、図
2は本実施例の仮想計算機システムにおける主記憶移動
手段の構成と、この主記憶移動手段による主記憶移動処
理手順を示す説明図、図3は本実施例における論理区画
手段による主記憶割り当てを示す説明図、図4は本実施
例における主記憶移動処理後の主記憶割り当てを示す説
明図である。[Embodiment] FIG. 1 is a block diagram showing the hardware resource configuration of a virtual computer system according to an embodiment of the present invention, and FIG. FIG. 3 is an explanatory diagram showing the main memory migration processing procedure by the memory migration means. FIG. 3 is an explanatory diagram showing the main memory allocation by the logical partitioning means in this embodiment. FIG. 4 is an explanatory diagram showing the main memory allocation after the main memory migration processing in this embodiment. FIG.
【0017】まず、図1により本実施例の仮想計算機シ
ステムのハードウェア資源構成を説明する。First, the hardware resource configuration of the virtual computer system of this embodiment will be explained with reference to FIG.
【0018】本実施例の仮想計算機システムのハードウ
ェア資源は、たとえばLPARモード(論理区画手段)
という新しい分割形態を持った仮想計算機システムとさ
れ、4組の命令プロセッサ(IP1〜IP4)1、主記
憶部/仮想記憶部(MS/ES)2およびチャネルパス
(CH)3と、デバイス(DEVICE)4とから構成
され、デバイス4が4組の各仮想計算機群に分割されて
使用される。The hardware resources of the virtual computer system of this embodiment are, for example, in LPAR mode (logical partition means).
It is a virtual computer system with a new partitioning form called 4 sets of instruction processors (IP1 to IP4) 1, main memory/virtual memory (MS/ES) 2, channel path (CH) 3, and device (DEVICE). ) 4, and the device 4 is divided into four virtual machine groups for use.
【0019】また、上記のハードウェア資源は、LPA
Rモードにおいて排他的または時分割で分割され、論理
的な計算機システムであるLPARに分割される。すな
わち、上記ハードウェア構成の内、命令プロセッサ1は
時分割によって各LPARに割り当てられ、他のハード
ウェアは排他的に分割されるようになっている。[0019] Furthermore, the above hardware resources are LPA
In R mode, it is divided exclusively or time-divisionally into LPARs, which are logical computer systems. That is, in the above hardware configuration, the instruction processor 1 is allocated to each LPAR by time division, and other hardware is exclusively divided.
【0020】そして、各LPARに割り当てられた主記
憶が、図2に示すような主記憶移動処理(主記憶移動手
段)により動的に再構成され、物理主記憶内で自由自在
に各LPARの主記憶オリジンが変更されて主記憶エリ
アが移動可能な機能を備えている。Then, the main memory assigned to each LPAR is dynamically reconfigured by the main memory migration process (main memory migration means) as shown in FIG. It has a function that allows the main memory area to be moved by changing the main memory origin.
【0021】すなわち、主記憶移動処理は、図2に示す
ように各LPARに対するオペレーションインタフェー
スを提供するLPARフレームを備えたSVP( Se
rvice Processor)5と、各LPARへ
の操作コマンドなどを制御するLPAR制御部6と、L
PAR制御部6からの指示に従ってゲストを制御し、ま
たシミュレーションが必要な命令に対してはシミュレー
ション処理を行うLIP( Logical Inst
ruction Processor)制御部7と、全
LPARの物理資源情報をすべて管理する資源管理部8
の構成により実行される。That is, the main memory migration process is performed using an SVP (Se
(rvice processor) 5, an LPAR control unit 6 that controls operation commands to each LPAR, and
LIP (Logical Inst.
control unit 7 and a resource management unit 8 that manages all physical resource information of all LPARs.
It is executed by the configuration.
【0022】次に、本実施例の作用について、たとえば
2つのLPARを稼働させる場合について図2により説
明する。Next, the operation of this embodiment will be explained with reference to FIG. 2, for example, when two LPARs are operated.
【0023】始めに、各LPARが稼働する前に定義し
たMSオリジンおよびMSサイズは図3(a) に示す
ようになっており、MSギャップがこのLPARとMS
上位のLPARとの間の未使用エリアのサイズを示した
ものである。すなわち、LPAR1とLPAR2の間に
は、MSのギャップがないためにLPAR1のMSギャ
ップは“0”となる。[0023] First, the MS origin and MS size defined before each LPAR starts operating are as shown in Fig. 3(a), and the MS gap is between this LPAR and the MS size.
This shows the size of the unused area between the upper LPAR and the upper LPAR. That is, since there is no MS gap between LPAR1 and LPAR2, the MS gap of LPAR1 is "0".
【0024】また、定義された2つのLPARが稼働し
ている時の主記憶のアロケーション状態は、図3(b)
に示すようにLPAR1がMS=0Mバイトから12
8Mバイトまで割り当てられており、残りのMS=12
5Mバイトが未割り当てエリアである。Furthermore, the allocation state of the main memory when the two defined LPARs are in operation is shown in FIG. 3(b).
As shown in
Up to 8MB is allocated, remaining MS = 12
5 Mbytes is an unallocated area.
【0025】そして、2つのLPARが稼働中に、LP
AR1のMSエリアを拡大する必要ができた時に本発明
の主記憶移動(MOVE MS)機能を利用すること
ができる。[0025] Then, while the two LPARs are in operation, the LP
When it becomes necessary to expand the MS area of AR1, the main memory movement (MOVE MS) function of the present invention can be used.
【0026】まず、たとえばSVP5上のLPARフレ
ームで、LPAR2に対し、MOVE MSコマンド
(以下、MVSTORコマンドという)をMS0=19
2と指定する。このオペレーションにより、制御がSV
P5からLPAR2のLPAR制御部6に移る。First, for example, in the LPAR frame on SVP5, a MOVE MS command (hereinafter referred to as MVSTOR command) is sent to LPAR2 with MS0=19.
Specify 2. This operation causes the control to
The process moves from P5 to the LPAR control unit 6 of LPAR2.
【0027】そして、LPAR制御部6では、まずLI
Pを停止させるためにLIP制御部7に指示を出し、L
IP制御部7はLIP、すなわちLPAR2のゲストを
ストップ状態にする(処理フロー201)。[0027] Then, in the LPAR control unit 6, first, the LI
Instructs the LIP control unit 7 to stop the L
The IP control unit 7 puts the LIP, that is, the guest of LPAR2, in a stopped state (processing flow 201).
【0028】さらに、このLPAR2につながる全ての
I/Oデバイスに対し、BUSY状態が回避されるのを
最大10秒間待つ(処理フロー202)。通常、LIP
停止時、I/OデバイスはBUSY状態をすぐに回避で
きるが、特殊なケースを想定して10秒間タイマーを用
意している。Furthermore, the CPU waits for a maximum of 10 seconds for all I/O devices connected to this LPAR2 to avoid the BUSY state (processing flow 202). Usually, L.I.P.
When stopped, the I/O device can immediately avoid the BUSY state, but a 10 second timer is provided for special cases.
【0029】たとえば、タイムアウトの場合は、その旨
のメッセージを出力してBUSYなI/Oデバイスを指
摘する。この処理フロー202の必要性は、処理フロー
201でLIPを停止させたが、IOPが稼働中のため
に、I/O命令によって従来エリア(稼働前エリア)に
対してアクセスする可能性を防ぐためである。For example, in the case of a timeout, a message to that effect is output and a BUSY I/O device is pointed out. The necessity of this processing flow 202 is to prevent the possibility of accessing the conventional area (pre-operation area) by an I/O command because the IOP is in operation although the LIP was stopped in the processing flow 201. It is.
【0030】そして、コマンドにより指定されたMSオ
リジン(ここでは192Mバイト)が打倒かどうかのチ
ェック、すなわちMOVEできるか否かのチェックを資
源管理部8で行う(処理フロー203)。ここで、資源
管理部8は全てのLPARのMSマップを保持しており
、指定されたMSオリジンからそのサイズ分、他LPA
Rが使用していないかのチェックを行う。[0030] Then, the resource management unit 8 checks whether the MS origin (192 Mbytes in this case) specified by the command has been overthrown, that is, whether it can be moved (processing flow 203). Here, the resource management unit 8 holds MS maps of all LPARs, and from the specified MS origin, other LPARs are
Check whether R is not using it.
【0031】本実施例では、MSオリジンの192Mバ
イトから384MバイトまではLPAR2が使用してい
て、384Mバイト以降は未割り当てであるために移動
可能である。そして、資源管理部8では、MS移動が可
能である時にIOPに対してSALE命令を発行し、更
新後のLPARのMS範囲を連絡する。In this embodiment, LPAR2 uses the MS origin from 192 Mbytes to 384 Mbytes, and the rest after 384 Mbytes is unallocated and can be moved. Then, the resource management unit 8 issues a SALE command to the IOP when MS movement is possible, and notifies the MS range of the updated LPAR.
【0032】続いて、実際のメモリ転送処理を処理フロ
ー204〜209に基づいて説明する。Next, actual memory transfer processing will be explained based on processing flows 204 to 209.
【0033】まず、転送を開始するデータのスタートア
ドレスおよび転送先アドレスのスタートアドレスを設定
する(処理フロー204)。本実施例では、転送前アド
レスが384Mバイト−1ページで、転送先アドレスが
448Mバイト−1ページである。すなわち、転送先ア
ドレスより開始し、1ページ分ずつアドレスを減じてい
くことになる。First, a start address of data to be transferred and a start address of a transfer destination address are set (processing flow 204). In this embodiment, the pre-transfer address is 384 Mbytes - 1 page, and the transfer destination address is 448 Mbytes - 1 page. That is, starting from the transfer destination address, the address is decreased one page at a time.
【0034】そして、転送前エリアのKEYを読み出し
(処理フロー205)、レジスタに退避する。そして、
処理フロー204で求めたアドレスより、転送先エリア
にデータを転送し(処理フロー206)、この転送先エ
リアに先程読み込んだKEYをセットする(処理フロー
207)。これで、1ページ分のメモリ転送は完了した
ことになる。Then, the KEY in the pre-transfer area is read (processing flow 205) and saved in the register. and,
Data is transferred to the transfer destination area from the address obtained in process flow 204 (process flow 206), and the KEY read earlier is set in this transfer destination area (process flow 207). This means that the memory transfer for one page is completed.
【0035】さらに、次に転送するエリアおよび転送先
エリアのアドレスを更新する(処理フロー208)。本
実施例では、1ページ分ずつ減じていき、この処理をL
PARのMSサイズ分(ページ単位)繰り返す。Furthermore, the addresses of the next area to be transferred and the destination area are updated (processing flow 208). In this embodiment, the amount is decreased one page at a time, and this process is
Repeat for the MS size of PAR (page unit).
【0036】以上で、MS転送処理は終了する(処理フ
ロー209)。最後に、LIPを再開始させるために、
LIP制御部7に指示を出す。この時、LIP制御部7
は新しくなったMSオリジンをセットするため、SDを
更新後、LIP、すなわちLPAR2のゲストをスター
トさせる(処理フロー210)。また、SVP5上のフ
レームに対し、MVSTORコマンドの結果を報告する
(処理フロー211)。本実施例では、MVSTORコ
マンドは正常に終了する。With this, the MS transfer process ends (processing flow 209). Finally, to restart LIP,
An instruction is issued to the LIP control unit 7. At this time, the LIP control section 7
In order to set the new MS origin, after updating the SD, the LIP, that is, the guest of LPAR2 is started (processing flow 210). Furthermore, the result of the MVSTOR command is reported for the frame on the SVP 5 (processing flow 211). In this example, the MVSTOR command completes normally.
【0037】この場合に、MVSTORコマンドの終了
後におけるLPARのMS割り当て状況は図4(a)
に示すようになり、MVSTORコマンドによってLP
AR1のMSギャップができたため、LPAR1はこの
MSギャップ分だけMSを増やすことが可能となる。ま
た、LPAR1,2のMSアロケーション状態は図4(
b)に示すようになり、LPAR2がまだMS上位方向
に61Mバイト移動可能である。In this case, the LPAR MS allocation status after the MVSTOR command ends is shown in FIG. 4(a).
The LP is now as shown in
Since the MS gap of AR1 is created, LPAR1 can increase the number of MSs by this MS gap. In addition, the MS allocation status of LPAR1 and 2 is shown in Figure 4 (
As shown in b), LPAR2 can still be moved by 61 Mbytes in the upper MS direction.
【0038】以上のように、LPAR2の稼働状態に影
響を与えることなく、LPAR1のMSを拡大させるこ
とが可能となる。As described above, it is possible to expand the MS of LPAR1 without affecting the operating state of LPAR2.
【0039】従って、本実施例の仮想計算機システムに
よれば、LPARモード機能を持つ仮想計算機システム
において、物理主記憶内で自由自在に各LPARの主記
憶オリジンを変更して主記憶エリアを移動可能なMVS
TORコマンドを提供することができるので、従来のよ
うに稼働中の仮想計算機を停止させ、主記憶オリジンの
再設定後にさらに再IPLする必要がなくなり、他の主
記憶エリアにリロケーションできるので稼働中の仮想計
算機の継続が可能となる。Therefore, according to the virtual computer system of this embodiment, in a virtual computer system having an LPAR mode function, it is possible to freely change the main memory origin of each LPAR within the physical main memory and move the main memory area. MVS
Since the TOR command can be provided, there is no need to stop a running virtual machine and re-IPL it after resetting the main memory origin as in the past, and it can be relocated to another main memory area. It becomes possible to continue using the virtual machine.
【0040】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
で種々変更可能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained based on examples, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say.
【0041】以上の説明では、主として本発明者によっ
てなされた発明をその利用分野であるLPAR機能を備
えた仮想計算機システムに適用した場合について説明し
たが、これに限定されるものではなく、他の仮想計算機
システムについても広く適用可能である。[0041] In the above explanation, the invention made by the present inventor was mainly applied to the field of application, which is a virtual computer system equipped with an LPAR function. It is also widely applicable to virtual computer systems.
【0042】[0042]
【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
下記のとおりである。[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by the typical inventions are briefly explained as follows.
It is as follows.
【0043】すなわち、複数の仮想計算機を制御するハ
ードウェア機構と、このハードウェア機構を排他的また
は時分割で論理的に区画化する論理区画手段と、複数の
仮想計算機の論理区画手段による指定仮想計算機の主記
憶オリジンを変更して主記憶エリアを移動する主記憶移
動手段とを備えることにより、たとえば複数の仮想計算
機が物理的主記憶をすべて使用している場合には、動的
に少なくとも2つ以上の仮想計算機の主記憶エリアを交
換したり、または複数の仮想計算機が稼働中に一方の仮
想計算機の主記憶エリアを拡張する場合には、他方の仮
想計算機の主記憶エリアを自由に移動させる機能を得る
ことができる。That is, a hardware mechanism for controlling a plurality of virtual machines, a logical partition means for logically partitioning this hardware mechanism either exclusively or in a time-sharing manner, and a designated virtual machine by the logical partition means for the plurality of virtual machines. By providing a main memory moving means that changes the main memory origin of the computer and moves the main memory area, for example, when multiple virtual computers are using all of the physical main memory, at least two When exchanging the main memory areas of two or more virtual machines, or expanding the main memory area of one virtual machine while multiple virtual machines are running, you can freely move the main memory area of the other virtual machine. You can obtain functions that allow you to
【0044】これにより、ハードウェア機構で稼働中の
複数の仮想計算機の各割り当て主記憶オリジンを自由に
変更し、稼働中の仮想計算機を停止させることなく、他
の主記憶にリロケーションできるので、稼働中の仮想計
算機をそのまま継続することが可能となる。[0044] This makes it possible to freely change the allocated main memory origins of multiple virtual machines running on the hardware mechanism and relocate them to other main memory without stopping the running virtual machines. It becomes possible to continue using the virtual machine inside.
【0045】この結果、指定仮想計算機の主記憶移動を
、この仮想計算機の使用ユーザに対して影響を与えるこ
となく実現し、情報処理装置の効率化および使い勝手の
向上が可能とされる仮想計算機システムを得ることがで
きる。[0045] As a result, a virtual computer system is realized in which the main memory of a designated virtual machine can be moved without affecting the users of this virtual machine, thereby making it possible to improve the efficiency and usability of an information processing device. can be obtained.
【図1】本発明の一実施例である仮想計算機システムの
ハードウェア資源構成を示すブロック図である。FIG. 1 is a block diagram showing the hardware resource configuration of a virtual computer system that is an embodiment of the present invention.
【図2】本実施例の仮想計算機システムにおける主記憶
移動手段の構成と、この主記憶移動手段による主記憶移
動処理手順を示す説明図である。FIG. 2 is an explanatory diagram showing the configuration of a main memory migration means in the virtual computer system of this embodiment and a main memory migration processing procedure by this main memory migration means.
【図3】本実施例における論理区画手段による主記憶割
り当てを示す説明図である。FIG. 3 is an explanatory diagram showing main memory allocation by logical partitioning means in this embodiment.
【図4】本実施例における主記憶移動処理後の主記憶割
り当てを示す説明図である。FIG. 4 is an explanatory diagram showing main memory allocation after main memory migration processing in this embodiment.
1 命令プロセッサ 2 主記憶部/仮想記憶部 3 チャネルパス 4 デバイス 5 SVP 6 LPAR制御部 7 LIP制御部 8 資源管理部 1 Instruction processor 2 Main memory/virtual memory 3 Channel path 4 Device 5 SVP 6 LPAR control section 7 LIP control section 8 Resource Management Department
Claims (3)
装置のオペレータインタフェースを提供するサービスプ
ロセッサとを備えた仮想計算機システムであって、複数
の仮想計算機を制御するハードウェア機構と、該ハード
ウェア機構を排他的または時分割で論理的に区画化する
論理区画手段と、前記複数の仮想計算機の該論理区画手
段による指定仮想計算機の主記憶オリジンを変更して主
記憶エリアを移動する主記憶移動手段とを備え、前記ハ
ードウェア機構で稼働中の前記複数の仮想計算機の各割
り当て主記憶オリジンを自由に変更することを特徴とす
る仮想計算機システム。1. A virtual computer system comprising at least an information processing device and a service processor that provides an operator interface for the information processing device, the system comprising a hardware mechanism for controlling a plurality of virtual computers, and a hardware mechanism for controlling the hardware mechanism. a logical partitioning means for logically partitioning the plurality of virtual machines in an exclusive or time-sharing manner; and a main memory moving means for changing the main memory origin of a designated virtual machine by the logical partitioning means to move the main memory area of the plurality of virtual machines. A virtual computer system, characterized in that the allocated main memory origin of each of the plurality of virtual machines running on the hardware mechanism is freely changed.
をすべて使用している場合に、動的に少なくとも2つ以
上の仮想計算機の主記憶エリアを交換することを特徴と
する請求項1記載の仮想計算機システム。2. The main memory area of at least two or more virtual machines is dynamically exchanged when the plurality of virtual machines are using all of the physical main memory. virtual computer system.
の仮想計算機の主記憶エリアを拡張する場合に、他方の
仮想計算機の主記憶エリアを自由に移動することを特徴
とする請求項1記載の仮想計算機システム。3. When expanding the main storage area of one of the virtual computers while the plurality of virtual computers are in operation, the main storage area of the other virtual computer is freely moved. virtual computer system.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12076191A JPH04348434A (en) | 1991-05-27 | 1991-05-27 | Virtual computer system |
GB9210282A GB2256513B (en) | 1991-05-27 | 1992-05-13 | A method of and system for dynamically relocating main storage area to virtual machine |
DE19924217444 DE4217444A1 (en) | 1991-05-27 | 1992-05-26 | METHOD AND DEVICE FOR THE DYNAMIC TRANSFER OF VIRTUAL MACHINES IN A MAIN STORAGE |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12076191A JPH04348434A (en) | 1991-05-27 | 1991-05-27 | Virtual computer system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04348434A true JPH04348434A (en) | 1992-12-03 |
Family
ID=14794341
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12076191A Pending JPH04348434A (en) | 1991-05-27 | 1991-05-27 | Virtual computer system |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPH04348434A (en) |
DE (1) | DE4217444A1 (en) |
GB (1) | GB2256513B (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06250919A (en) * | 1993-02-08 | 1994-09-09 | Internatl Business Mach Corp <Ibm> | Computer memory system |
WO2002005091A1 (en) * | 2000-07-06 | 2002-01-17 | Fujitsu Limited | Virtual computer system and control method |
JP2004526229A (en) * | 2000-12-27 | 2004-08-26 | インテル・コーポレーション | A method for resolving address space conflicts between a virtual machine monitor and a guest operating system |
JP2008541214A (en) * | 2005-05-05 | 2008-11-20 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Managing computer memory in a computing environment with dynamic logical partitioning |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0635732A (en) * | 1992-07-14 | 1994-02-10 | Hitachi Ltd | Area assigning method for storage device |
JPH07262093A (en) * | 1994-03-17 | 1995-10-13 | Hitachi Ltd | Control system for reconstruction of storage area |
US6128714A (en) | 1994-03-17 | 2000-10-03 | Hitachi, Ltd. | Method of processing a data move instruction for moving data between main storage and extended storage and data move instruction processing apparatus |
US5819061A (en) * | 1994-07-25 | 1998-10-06 | International Business Machines Corporation | Method and apparatus for dynamic storage reconfiguration in a partitioned environment |
US6760441B1 (en) | 2000-03-31 | 2004-07-06 | Intel Corporation | Generating a key hieararchy for use in an isolated execution environment |
US6769058B1 (en) | 2000-03-31 | 2004-07-27 | Intel Corporation | Resetting a processor in an isolated execution environment |
US6795905B1 (en) | 2000-03-31 | 2004-09-21 | Intel Corporation | Controlling accesses to isolated memory using a memory controller for isolated execution |
US6976162B1 (en) | 2000-06-28 | 2005-12-13 | Intel Corporation | Platform and method for establishing provable identities while maintaining privacy |
US6986052B1 (en) | 2000-06-30 | 2006-01-10 | Intel Corporation | Method and apparatus for secure execution using a secure memory partition |
US7793111B1 (en) | 2000-09-28 | 2010-09-07 | Intel Corporation | Mechanism to handle events in a machine with isolated execution |
US7085705B2 (en) | 2000-12-21 | 2006-08-01 | Microsoft Corporation | System and method for the logical substitution of processor control in an emulated computing environment |
AU2002231073A1 (en) * | 2000-12-21 | 2002-07-01 | Connectix Corporation | Logical substitution of processor control in an emulated computing environment |
US7024555B2 (en) | 2001-11-01 | 2006-04-04 | Intel Corporation | Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment |
US7124273B2 (en) | 2002-02-25 | 2006-10-17 | Intel Corporation | Method and apparatus for translating guest physical addresses in a virtual machine environment |
US7631196B2 (en) | 2002-02-25 | 2009-12-08 | Intel Corporation | Method and apparatus for loading a trustable operating system |
US7069442B2 (en) | 2002-03-29 | 2006-06-27 | Intel Corporation | System and method for execution of a secured environment initialization instruction |
US7318141B2 (en) | 2002-12-17 | 2008-01-08 | Intel Corporation | Methods and systems to control virtual machines |
US7900017B2 (en) | 2002-12-27 | 2011-03-01 | Intel Corporation | Mechanism for remapping post virtual machine memory pages |
US7415708B2 (en) | 2003-06-26 | 2008-08-19 | Intel Corporation | Virtual machine management using processor state information |
US7739521B2 (en) | 2003-09-18 | 2010-06-15 | Intel Corporation | Method of obscuring cryptographic computations |
US20050080934A1 (en) | 2003-09-30 | 2005-04-14 | Cota-Robles Erik C. | Invalidating translation lookaside buffer entries in a virtual machine (VM) system |
US8156343B2 (en) | 2003-11-26 | 2012-04-10 | Intel Corporation | Accessing private data about the state of a data processing machine from storage that is publicly accessible |
US8037314B2 (en) | 2003-12-22 | 2011-10-11 | Intel Corporation | Replacing blinded authentication authority |
US7802085B2 (en) | 2004-02-18 | 2010-09-21 | Intel Corporation | Apparatus and method for distributing private keys to an entity with minimal secret, unique information |
US7620949B2 (en) | 2004-03-31 | 2009-11-17 | Intel Corporation | Method and apparatus for facilitating recognition of an open event window during operation of guest software in a virtual machine environment |
US8271976B2 (en) | 2004-06-30 | 2012-09-18 | Microsoft Corporation | Systems and methods for initializing multiple virtual processors within a single virtual machine |
US7383405B2 (en) | 2004-06-30 | 2008-06-03 | Microsoft Corporation | Systems and methods for voluntary migration of a virtual machine between hosts with common storage connectivity |
US7840962B2 (en) | 2004-09-30 | 2010-11-23 | Intel Corporation | System and method for controlling switching between VMM and VM using enabling value of VMM timer indicator and VMM timer value having a specified time |
US8146078B2 (en) | 2004-10-29 | 2012-03-27 | Intel Corporation | Timer offsetting mechanism in a virtual machine environment |
US8924728B2 (en) | 2004-11-30 | 2014-12-30 | Intel Corporation | Apparatus and method for establishing a secure session with a device without exposing privacy-sensitive information |
US8533777B2 (en) | 2004-12-29 | 2013-09-10 | Intel Corporation | Mechanism to determine trust of out-of-band management agents |
US7395405B2 (en) | 2005-01-28 | 2008-07-01 | Intel Corporation | Method and apparatus for supporting address translation in a virtual machine environment |
US7809957B2 (en) | 2005-09-29 | 2010-10-05 | Intel Corporation | Trusted platform module for generating sealed data |
US8014530B2 (en) | 2006-03-22 | 2011-09-06 | Intel Corporation | Method and apparatus for authenticated, recoverable key distribution with no database secrets |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4916608A (en) * | 1986-05-30 | 1990-04-10 | International Business Machines Corporation | Provision of virtual storage resources to an operating system control program |
JP2615103B2 (en) * | 1987-12-11 | 1997-05-28 | 株式会社日立製作所 | Virtual computer system |
EP0473802B1 (en) * | 1990-09-03 | 1995-11-08 | International Business Machines Corporation | Computer with extended virtual storage concept |
-
1991
- 1991-05-27 JP JP12076191A patent/JPH04348434A/en active Pending
-
1992
- 1992-05-13 GB GB9210282A patent/GB2256513B/en not_active Expired - Fee Related
- 1992-05-26 DE DE19924217444 patent/DE4217444A1/en not_active Withdrawn
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06250919A (en) * | 1993-02-08 | 1994-09-09 | Internatl Business Mach Corp <Ibm> | Computer memory system |
US5652853A (en) * | 1993-02-08 | 1997-07-29 | International Business Machines Corporation | Multi-zone relocation facility computer memory system |
WO2002005091A1 (en) * | 2000-07-06 | 2002-01-17 | Fujitsu Limited | Virtual computer system and control method |
JP2004526229A (en) * | 2000-12-27 | 2004-08-26 | インテル・コーポレーション | A method for resolving address space conflicts between a virtual machine monitor and a guest operating system |
JP2008541214A (en) * | 2005-05-05 | 2008-11-20 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Managing computer memory in a computing environment with dynamic logical partitioning |
Also Published As
Publication number | Publication date |
---|---|
GB2256513B (en) | 1994-11-23 |
GB2256513A (en) | 1992-12-09 |
DE4217444A1 (en) | 1992-12-03 |
GB9210282D0 (en) | 1992-07-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH04348434A (en) | Virtual computer system | |
JP3225804B2 (en) | I / O channel expansion method | |
JP4921384B2 (en) | Method, apparatus and system for dynamically reallocating memory from one virtual machine to another | |
JP3653159B2 (en) | Virtual computer migration control method between virtual computer systems | |
US7539782B2 (en) | Method of virtualizing I/O resources in a computer system | |
JP2737823B2 (en) | Computer system | |
JP3186244B2 (en) | Virtual computer system | |
GB2508983A (en) | Migration of virtual machines with reassignment of hardware memory segments | |
KR20040028805A (en) | System for Yielding to a Processor | |
JP2010237737A (en) | Apparatus for dynamically migrating lpar with pass-through i/o device, method and program thereof | |
TW200406673A (en) | Procedure for dynamic reconfiguration of resources of logical partitions | |
JPH06187178A (en) | Input and output interruption control method for virtual computer system | |
JPH0754471B2 (en) | Data processing device | |
JPH06110715A (en) | Dynamic allocating method for computer resources in virtual computer system | |
US5369750A (en) | Method and apparatus for configuring multiple absolute address spaces | |
JPH10301795A (en) | Virtual computer system | |
JPH10293695A (en) | Dynamic reconfiguration system of logic computer system | |
JP3490212B2 (en) | Input / output channel expansion method for information processing device | |
JP3587631B2 (en) | Virtual computer system | |
JPH0470935A (en) | Computer system | |
JPH06110717A (en) | Complex computer system | |
JP2864255B2 (en) | Virtual computer system | |
JP2001265613A (en) | Virtual computer system | |
JPH04346136A (en) | Virtual instruction processor structure control method | |
CN115756742A (en) | Performance optimization design method, system, medium and device for direct I/O virtualization |