JPH04346150A - Data transfer processing system - Google Patents

Abstract

PURPOSE:To set direct memory access transfer in any microprocessor or in a batch when transferring some continuous memory blocks to a memory space. CONSTITUTION:Transfer information is written in an empty position in an auxiliary register 206 through a window register 207. Receiving a transfer enabling signal to main registers 201 to 203, the data of an auxiliary register group 206 can be transferred to the main registers 201 to 203 for the required transfer channel. In this case, the main registers 201 to 203 are a group of internal setting registers to set a reference address, offset address, and a transfer mode, etc., of the transfer channel corresponding to each input/output device. Thus, when transferring several memory blocks, the transfer setting can be performed any time or simultaneously, resulting in providing the flexibility in microprocessor processing.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer processing system using a DMAC for controlling data transfer between a plurality of input/output devices connected to a common transmission bus and a memory system.

0002

2. Description of the Related Art In recent years, with the trend toward decentralization of control systems, a plurality of input/output devices are connected to a common transmission bus and controlled while mutually transferring data. Furthermore, with the advancement of high-speed arithmetic processing processors and large-capacity memories, the amount of data to be handled has become enormous, and high-speed and efficient data processing has become required.

Conventionally, in large-scale systems with a large number of connected input/output devices and systems that require high speed,
In order to reduce the burden on the microprocessor, a DMAC (direct memory access controller) 403 is used to connect input/output devices and 404 as shown in FIG.
~406 Controls direct data transfer to and from the memory system 402. Here, 401 is a microprocessor, 407 is a CPU bus, and 408 is a DM
A bus 409 and 410 are address buses.

In such a conventional data transfer processing system using a DMAC, when using DMA transfer, the microprocessor 401 sets the internal setting register 403a of the DMAC 403 in advance for each transmission channel.
Reference addresses (base addresses) 305 to 308 for transfer channels corresponding to each input/output device 404 to 406 as shown in FIG. ~3) and other setting information to DMAC4
It is necessary to set it in the internal setting register 403a of 03. After that, DM to each input/output device 404 to 406
Specify A transfer mode and transfer each input/output device 404 to 406
Assertion of the DREQ signal from the transfer mode requests use of the bus corresponding to the transfer mode.

[0005] In the DMAC 403, according to the predetermined priority distribution of the DREQ signal,
D above allows input/output devices that support the DREQ signal with higher priority to use the common bus.
Each input/output device 404-406 is notified by returning a DACK signal corresponding to the REQ signal. Subsequent operations are performed using the internal setting register 40 of the DMAC403.
This is done according to the settings in 3a. After the data transfer process to the input/output device is completed, use of the bus is permitted by returning a DACK signal corresponding to the other input/output device having the next highest priority.

In this conventional procedure, for the same transmission channel, the setting of the next memory block is changed to the DMAC4 until the data transfer to the input/output device is completely completed.
It is not possible to set the internal setting register of 03, and the microprocessor needs to set it again after the transfer is completed.

[0007]

[Problem to be solved by the invention] In this way, conventional DM
With AC, the microprocessor could not write to the DMAC's internal configuration registers until a DMA transfer was completed for the same transmission channel. In order to increase the flexibility of microprocessor processing, if setting information can be written to another register group inside the DMAC even during DMA transfer of any memory block, transfer settings can be performed sequentially without waiting for the DMA transfer to finish. It is possible to write data.

The present invention solves the above-mentioned conventional problems by providing a group of auxiliary registers in the DMA so that many memory blocks can be set at once and at any time.
It is an object of the present invention to provide a data transfer processing system that can increase the flexibility of microprocessor processing by allowing the MA transfer mode to be specified.

[0009]

[Means for Solving the Problems] In order to solve the above problems, the data transfer processing system of the present invention enables direct data transfer between a plurality of input/output devices and a memory system connected to a common bus. In a data transfer processing system using a DMAC, a group of auxiliary registers for setting the transfer mode is provided inside the DMAC in addition to internal setting registers, and when the microprocessor transfers several consecutive memory blocks to the memory space, But DMA
In order to set the transfer, the transfer mode and the like can be set in the auxiliary register of the DMAC, and the auxiliary register can transfer setting data to the internal setting register.

0010

[Operation] With the above configuration, when several memory blocks are successively transferred to the memory space at once, or at any time during DMA transfer,
Setting information for DMA transfer can be written to the auxiliary register group of the DMAC, and the auxiliary register group transfers the data of the auxiliary register group to the internal setting register when the data transfer of the internal setting register of the DMAC is completed, and sequentially writes the data of the auxiliary register group to the internal setting register. D
MA transfer can be performed, making microprocessor processing more flexible, and when several block transfers are executed in succession, it is possible to improve processing efficiency.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a data transfer processing system according to an embodiment of the present invention. Similar to FIG. 4, a common bus includes a plurality of input/output devices 104 to 106 and memory.
System 102 and DMAC 103 are connected. The DMAC 103 contains an internal setting register 103a, transfer channel reference addresses 305 to 308, and an offset address 30 as shown in FIG.
An internal auxiliary register group 103b is provided that can temporarily store transfer information such as 1 to 304 and transfer mode (channels 1 to 3) and transfer this data to an internal setting register 103a.

Next, the internal blocks of the DMAC 103 will be explained based on FIG. The microprocessor 101 in FIG. 1 transfers the DMA transfer command to the peripheral input/output device 104.
-106 Before specifying, various settings for transfer are made. At this time, the transfer information is written to a vacant position in the auxiliary register group 206 through the window register 207 . Writing to the auxiliary register group 206 is configured so that writing is permitted to only one of the many auxiliary register groups, and at the same time, some kind of control is applied so that it can be determined which channel the setting data is for. This is done by setting a bit. If the DMA transfer has already been completed or is not currently being used, a control signal is sent from the auxiliary register group 206 to the channel identification device 205 . Upon receiving this signal, the data in the auxiliary register is transferred to the main register 2 for the desired transfer channel.
01 to 203.

[0013] Here, main registers 201 to 203
is a group of internal setting registers for setting a transfer mode for setting a reference address (base address), offset address (number of transfer bytes), transfer mode, etc. of a transfer channel corresponding to each input/output device. At this time, main registers 201 to 20, which are a group of internal setting registers,
3 may be setting data for any transfer channel. In other words, when the information of each transfer channel is transferred to the internal setting register, the channel selection device 204 selects the DREQ from the input/output device of the corresponding channel.
Control is now possible only for the signal, and conventional transfer will be resumed. In this way, the main registers 201 to 203 in the DMAC do not need to continue to be setting registers for each channel, and the auxiliary register group 206
The structure is such that the transfer channel (input/output channel) can be determined at the time when data is transferred from the auxiliary register group 206. As a result, only DREQ for the corresponding transfer channel is handled.

As described above, by having the auxiliary register group 206, which is not present in the conventional DMAC, it is possible to specify DMA transfer setting data to the microprocessor at any time, and when transferring several memory blocks, It is possible to provide flexibility in microprocessor processing, such as being able to perform transfer settings all at once.

[0015]

As described above, according to the present invention, the function of the DMAC that controls direct data transfer between a large number of input/output devices connected to a common bus and the memory system is enhanced, and the microprocessor processing can be made more flexible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data transfer processing system according to an embodiment of the present invention.

FIG. 2 is a block diagram inside a DMAC in a data transfer processing system according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating setting information in a memory space.

FIG. 4 is a block diagram of a conventional data transfer processing system.

[Explanation of symbols]

101 Microprocessor 102
Memory system 103
DMAC 103 a Internal setting register 103 b
Auxiliary register group 104 - 106 Input/output device 107 CPU bus 108 DMA bus 109, 110 Address bus 201 - 20
3 Main register for transfer mode setting (internal setting register) 204 Channel selection device 205
Channel identification device 206
Auxiliary register group 207 Window register 208 Data bus 209 DREQ for each channel
, DACK signal

Claims (1)

[Claims] 1. An input/output device connected to a plurality of input/output channels and a memory system are connected to a common transmission bus, and direct data transfer between the memory system and the input/output device is performed. Direct memory access controller (DMA) controls direct data transfer.
This is a data transfer processing system carried out by the DMAC (referred to as C), which has a group of auxiliary registers for temporarily storing setting data in addition to internal setting registers in the DMAC, and further includes:
When transferring several consecutive blocks of memory to memory space, the microprocessor never
In order to set MA transfer, the DMAC has a means for setting the transfer mode etc. in the auxiliary register group, and a means for the auxiliary register group to transfer setting data to the internal setting register. A data transfer processing system configured to resume transfer of the next memory block in sequence after the data transfer between them is completed.