JPH04330765A - Dielectric isolated substrate and manufacture thereof and semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable a filler to be deposited in dividing trenches for dividing a single crystal silicon wafer into multiple element formation regions. CONSTITUTION:Isolation trenches 20 are formed around respective element formation regions 20 in the state wherein a single crystal silicon regins 24 are left in the positions corresponding to the four corners of respective element formation regions 20 out of the regions around the regions 20 formed on a single silicon wafer 10 so that polycrystal silicons 34 may be deposited in the isolation trenches 30.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a dielectric isolation substrate.
In particular, it relates to a dielectric isolation substrate in which a single crystal silicon wafer formed on a support is divided into a plurality of element forming regions by an insulating film, a method for manufacturing the same, and a semiconductor integrated circuit device formed using the dielectric isolation substrate. .

0002

2. Description of the Related Art LSIs are composed of a large number of semiconductor elements integrated on a substrate. Among these LSIs, high voltage withstand voltages ranging from several tens of volts to several hundred volts between elements are
A dielectric isolation substrate is used as a substrate because it is necessary to completely isolate each semiconductor element with an insulating film such as an oxide film. When forming a dielectric isolation substrate, a single crystal silicon wafer is bonded to the surface of a support made of polycrystalline silicon via a dielectric film, and a plurality of semiconductor formation regions are formed on this single crystal silicon wafer. It has been adopted. However, conventional dielectric isolation substrates have had the problem that warpage and distortion occur in the substrate due to the difference in thermal expansion coefficients between single crystal silicon and polycrystalline silicon. Therefore, as described in Japanese Patent Application Laid-open No. 61-59852, it has been proposed that the support is made of single-crystal silicon and a single-crystal silicon wafer is bonded to this support via a dielectric film. There is. However, in the case of this structure, when forming multiple element formation regions on a single crystal silicon wafer, separation grooves are formed around the element formation areas, and polycrystalline silicon is filled into these separation grooves through an insulating film. This configuration has the disadvantage that it takes a lot of time to deposit polycrystalline silicon into the separation grooves and to flatten the surface of the single-crystal silicon wafer. That is, if the width of the isolation trench is narrowed, it becomes difficult to form the isolation trench, and conversely, if the width of the isolation trench is made wide, it takes time to deposit polycrystalline silicon within the isolation trench. Furthermore, among the isolation grooves formed around each element formation area, the grooves corresponding to the four corners of each element formation area are wider than the other isolation grooves, so there are multiple grooves in the center of the grooves corresponding to each of the four corners. Recesses may be formed when depositing crystalline silicon. In order to fill this recess, a large amount of polycrystalline silicon must be deposited in other parts, and it will take time to remove the polycrystalline silicon in a later process. Therefore, as described in Japanese Patent Application Laid-Open No. 1-187944, pillars are placed in the center of each region of the isolation trench corresponding to the four corners of the element formation region, and polycrystalline silicon is deposited within the isolation trench. In this case, a method has been proposed in which recesses are prevented from being formed in isolation grooves corresponding to the four corners of the element formation region.

0003

[Problems to be Solved by the Invention] However, in a structure in which a pillar is placed in the center of a region where isolation grooves intersect, it is difficult to place a pillar in a device because isolation grooves in semiconductor integrated circuits are usually very fine, several μm or less. Even if the pillars are formed separately from the formation region, the pillars are likely to be damaged during the subsequent cleaning process, and there is a problem that the yield when depositing polycrystalline silicon or the like in the separation grooves is reduced. Particularly in power ICs that handle high voltage and large current, the number of isolation grooves is several 1.
This problem becomes more pronounced from a depth of 0 μm. In addition, placing a pillar made of semiconductor material at the center of the area where the separation grooves intersect requires precision processing of several μm, and due to precision issues, it is difficult to maintain a uniform spacing of the separation grooves within the wafer. Have difficulty. Also, T is used as a separation groove.
A method of forming a T-shaped isolation trench has been proposed, but the method of forming a T-shaped isolation trench reduces the degree of freedom in the layout of the IC element, making it difficult to reduce the IC chip size. It becomes difficult. An object of the present invention is to provide a dielectric separation substrate that can uniformly deposit a filler in separation grooves for dividing a single crystal silicon wafer into a plurality of element forming regions, a method for manufacturing the same, and a dielectric separation substrate using the dielectric separation substrate. It is an object of the present invention to provide a semiconductor integrated circuit device that has improved performance.

0004

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a first substrate in which a single crystal silicon wafer bonded to a support via an insulating film is divided into a plurality of regions, Each region is formed as a polygonal element forming area, and other elements are formed in the area around each element forming area except for each area in the approximate center of the corner corresponding to each corner of each element forming area. Isolation trenches are formed to indicate boundaries with the regions, a filler is deposited in each isolation trench via an insulating film, and each element formation region is electrically insulated from each other with the insulator in the isolation trench in between. The dielectric isolation substrate is configured such that the central region is formed as a single crystal silicon region separated from each element forming region.

[0005] As a second substrate, a single crystal silicon wafer bonded to a support via an insulating film is divided into a plurality of element formation areas, and four corners of the periphery of each element formation area correspond to the four corners of each element formation area. A separation groove is formed in the area excluding each area in the approximately central part, which indicates the boundary with other element formation areas.
A filling is deposited in each isolation trench via an insulating film, and each element forming region is electrically insulated from each other with the isolation trench in between.
The dielectric isolation substrate is configured such that the central region is formed as a single crystal silicon region separated from each element forming region.

[0006] As the third substrate including the first or second substrate, the insulating filler constitutes a dielectric isolation substrate made of a silicon oxide film.

[0007] As a first manufacturing method, a single crystal silicon wafer is bonded onto a support via an insulating film, an insulating film is formed on the surface of the single crystal silicon wafer, and a single crystal silicon wafer is formed as a pattern in which this insulating film is left. A silicon wafer is divided into a plurality of regions, each region is formed into a polygonal element formation region, and each corner region corresponding to each corner of each element formation region is divided into polygonal element formation regions. A mask pattern is formed to connect each element forming area to each other through the mask pattern, and a pattern for peeling off the insulating film is formed by removing the corner area corresponding to each corner of each element forming area among the area and the periphery of each element forming area. A peeling pattern is formed in the etched area to indicate the boundary with other element formation areas, and the insulating film on the surface of the single crystal silicon wafer is etched according to each pattern. An isolation groove is formed in the area where the film has been peeled off, and after removing the insulating film on the surface of the single crystal silicon wafer, an insulating film is formed on the wall of each isolation groove. This method employs a method of manufacturing a dielectric substrate in which the single-crystal silicon wafer is electrically isolated from each other through the trenches, a filler is deposited in each isolation trench, and the surface of the single-crystal silicon wafer is then flattened.

In the second manufacturing process, a single-crystal silicon wafer is bonded to a support via an insulating film, an insulating film is formed on the surface of the single-crystal silicon wafer, and a pattern in which this insulating film is left is formed using a single-crystal silicon wafer. The wafer is divided into a plurality of element formation areas, and a mask pattern is formed to connect the element formation areas to each other through areas corresponding to the four corners of each element formation area around the periphery of each element formation area, and an insulating film is formed. As a peeling pattern, a peeling pattern is formed around the area and each element forming area excluding each area corresponding to the four corners of each element forming area and indicating the boundary with other element forming areas. , etching the insulating film on the surface of the single-crystal silicon wafer according to each pattern, forming a separation groove in the area where the insulating film has been peeled off of the etched single-crystal silicon wafer, and etching the insulating film on the surface of the single-crystal silicon wafer. After removing, an insulating film is formed on the wall of each dividing groove,
By forming this insulating film, each element formation region is electrically isolated from each other via the insulating film, and then a filler is deposited in each isolation trench, followed by a dielectric material that flattens the surface of the single-crystal silicon wafer. This method adopts the manufacturing method of the substrate.

[0009] As the first device, the first, second or third
This is a semiconductor integrated circuit device in which a semiconductor element is formed on a dielectric isolation substrate.

The second device is a semiconductor integrated circuit device in which a semiconductor element is formed on a dielectric isolation substrate manufactured by the first or third method.

[0011]

[Operation] According to the above means, each element is formed in each area approximately at the center of the corner corresponding to each corner of each element forming area or each area approximately at the center corresponding to the four corners of each element forming area. Since a single crystal silicon region is formed that is separated from the other regions, all isolation trenches can be completely filled with a constant deposition amount, which reduces manufacturing time and reduces the amount of insulating fill deposited. It can be reduced.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a process diagram for explaining a method for manufacturing a dielectric isolation substrate, and FIG. 2 is a plan view of a main part of the dielectric isolation substrate manufactured by the manufacturing method shown in FIG. In FIGS. 1 and 2, when manufacturing the dielectric isolation substrate,
First, a single crystal silicon wafer 10 is prepared (a). Next, a support 12 made of a single crystal silicon wafer is prepared, and insulating films 14 and 16 made of silicon oxide are formed on the front and back surfaces of the support 12 to a thickness of about 2 μm. Thereafter, the support 12 and the single crystal silicon 10 are pasted together via the insulating film 16, and a high temperature heat treatment is applied to them to bond the two silicon wafers (b). Next, single crystal silicon 10
By removing unnecessary portions of the single crystal silicon 10 by polishing or etching, the single crystal silicon 10 is made into a single crystal silicon thin film having a thickness of approximately 30 μm, which is necessary for forming a semiconductor element having desired electrical characteristics. After this, on the surface of the single crystal silicon 10,
In the subsequent etching process, an oxide film 18 of about 2 μm is formed to mask the surface of the single crystal silicon 10 (c)
. When forming this oxide film 18, as shown in (C), the single crystal silicon 10 is divided into a plurality of element formation regions, and the four corners of each element formation region are connected to a connecting part. 22, forming a mask pattern 26 connected via the single crystal silicon region 24, and forming the oxide film 1
A peeling pattern 28 indicating a boundary between each element forming region 20 is formed as a pattern for peeling off the wafer 8 . This peeling pattern 28 is formed when forming the separation grooves so that the width of each separation groove is constant.

Next, an etching process is started, and the oxide film 18 is etched.
The parts corresponding to the peeling patterns 28 are removed, leaving the parts corresponding to the mask patterns 26, and at this time, the element forming regions 20 are connected to each other via the connecting parts 22 and the single crystal silicon regions 20. After this, using a method such as dry etching, the area corresponding to the peeling pattern 28 is etched to a depth of approximately 3.
A separation groove 30 of 0 μm is formed (d). Furthermore, at this time, the oxide film 18 is removed from the surface of the single crystal silicon 10. The state at this time is shown in (D). At this time, each isolation trench 30 is formed with the same width, and the four corners of each element formation region are connected via the connecting portion 22 and the single crystal silicon region 24. In other words, each separation groove does not cross each other,
Single crystal silicon region 24 around the element formation region 20
A separation groove 30 is formed except for the area.

Next, an insulating film 32 made of silicon oxide is formed to a thickness of approximately 2 μm on the wall surface of each isolation trench 30 (e). At this time, the width of the isolation trench 30 becomes narrow due to the formation of the oxide film 32, and the periphery of each element formation region 20 and the periphery of the single crystal silicon region 24 is eroded due to the oxidation action of the oxide film 32. are electrically isolated from each other via an insulating film 32. That is, since the width of the connecting portion 22 is narrow, it is eroded by the oxidation action of the insulating film 32, and the single crystal silicon region 24 is electrically isolated from each element forming region 20 via the insulating film 32. Since the single crystal silicon region 24 is connected to each element formation region 20 via the connecting portion 22 and then separated into each element formation region 20, it will not break when separated from each element formation region 20. do not have. When the insulating film 32 is formed on the wall surface of the isolation trench 30 and the surface of each element forming region 20, the surface of the single crystal silicon 10 becomes as shown in (E). After this, polycrystalline silicon 3 is formed in the separation trench 30 by a vapor phase growth (CVD) method.
Deposit 4 (f). In this case, since all the isolation trenches 30 are formed to have the same dimensions, polycrystalline silicon 34 can be uniformly deposited in all the isolation trenches 30 in a fixed deposition time. That is, since single-crystal silicon regions 24 are formed at the four corners of each element formation region 20, polycrystalline silicon 34 can be deposited without forming a recess in isolation trench 30. Thereafter, unnecessary polycrystalline silicon 34 and insulating film 32 formed on the surface of single crystal silicon 10 are removed to make the surface of single crystal silicon 10 flat (g), as shown in FIG. A dielectric isolation substrate 36 is formed.

In the above embodiment, each element forming region 20
As shown in FIGS. 3 and 4, the single crystal silicon 10 is divided into three element forming areas 20, and each element forming area is It is also possible to form a separation trench 30 and a single crystal silicon region 24 between the regions 20, and as shown in FIGS. 5 and 6, the single crystal silicon 10 can be divided into two element formation regions 20, and A separation groove 30 is formed at the boundary of the element formation region 20 and the single crystal silicon region 24
It is also possible to form In this case, a plan view of the main part with each dielectric isolation substrate formed is shown in FIGS. 4 and 6. In each of the embodiments described above, the isolation grooves 30 are formed without intersecting with each other, as in the embodiments described above, so that each isolation groove 30 can be uniformly filled with polycrystalline silicon 34. Further, as in the embodiment described above, the amount of deposited polycrystalline silicon 34 can be reduced, and the deposition time and the dry etching time in the subsequent dry etching process for removing polycrystalline silicon can be shortened.

Further, in each of the embodiments described above, polycrystalline silicon 34 was used as the material for filling the isolation trenches, but other materials such as silicon oxide film may also be used.

[0017]

[Effects of the Invention] As explained above, according to the present invention,
When forming multiple element formation regions on a single-crystal silicon wafer, the width of the isolation grooves can be reduced by forming single-crystal silicon regions between each isolation groove without crossing the separation grooves that serve as the boundaries of each element formation area. can be made to have the same width, the filling can be deposited uniformly in the separation groove, the amount of deposited filling can be reduced, and the time for depositing the filling and the time for removing the filling can be reduced. This can contribute to improving production costs. Further, since the degree of freedom in layout of the elements constituting the semiconductor element is not lost, it is possible to prevent the chip size of the semiconductor element from increasing.

[Brief explanation of drawings]

FIG. 1 is a process diagram for explaining a method for manufacturing a dielectric isolation substrate.

FIG. 2 is a plan view of essential parts of a dielectric isolation substrate.

FIG. 3 is a plan view of a main part of a dielectric isolation substrate showing another embodiment of the present invention.

4 is a plan view of main parts showing the state after completion of FIG. 3; FIG.

FIG. 5 is a plan view of main parts showing still another embodiment of the present invention.

FIG. 6 is a plan view of main parts showing the state shown in FIG. 5 after completion.

[Explanation of symbols]

10 Single crystal silicon wafer 12 Support 14, 16 Insulating film 18 Oxide film 20 Element formation area 22 Connecting part 24 Single crystal silicon region 26 Mask pattern 28 Peeling pattern 30 Separation groove 32 Insulating film

Claims (7)

[Claims] 1. A single-crystal silicon wafer bonded to a support via an insulating film is divided into a plurality of regions, each region is formed into a polygonal element formation region, and a portion of the periphery of each element formation region is divided into a plurality of regions. Isolation grooves are formed in the area excluding each area at the approximate center of the corner corresponding to each corner of each element formation area to indicate a boundary with other element formation areas. A filling is deposited, and each element forming region is electrically insulated from each other with an insulator in the isolation trench between them, and the central region is formed as a single crystal silicon region separated from each element forming region. Dielectric isolation substrate. 2. A single crystal silicon wafer bonded to a support via an insulating film is divided into a plurality of element formation regions,
Isolation grooves are formed around each element formation area, except for the approximately central areas corresponding to the four corners of each element formation area, and are formed to indicate boundaries with other element formation areas. Filling is deposited through the film, each element forming region is electrically insulated from each other with a separation groove in between, and the central region is formed as a single crystal silicon region separated from each element forming region. Dielectric isolation substrate. 3. The dielectric isolation substrate according to claim 1, wherein the insulating filling is composed of a silicon oxide film. 4. A single-crystal silicon wafer is bonded onto a support via an insulating film, an insulating film is formed on the surface of the single-crystal silicon wafer, and a plurality of single-crystal silicon wafers are bonded to form a pattern in which this insulating film is left. Each region is divided into regions, each region is formed into a polygonal element formation region, and each element formation region is formed through a corner region corresponding to each corner of each element formation region out of the periphery of each element formation region. Form a mask pattern to connect the two to each other, and as a pattern to peel off the insulation film
A peeling pattern is formed around each element forming area except for each corner area corresponding to each corner of each element forming area to indicate a boundary with other element forming areas, and according to each pattern, After etching the insulating film on the surface of the single-crystal silicon wafer, forming separation grooves in the areas of the etched single-crystal silicon wafer where the insulating film has been removed, and removing the insulating film on the surface of the single-crystal silicon wafer. An insulating film is formed on the wall surface of each isolation trench, and by forming this insulating film, each element formation region is electrically isolated from each other via the insulating film, and then a filler is deposited in each isolation trench, and then a filler is deposited in each isolation trench. A method for manufacturing a dielectric substrate that flattens the surface of a crystalline silicon wafer. 5. A single-crystal silicon wafer is bonded onto a support via an insulating film, an insulating film is formed on the surface of the single-crystal silicon wafer, and a plurality of single-crystal silicon wafers are bonded as a pattern in which this insulating film is left. A pattern for separating the insulating film by forming a mask pattern that divides the device forming regions and connecting the device forming regions to each other through regions corresponding to the four corners of each device forming region out of the periphery of each device forming region. A peeling pattern is formed around the area and each element forming area excluding each area corresponding to the four corners of each element forming area to indicate a boundary with another element forming area,
The insulating film on the surface of the single-crystal silicon wafer is etched according to each pattern, and separation grooves are formed in the regions of the etched single-crystal silicon wafer where the insulating film has been peeled off. After the removal, an insulating film is formed on the wall surface of each isolation trench, and by forming this insulating film, each element formation region is electrically isolated from each other via the insulating film, and then a filler is deposited in each isolation trench, Next is a method for manufacturing a dielectric substrate that flattens the surface of a single-crystal silicon wafer. 6. A semiconductor integrated circuit device comprising a semiconductor element formed on the dielectric isolation substrate according to claim 1, 2 or 3. 7. A semiconductor integrated circuit device comprising a semiconductor element formed on a dielectric isolation substrate manufactured by the method according to claim 5 or 6.