JPH04337657A - Lead frame for semiconductor device - Google Patents

Abstract

PURPOSE:To enable heat resistance of a surface treatment film to be improved by providing an Ni plating layer on an entire surface of a lead frame, a Pd plating layer at an inner-lead part and an outer-lead portion at its upper layer, and further an Au plating layer at a the inner-lead part and the outer-lead part at its upper layer. CONSTITUTION:An Ni plating layer 9 is provided on an entire surface of a lead frame 1. The Ni plating layer 9 is provided for preventing diffusion and corrosion. A Pd or Pd alloy plating layer 15 is provided on an upper layer of the Ni plating layer 9. This Pd or Pd alloy plating layer 15 is provided at an inner-lead part 5 and an outer-lead part 3. An Au plating layer 16 is provided on the Pd or Pd alloy plating layer 15. This Au plating layer 16 is provided at the inner-lead part 5 and the outer-lead part 3, thus enabling heat resistance at the time of assembly of semiconductor to be improved at a low cost.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to lead frames for semiconductor devices.

0002

2. Description of the Related Art A lead frame for a semiconductor device generally includes a semiconductor chip mounting portion 7, an inner lead portion 5, an outer lead portion 3, an outer frame portion 2, etc., as shown in FIG.

As shown in FIG. 5, the method for manufacturing a semiconductor package involves bonding a semiconductor chip 13 onto a semiconductor chip mounting portion 7, and then depositing an Ag plating layer on the electrode portion of the semiconductor chip and the tip portion 6 of the inner lead portion 5. 10 is wire bonded (W/
B) Do. After that, it is molded with mold resin 14. Furthermore, in order to improve the ease of mounting the semiconductor package on a printed circuit board, after cutting the outer frame part 2 of the lead frame, a solder plating layer (Sm-Pb alloy plating layer) is applied to the part including the outer lead part 3. ) 11 to make a finished product.

However, in such a process, the outer lead portion is dipped for 20 seconds during hot-dip plating after assembly.
Due to heating above 0°C, cracks may occur in the resin mold due to thermal shock. Furthermore, this method has poor productivity and is high in cost. Furthermore, the flux used during hot-dip plating contaminates the semiconductor package, outer leads, etc., causing a reduction in the reliability of the semiconductor. In order to solve such problems,
In recent years, a technique has been studied in which palladium (Pd), which has good W/B properties and solderability, is provided as a surface treatment film in advance at the lead frame stage.

[0005]

[Problems to be Solved by the Invention] In the method of providing a solder plating layer on the outer lead portion after semiconductor assembly, there are problems such as thermal shock due to heating during hot-dip plating, cracking of the resin mold, and damage to the semiconductor package and outer lead portion due to the use of flux. Decrease in moisture resistance due to contamination was unavoidable. Furthermore, the finished product plating process takes up most of the time it takes for semiconductor manufacturers to ship semiconductors, which has been an obstacle to shortening product delivery times. In addition, when considering the improvement of productivity in the semiconductor assembly process, finished product plating relies on outsourcing, which makes it impossible to deal with integrated automation of the line, which poses problems in terms of reducing labor costs and costs. There were many.

[0006] In advance, Pd is applied to the outermost surface of the lead frame.
Since the lead frame provided with the plating layer has good W/B properties and solderability because of its single color, the plating process can also be simplified. Therefore, recently, it has become a technology that is attracting attention as an alternative to lead frames that are pre-plated with Ag plating and solder plating. However, due to the high price of Pd, it must be plated thinly, and the Pd plating film itself has many pinholes, and after heating to around 300 degrees Celsius during semiconductor assembly, oxidation of the base metal and Pd itself occurs. W/
There was a problem that the properties of the plating film, such as B properties and solderability, deteriorated.

[0007] The present invention makes it possible to significantly improve the heat resistance of the surface-treated film and obtain excellent properties.
The purpose of the present invention is to provide a lead frame for a semiconductor device that can provide a high-quality surface treatment film at a lower price than when using a single layer.

[0008]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a lead frame for a semiconductor device having an inner lead portion and an outer lead portion, wherein the entire surface of the lead frame is coated with Ni-based plating. has a layer,
A lead frame for a semiconductor device, which has a Pd or Pd alloy plating layer on at least the inner lead portion and the outer lead portion of the upper layer, and further has an Au plating layer on at least the inner lead portion and the outer lead portion of the upper layer. is provided.

The present invention will be explained in more detail below.

FIG. 1 is a sectional view of a package using a lead frame for a semiconductor device showing one embodiment of the present invention. The shape of the lead frame of the present invention is similar to that shown in FIG. 4, and has an inner lead part 5 and an outer lead part 3.

[0011] The present invention has a Ni-based plating layer 9 on the entire surface of the lead frame 1 having the shape shown in FIG. .

The lead frame material is generally made of C.
Examples include, but are not limited to, u alloys and Fe alloys. The Ni-based plating layer 9 is provided to prevent diffusion and improve corrosion resistance. Generally, matte or glossy plating is performed using a Watt bath, and the layer thickness may be about 0.1 to 5 μm. The layer thickness may be more than 5 μm, but if it is more than 10 μm, there is a risk of cracks occurring during bending.

A Pd or Pd alloy plating layer 15 is provided on the Ni-based plating layer 9 . This Pd or Pd alloy plating layer 15 is applied to at least the inner lead portion 5.
It is provided in the outer lead portion 3 to impart W/B properties and solderability, but since it is expensive, it is advantageous not to make the layer thick too much, and it is sufficient if it is 0.01 μm or more. This P
d or Pd alloy plating can be provided by a known method.

In the present invention, an Au plating layer 16 is provided on the Pd or Pd alloy plating layer 15. This Au plating layer 16 is provided at least on the inner lead portion 5 and the outer lead portion 3. This makes it possible to significantly improve heat resistance during semiconductor assembly at low cost. If the thickness of the Au plating layer 16 is 0.01 μm or more, excellent W/B properties and solderability can be maintained even after semiconductor assembly.

[0015]

EXAMPLES The present invention will be specifically explained below based on examples.

(Example 1) Matte Ni plating was provided on the entire surface of a Cu alloy lead frame to a thickness of 0.5 μm. Thereafter, Pd plating was applied to the inner lead portion and outer lead portion of the lead frame to a thickness of 0.05 μm, respectively. Furthermore, Au plating was performed on the upper layer to a thickness of 0.02 μm. Note that each plating thickness was measured using a fluorescent X-ray film thickness meter. The plating conditions are as follows. Matte Ni plating (Wat bath) NiSO4 ・6H2 O 250g/
l Temperature 55℃ NiC
l2 ・6H2 O 50g/l Current density 4A/dm2 H3 BO3
50g/l
Anode Ni plate Pd plating solution: Paradex HS (manufactured by Tanaka Kikinzoku Kogyo Co., Ltd.) Metal Pd concentration 10 g/l Current density 1
A/dm2 temperature 6
0℃ Anode Platinum plated tin plate Au plating solution: Temperex 702 (
(manufactured by Tanaka Kikinzoku Kogyo Co., Ltd.) Metallic Au concentration
15g/l temperature
70℃ current density
0.5A/dm2 anode
Platinum plated titanium plate

Next, for comparison, the same sample as in Example 1 which had been subjected to Pd plating was used. At this time, the Pd plating thickness was 0.05
μm (Comparative Example 1) and 0.5 μm (Comparative Example 2) (see Table 1).

(Example 2) After providing 0.5 μm of bright Ni plating on the entire surface of the Fe alloy lead frame, Pd-Ni
Plating is performed to a thickness of 0.1 μm, and further Au plating is applied to a thickness of 0.1 μm.
02 μm. Each plating thickness was measured using a fluorescent X-ray film thickness meter. In addition, the plating conditions are as follows. Bright Ni plating (Wat bath) NiSO4 ・6H2 O 250g/
l Temperature 50℃ NiC
l2 ・6H2 O 51g/l Current density 4A/dm2 H3 BO3
50g/l
Anode Ni plate #61 (secondary brightener)
5ml/l (manufactured by Shobara Yugilite)
#63 (primary brightener) 10ml/
l (manufactured by Shobara Yugilite Co., Ltd.) Pd-Ni plating solution Balnic 816
Temperature 30℃ (NE
(manufactured by Chemcat) Metallic Pd concentration 10
g/l Current density 1A/dm2
Metallic Ni concentration 6g/l
Anode Platinum-plated titanium plate Au plating solution Ourobel UP-24
Current density 1A/dm2 (
(manufactured by Nippon Leeronal Co., Ltd.) Metallic Au concentration
8g/l Anode Platinum-plated titanium plate Temperature 70℃

Next, for comparison, the Pd of Example 2
-The one that had been subjected to Ni plating was used. At this time Pd
-Ni plating thickness is 0.1 μm (Comparative Example 3)
and 1.0 μm (Comparative Example 4) (see Table 2). In addition, as Comparative Example 5, the Pd-Ni plating of Example 2 was not provided, and Au plating was directly applied to a thickness of 0.02 μm on the Ni plating.
I used what was provided. The layer numbers in Tables 1 and 2 are shown in Figure 2.
It was shown to.

The characteristics of the lead frame of the present invention thus obtained and Comparative Examples 1 to 5 were compared. The comparison items are 30 samples that simulate the thermal history of the pellet attaching process during semiconductor assembly.
These are a W/B test and a solderability test after heating at 0° C. for 30 seconds. In the W/B test, the ratio of the number of Au wires crimped to the total number of shots was expressed as the W/B crimping rate. The solder wettability test uses a digital solder graph manufactured by Tamura Seisakusho, immerses the sample in a eutectic solder bath kept at 230 ± 5 degrees Celsius, measures the zero crossing time (solder wetting time), and calculates the time (S). It was expressed as In addition, at this time 25
wt% WW rosin flux was used. The results are shown in Table 3. Further, Table 4 shows a comparison of plating chemical costs when providing the minimum necessary Au and Pd plating to satisfy the characteristics. A, B, C, and D in Table 4 indicate manufacturers, and the total plating chemical costs are expressed as a ratio, with the value of D being 1. Furthermore, regarding the solder wettability of Example 1 and Comparative Example 2,
The temperature was varied by 25°C in the range of 300 to 450°C,
The solder wetting time was measured for the sample heated for 30 seconds. The results are shown in Figure 3.

[0021]

[0022]

[0023]

[0024]

From Table 3, the lead frame of the present invention has 30
The W/B compression bonding rate after heating at 0° C. for 30 seconds was 100%, which was excellent. However, in Comparative Examples 1 to 5, the W/B crimping rate was all 0%.
Therefore, a decrease in W/B properties was observed. In addition, regarding solder wettability, the lead frame of the present invention
Even after heating for seconds, the zero crossing time was good, being within 1 second, whereas in the comparative example, the value of the zero crossing time increased and the solderability deteriorated. Further, from FIG. 3, Example 1 had good solder wettability even after heating at 425° C. for 30 seconds, whereas Comparative Example 2 had poor solder wettability when heated at over 300° C. From the above, it was found that heat resistance was improved by 100° C. or more by providing a thin Au plating on the Pd layer.

[0026]

[Effects of the Invention] Since the present invention is configured as described above, it is possible to significantly improve the heat resistance of the lead frame surface treatment film, and to maintain stable W even after semiconductor assembly. /B properties and solderability were obtained. Furthermore, the two-layer structure in which Au is provided on Pd has the advantage that the cost of plating chemicals is lower overall than when the characteristics are satisfied only with Pd.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a package using a lead frame for a semiconductor device showing one embodiment of the present invention.

FIG. 2 is a cross-sectional view showing each layer number of the example lead frame.

FIG. 3 is a graph showing the relationship between each heating temperature and zero crossing time.

FIG. 4 is a plan view showing an example of a conventional lead frame.

FIG. 5 is a cross-sectional view showing an example of a conventional semiconductor package.

[Explanation of symbols]

1 Lead frame 2 Outer frame part 3 Outer lead part 4 Dam bar 5 Inner lead part 6 Tip of inner lead part 7 Semiconductor chip mounting part 8 Pilot hole 9 Ni-based plating layer 10 Ag plating layer 11 Sn-Pb alloy plating layer 12 Au wire 13 Semiconductor chip 14 Mold resin 15　Pd or Pd alloy plating layer 16 Au plating layer 17 Lead frame material

Claims (1)

[Claims] 1. A lead frame for a semiconductor device having an inner lead portion and an outer lead portion, the lead frame comprising:
The lead frame has a Ni plating layer on the entire surface, a Pd or Pd alloy plating layer on at least the inner lead portion and the outer lead portion of the upper layer, and an Au plating layer on at least the inner lead portion and the outer lead portion of the upper layer. A lead frame for a semiconductor device characterized by having a plating layer.