JPH04313882A - Record control system for memory card - Google Patents

Abstract

PURPOSE:To provide a storage control system for a memory card being contrived the holding of the life of the memory card using an EEPROM and the simplification of the system structure. CONSTITUTION:The data region 17 of the EEPROM is divided into a storage unit consisting of a cluster 18 being a minimum control region of an image data recording and a header 20 storing a control information of respective data and the header 20 is written at a data writing time to the cluster 18. In the case of the data read-out, the data of the cluster 18 is read-out by retrieving each header 20. At the data writing time, the rewriting of the control region, namely the rewriting accompanied with the erase is not present, so such an inconvenience does not occur that the rewriting number of the control region is larger than it of the data region and the life of the memory card can be held. Besides a large capacity of memory at the erase time at the system side can be omitted and the processing step can be simplified.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage management system for a memory card that stores data such as image data and character data, and more particularly to a storage management system for a memory card equipped with an EEPROM.

0002

[Prior Art] In recent years, semiconductor memories have been used in place of floppy disks as media for recording image data in electronic still cameras and character data in word processors.
Smaller memory cards have come into use.

Conventionally, such memory cards have used static RAM (hereinafter referred to as SRAM) which can perform high-speed reading and writing. However, since this SRAM is a volatile semiconductor memory, it requires a backup battery inside the memory card, and when storing large amounts of data such as image data, it becomes expensive and the memory The problem was that the card prices were high.

Therefore, in recent years, EEP, which is a non-volatile semiconductor memory that is inexpensive and does not require a backup battery, has been developed.
The use of ROM (electrically erasable/rewritable read-only memory) in memory cards is being considered. This EEPROM has an excellent storage life of more than 10 years without batteries, and in recent years has come to have read and write speeds comparable to SRAM, and is about one-fourth the price of SRAM. being developed.

By the way, various memory card storage management systems have been proposed in order to efficiently read and write data stored in the storage medium of a memory card. For example, there is a storage management system for a memory card disclosed in Japanese Patent Application No. 1-317796, and a storage management system applied to an image recording and reproducing apparatus disclosed in Japanese Patent Application No. 1-326118.

[0006] In these storage management systems, the storage area of the recording medium is divided into a data storage area for storing data, and
It was divided into a management information storage area for storing this management information. In this method, when reading data, the management information is read out from the management information storage area and referenced, and the corresponding address in the data storage area is accessed and the data is read out. In addition, when writing data, the management information is read from the management area and referenced to search for an empty area in the data area, and the data is written to the address of the desired empty area, and the data is managed after writing the data. The information was rewritten and the rewritten management information was stored in the management area of the recording medium.

[0007]

[Problem to be Solved by the Invention] However, in conventional storage management systems, management information for multiple data is written in a management area at once, so the management information must be rewritten every time data is written. , the number of times the management area is rewritten is greater than the number of times the data area is rewritten. Therefore, EEPR has a limit on the number of rewrites.
When OM is employed in a memory card, the lifespan of the memory card is limited by the number of times the management area can be rewritten, resulting in a problem that the lifespan of the memory card becomes extremely short. In particular, in a block erase type EEPROM, even though the data area is in a usable state where the number of rewrites has not been reached, the management area reaches the rewrite limit first, and although data is written, the management information There was a problem in that the data could not be written and the data could not be read, resulting in unnecessary processing.

Furthermore, in the conventional storage management system, EE
When PROM is used as a memory card, EEPROM
Since deletion is performed during rewriting, the management information is temporarily stored on the system side, and then the management area is deleted. During this time, the management information stored on the system side is rewritten, and then this management information is transferred to the data. Along with the writing, writing to the EEPROM is performed. Therefore, when EEPROM is used in the conventional storage management method, there is a problem in that the process of storing and rewriting management information on the system side becomes complicated, and it also places a burden on system control. . In this case, a problem arises in that the circuit configuration on the system side becomes complicated, such as by providing a backup memory with the same capacity as the EEPROM or the same capacity as the management area on the system side, and providing a circuit for rewriting the memory. In particular, flash type EEP that performs all erasing when rewriting
When a ROM is used, the main data must also be backed up when rewriting the management information, resulting in a problem of poor processing efficiency.

[0009] The present invention eliminates these drawbacks of the prior art, makes it possible to extend the lifespan of a memory card using EEPROM, and reduces the processing burden on the system side and simplifies the circuit configuration. The purpose of the present invention is to provide a memory card storage management method that allows for the storage management of memory cards.

0010

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention stores management information together with data in a memory card equipped with an electrically erasable and rewritable EEPROM as a storage element. In a memory card storage management system, the storage area of an EEPROM is divided into a plurality of storage areas each having a predetermined storage capacity, and each of these storage areas has a management function for data stored in that storage area. When a header section for storing information is formed and data in each storage area is accessed, the header section for accessing the data is searched and referenced for each storage area. The method is characterized in that information is obtained and, based on this information, each storage area including each header section is accessed.

In this case, it is preferable that each storage area including the header section has the same capacity as the erase unit of the block erase type EEPROM.

[0012] Furthermore, it is preferable to write a data number in the header section at any time to identify the data for each storage area when recording data.

On the other hand, the memory card system of the present invention uses electrically erasable and rewritable EE as a memory element.
In a memory card system that uses a memory card equipped with a PROM as a recording medium, the EEP of the memory card is
The storage area of the ROM is divided into a plurality of storage areas of a predetermined capacity each including a header section in which management information is written, and the system into which this memory card is installed determines the amount of data to be sent to the memory card according to the division in the EEPROM. data amount counting means for counting whether the data storage capacity of each storage area has been reached; and a header writing for writing management information into the header section of each storage area based on the count result of the data amount counting means. It is characterized by comprising a means for loading.

Furthermore, the memory card of the present invention uses electrically erasable and rewritable EEPRO as a storage element.
In the memory card which stores management information along with data, the EEPROM has a storage area divided into a plurality of storage areas each having a predetermined storage capacity including a header section, and is supplied from the system side. The storage area includes a control means for generating a start address selection signal for selecting a start address of the storage area based on the control signal and the address, and increments subsequent addresses based on the start address selection signal.
It is characterized in that data is accessed for each storage area of the storage area.

[0015]

[Operation] According to the memory card storage management system of the present invention, the data area of the EEPROM of the memory card is
For example, it is composed of a storage unit consisting of a cluster, which is the minimum management area for image data, and a header section in which management information for the cluster is written. When writing data, the header sections of other clusters that have already been written are searched in order to find an area where no header section has been written, and then the data is written to that area. Along with this, management information is written in the header section of that area. Thereby, data can be written without erasing the management area.

When reading data, a desired data area is detected by searching the header section, and the data is read out. In this case, data can be retrieved in a shorter time by searching for a data number for data identification.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a memory card record management system according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a diagram showing a schematic configuration of a memory card system according to an embodiment of the present invention. In this figure, a host device 12 is an image recording device such as an electronic still camera, and uses a memory card 10 as a recording medium. The memory card 10 is a flash erase type EEP.
ROM (Electrically Erasable and Rewritable Memory)
is provided as a memory element. The host device 12 includes an interface unit 14 for writing data to the memory card 10 and reading data recorded in the memory card 10.
It is equipped with Interface unit 14 of host device 12
An I/O bus method is adopted in which the memory card 10 and the memory card 10 are connected via a bus 16. For example, J
The 24-pin configuration proposed in the IC memory card guidelines of EIDA (Japan Electronics Industry Promotion Association)
O bus etc. are adopted.

The memory card 10 has a storage area 17 in the format shown in FIG. 1 on an EEPROM chip. The storage area 17 is divided into storage units MU each having a cluster head 20, which is a management area in which management information is written, for each cluster 18, which is the smallest management unit for recording image data. There is. Cluster 1, 2, 3. ．． ．． Normally, image data forming one image is stored respectively, but if it cannot be stored in one cluster, it is stored in two or three clusters as shown in FIG.

Each cluster head 20 has 16
Byte capacity is allocated. The contents include a 2-byte image number ("0000" to "FFFE"), a 1-byte card number, data type, reserve area, next cluster number, etc. When writing image data, the data within one image is written in the order of the smallest cluster number, and when reproducing the image, the image number is specified and the data is read out in the order of the cluster numbers. The next cluster number in the cluster head 20 is used to jump the erase range in a block erase type EEPROM.

When the card 10 is inserted into the host device 12 and the erase button of the host device 12 is pressed, the data area 17 of the EEPROM is erased by flash erase, which erases existing records all at once, or block erase, which erases a portion of the data. Due to the characteristics of EEPROM, in its initial state, each bit is all "1" (FFFF).
" is written. In this embodiment, the cluster 18 into which data is written and the cluster head 20, which is its management area, are simultaneously erased as a storage unit MU. In addition, since the erase range is a divisor of the cluster size, in the case of block erase, there are areas where adjacent block erases overlap as in the conventional example, resulting in a large number of erases, resulting in an increase in EEPR.
Nothing that shortens the life of the OM will occur.

FIG. 2 is a diagram showing functional blocks of the memory card 10 in this embodiment. In this diagram,
The memory card 10 includes a plurality of EEPROM chips 20, 21, each having a data area 17 formed therein, and
A decoder 24 and a 24-bit address counter 26 to which addresses are input from among the data signals D0 to D7 supplied from the host device 12, a read signal RD, a write signal WR, and data from the host device 12 via the bus 16. It has a control decoder 28 to which identification signals A0 and A1 are input.

As shown in FIG. 5, the control decoder 22 receives the write signal WR and the data identification signals A0,
When A1 is input, the control signal generating circuit outputs the start address signal S1 and clock CK to the address counter 26, and outputs the write enable signal WE to the plurality of chips 20, 21, . . . Data identification signals A0 and A1 both indicate input of the lower byte of the address when they are at low level "LL", indicate the middle byte of the address when they are "HL", and indicate the upper byte of the address when they are "LH". , and further indicates data input in the case of "HH".

Address counter 26 outputs address signals A0-17 and decode signal S2 to decoder 24 based on the address of input data signals D0-D7, start address signal S1, and clock CK. Decoder 24 outputs a chip enable signal CE that selects one of the plurality of chips, for example chip 20. The chip 20 is enabled by inputting a chip enable signal, identifies address signals A0 to A17, detects a write command, and writes data sent after the write command to a designated address. Subsequent data writing is performed by incrementing the address at 10 μs intervals. Data is written in units of 8 bits, ie, 1 byte.

In the data read cycle of FIG.
When the control decoder 22 of the memory card 10 receives the read signal RD and the data identification signals A0 and A1, it outputs the start address signal S1 and the clock CK.
is output to the address counter 26, and an out enable signal OE is output to a plurality of chips. Address counter 26 includes input addresses D0 to D7, start and
Address signals A0 to A17 and a decode signal S2 are output to the decoder 24 based on the address signal S1 and clock CK. The decoder 24 receives a chip enable signal CE that selects one of the plurality of chips, for example, the chip 20.
Output. The chip 20 is enabled by inputting a chip enable signal, identifies address signals A0 to A17, detects a read command, and then outputs a read signal R.
Data D0 is sent from the specified address according to the timing of D.
~D7 are read continuously.

In the card erase mode shown in FIG. 7, the memory card 10 receives the write signal WR and erase commands D0 to D.
When 7 is input, erasing is performed in chip units in 9.5 ms.

FIG. 3 is a block diagram showing the configuration of the interface section 14 provided in the host device 12. As shown in FIG. The interface unit 14 is interposed between the bus 16 and a coder 18 that performs data processing such as compression processing of image data, and processes data sent from the coder 18 under the control of a system controller (not shown). This is an I/O interface circuit that supplies data to the memory card 10. This interface section 14 includes a control signal selector 30, a data selector 32, a timing controller 34, and two RAMs (random access memories).
36, 38, data amount counter 40, and timer 4
2 and a verify circuit 44.

The control signal selector 30, based on the select signal sent from the timing controller 34,
The read signal RD, write signal WR, and data identification signals A0 and A1 sent through the same circuit 34 are sent to the bus 16.
This is a selector that selectively outputs.

The two RAMs are a command RAM 36 that stores various EEPROM commands and a header RAM 38 that stores header information. Commands such as write and erase commands and header information are read or written based on control signals sent from the system controller, respectively. The data selector 32 includes commands read from the command RAM 36, header information read or written from the header RAM 38, and transmission data CDT0-7 or reception data CDV0-7 sent from the coder.
This is a selector that selectively outputs the data to the bidirectional data buses D0 to D7 of the bus 16, or selectively outputs the input of the bidirectional data bus to each section. The select signal is supplied from the timing controller 34.

The data amount counter 40 receives a control signal CD sent from the coder 18 to the timing controller 34.
This is a counter circuit that monitors R and CWR, counts the amount of data sent or read from the coder 18, and notifies the timing controller 34 of a cluster break every time the capacity of each cluster of the EEPROM is 8K bytes. . The timer 42 is connected to the memory card 1
The write timing in Figure 6 required for 0 is 10 μs,
The erase timing 9.5 ms shown in FIG. 7 is generated and supplied to the timing controller 34 to notify the timing controller 34 of the operation waiting state in the memory card 10. This timer 42 may be provided within the memory card 10, and in that case, the RDY/BUSY signal shown by the broken line may be sent from the memory card 10 to the timing controller 34.

The timing controller 34 receives control inputs from the data amount counter 40 and the timer 42,
This is a timing circuit that outputs a select signal to the data selector 32 and selector control signal section 30. The data latch verify 44 accumulates transmission data CDT0 to CDT7, and reads data CDT returned from the memory card 10.
This is a verification circuit that performs a verification check with DV0 to DV7.

In the operating state, when writing data from the host device 12 to the memory card 10, the coder 18 sends a control write signal CWR to the timing controller 34, and sends write data CDT0-7 to the data selector 32. Under the control of the timing controller 34, the control signal selector 30 sends out the write signal WR and data identification signals A0, A1, and the data selector 32 sends out the transmission data D0-7 to the memory card 10. The host device 1 sends the RDY/BSY signal that indicates when the memory card 10 is writing and erasing.
2 or when the timer 42 is measuring time, the timing controller 34 outputs a transmission stop signal CBSY to the coder 18. When the write data reaches a predetermined amount, the host device 12 reads it, and the data latch verify 44 performs a verification check on the transmitted and received data.

When the host device 12 reads data from the memory card 10, the coder 18 sends a control read signal CWR to the timing controller 34. Under the control of the timing controller 34, the control signal selector 30 outputs the read signal RD, data identification signal A0,
A1 is sent, and the data selector 32 selects the memory card 1.
The received data D0-7 read from 0 are output to the coder 18 as received data CDV0-7.

The interface unit 14 operates as described above. In this case, reading and writing data is
This process is performed for each storage unit MU consisting of each cluster 18 in the data area 17 of the memory card 10 and its header section 20. That is, when writing data, the header of the cluster is written. Therefore, rewriting of management information accompanying data writing, that is, rewriting accompanied by erasure, is not performed, and the inconvenience that the management area quickly reaches the rewriting limit is eliminated. As a result, the life of the EEPROM is extended, the large capacity memory required on the host device side when rewriting management information can be omitted, and processing steps etc. can be simplified.

It should be noted that the present invention is not limited to the above embodiments, and it is clear that matters that can be easily changed by those skilled in the art are within the scope of the present invention as long as they do not depart from the spirit of the present invention. For example, it is not necessary to write data in the order of clusters starting from the highest address, and data may be written starting from any cluster. Alternatively, the interface unit 14 may be removed from the host device 14 and configured as an adapter.

[0036]

Effects of the Invention As explained above, according to the memory card storage management system of the present invention, the EE of the memory card can be improved.
The data area of the PROM is composed of, for example, a storage unit consisting of a cluster, which is the minimum management area for image data, and a header section in which management information for the cluster is written. When writing data, by sequentially searching the header sections of other clusters that have already been written and detecting an area in which no header section has been written, data can be written to that area. Along with this, management information is written in the header section of that area. Therefore, data can be written without erasing the management area, and the life of the EEPROM can be extended.

Furthermore, since the management information is not rewritten, there is no need to provide a large capacity memory on the system side, and the processing thereof can be omitted, making it possible to simplify the system.

Furthermore, when reading data, a desired data area is detected by searching the header section, and the data is read out. In this case, by searching for a data number for data identification, data can be searched in a shorter time.

[Brief explanation of drawings]

FIG. 1 is a format diagram showing a data area of an EEPROM in an embodiment of the memory card storage management system of the present invention.

FIG. 2 is a functional block diagram showing a memory card in one embodiment of the present invention.

FIG. 3 is a functional block diagram showing an interface section of a host device in an embodiment of the present invention.

FIG. 4 is a conceptual diagram showing a connection state between a host device and a memory card in an embodiment of the present invention.

FIG. 5 is a timing chart showing a data write cycle in one embodiment of the present invention.

FIG. 6 is a timing chart showing a data read cycle in one embodiment of the present invention.

FIG. 7 is a timing chart showing card erasure in one embodiment of the present invention.

[Explanation of symbols]

10 Memory card 12 Host device 14 Interface section 17 Data area 18 Cluster 20 Cluster head MU Memory unit

Claims (5)

[Claims] 1. In a memory card storage management system in which a memory card equipped with an electrically erasable and rewritable EEPROM as a storage element stores management information together with data, a storage area of the EEPROM comprises:
The storage area is divided into a plurality of storage areas each having a predetermined storage capacity, and each of the divided storage areas is formed with a header section for storing management information of data stored in the storage area. Recording of management information in the header section is performed when writing data to each storage area, and when accessing data, the management information stored in the header section of each storage area is searched. A record management method for a memory card, characterized in that information for accessing data is obtained by referencing the data, and based on the information, access is made for each storage area including each header section. 2. The memory card storage management system according to claim 1, wherein each storage area including the header section has the same capacity as an erase unit of a block erase type EEPROM. Card storage management method. 3. The memory card storage management system according to claim 1, wherein a data number is written in the header section to identify the data for each storage area when data is recorded. A memory card storage management method characterized by: 4. In a memory card system that uses a memory card as a recording medium that includes an electrically erasable and rewritable EEPROM as a storage element, management information is written in each storage area of the EEPROM of the memory card. In a system in which a memory card is installed which is divided into a plurality of storage areas of a predetermined capacity including a header part, the amount of data sent to the memory card is equal to the data storage capacity of each of the divided storage areas in the EEPROM. It is characterized by comprising a data amount counting means for counting whether the data amount has been reached, and a header writing means for writing management information into the header part of each storage area based on the count result of the data amount counting means. memory card system. 5. A memory card comprising an electrically erasable and rewritable EEPROM as a storage element and storing management information thereof together with data, wherein the EEPR
The OM has a storage area divided into a plurality of storage areas each having a predetermined storage capacity including a header section, and selects the start address of the storage area based on a control signal and address supplied from the system side. The present invention is characterized in that it comprises a control means for generating a start address selection signal to access data in each storage area of the storage area by incrementing subsequent addresses based on the start address selection signal. Memory card.