JPH0430033B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to read/write of memory for graphic displays (raster scan type), particularly
The present invention relates to a graphic display control method that effectively performs memory control for writing the results of a DDA (Digital Differential Analyzer) and reading the display on the graphic display.

Conventional configuration and its problems In graphic displays (raster scan type), figures expressed by mathematical formulas are converted into dot (pixel) sequences using DDA and written to frame memory.
Data is generally read from this frame memory and displayed on a cathode ray tube (CRT). 1st
The figure is an example of converting a figure into a sequence of points using DDA.
In Figure 1, indicates a straight line with a small slope,
If this straight line is converted into a pixel column (pixel coordinates are indicated by circles) using DDA, multiple pixels will be lined up in the same row (x direction). The example in FIG. 1 is an example of a straight line with a large gradient, and in this case, many pixels are lined up in the same column (y direction). 1st
In the case shown in the figure, it is possible to write to the memory effectively if multiple pixels can be written simultaneously in the x direction. In this case, it is possible to write to the memory effectively if multiple pixels can be written simultaneously in the y direction.

When configuring a frame memory using highly integrated ICs, it is normal to use multiple ICs to read and write multiple pixels simultaneously, but it is common to read and write multiple pixels simultaneously in the x direction. If this is done, in the conventional example, multiple pixels in the y direction will be included in the same IC, making it impossible to read and write multiple pixels simultaneously. Furthermore, if it is possible to read and write multiple pixels in the y direction, it becomes impossible to read and write multiple pixels simultaneously in the x direction.

FIG. 2 shows a conventional example for solving this problem. Figure 2a shows how pixels on the screen of the frame memory are written, dividing the frame memory into small square areas. In the divided areas, pixels on the screen are always in the same row (x direction) in the same row in memory, and pixels in the same column (y direction) on the screen are always in different rows in memory. Place it like this. (For example, d2 in Figure 2 a)
3 shows the state of the pixel in the second row and third column on the screen) Figure 2b shows the arrangement of pixels on the buffer memory at the end of DDA. When writing the contents of this buffer memory to the frame memory, the arrangement is changed using an address conversion table. Fig. 2c shows a part of an arrangement method different from the arrangement method shown in Fig. 2a.
The same column follows the rules for separate lines. The order of pixels in memory is different from the order of pixels on a CRT, so when displaying on a CRT display, the order of read data is changed.

In this method, the DDA results are stored in a square buffer memory.

This method has the drawback that as the number of read/write bits increases, the number of DDA square buffers and address conversion sections increases by a factor of two, making it unsuitable for simultaneous reading and writing of many pixels.

OBJECTS OF THE INVENTION The present invention eliminates the drawbacks of the prior art and provides an effective graphic display control method for writing multi-pixel DDA results in the x and y directions.

Structure of the Invention The present invention allows reading and writing in the x and y directions by making the aspect ratio of a frame memory different from that of the screen of a graphic display and devising addressing.

DESCRIPTION OF EMBODIMENTS The configuration of an embodiment of the present invention will be described below with reference to the drawings.

In FIG. 3, 1 is a frame memory,
This frame memory 1 has a storage capacity to store at least the pixels of one CRT screen, and data is constantly read out from this frame memory 1.
Displayed on CRT display 4. The pixel arrangement of the frame memory 1 is shown in FIG. As shown in FIG. 4, this frame memory 1 is a CRT
The size of the display screen, i.e. (m+
1)×(n+1) pixels, m×(n
+2). (In this example, m
>n. When n>m, m×(n+α), α
2) In other words, the number of columns is decreased by one and the number of rows is increased by one. As a result, the pixels displayed on the CRT display extend one pixel per line and are moved to the next line. The pixel position on the CRT display and the pixel position in memory are 1
This means that each row is shifted by one. The pixels in column (i-j), row j on the CRT display are stored in the storage location of column i, row j on the frame memory. Note that when ij<0, the pixel of the (i-j+m+1) column (j-1) row is stored at the position of the i column and j row. The configuration of the frame memory 1 is as follows for (m+1)×(n+1) pixels:
(m+2)×n ₂ array, and in the storage position of column i and row j, column j (i-j) of the graphic display.
Pixels in row (i-j0) or (j-1) column (i-j+m+1) row (i-j<0) may be stored.

The capacity of frame memory 1 is the screen size (m+
1)×(n+1). Therefore, the size of frame memory 1 is m×(n ₁
+2) or (m+2)×n ₂ . n ₁ and n ₂ are m
×(n ₁ +2)>(m+1)×(n+1),(m+2)×
n ₂
>(m+1)×(n+1).

Note that a pixel stored in the frame memory 1 consists of one bit in the case of black and white display, and a plurality of bits in the case of color display.

The frame memory 1 is normally read and written to several pixels at the same time. When writing, the configuration is such that a different row address can be selected for each column as described later. With today's technology,
The frame memory 1 is composed of a plurality of IC memory chips. In this case, it means that another address selection signal is provided by the IC chip. For reading for screen display, the configuration is such that all columns for simultaneous reading can be set to the same line address.

FIG. 8 shows a specific example of the frame memory 1. In this example, we considered a case where a graphic display that displays (refreshes) a 100 x 1000 screen 60 times per second is configured using 1 x 64 kilobit DRAM with a cycle time of 200 nanoseconds. If you use 16 pieces of 64 kilobit DRAM,
1Mbit memory space can be prepared. This memory can store 1024×1024 image information. In this case, the memory cycles required for displaying on the CRT are 1024 x 1024 x 60/16 = approximately 4 million times. Since 200 nanoseconds of memory has 5 million memory cycles per second, 80% of it is used for displaying on the CRT. The remaining memory cycles are available for writing the DDA results. Since writing the DDA result one bit at a time is slow, the present invention, which writes multiple bits in one cycle, is necessary.

From 101a to 101r in Fig. 8,
It is DRAM. 21 is an address bus, for writing, XY address 9 or address conversion 1
When reading the address information from timing generator 1, the address information from timing generator 3 is read out.
Supplied to DRAM101.

A data bus 22 supplies display information from the write buffer 8 to the DRAM 101 during writing. In reading, display information is supplied from the DRAM 101 to the read buffer 2. 1×64
When frame memory 1 is configured with 16 kilobit DRAMs, the data bits of these DRAMs are 1
Since the data bus 22 is a 16-bit bus, when 16 DRAMs are used, the data bus 22 is a 16-bit bus.

1 x 64 kilobit DRAM address information is 16
However, as will be explained later, each DRAM is given partially different address information, so the number of bits on the bus is greater than 16 (with 64KDRAM, the row address and column address are usually divided into two parts). (This is not related to the essence of the present invention, so the explanation will be based on the assumption that the address information is transferred at one timing.)

FIG. 9 shows a method of writing image information into the DRAM 101. In the specific example shown in Figure 8, the fourth
This is an application of the method shown in the figure. (m+1)×(n
+1) to 1024×1024, (m+2)×n,
This is the case when the size is 1025×1023.

Considering display on a CRT, display information from 0/0 to 0/15 is stored in a separate DRAM. Thereafter, each 16 pixels will be stored in the same DRAM in the same way. In this case, pixels 0/0, 0/16, 0/32, 0/48, . . . are stored in the same DRAM.

In this configuration, control in the X and Y directions of the DDA, which will be described later, is required in the Y-axis direction in FIG. Addresses will be provided separately.

Reference numeral 2 in FIG. 3 is a read buffer, and this read buffer 2 sends out multiple pixels simultaneously read out from the frame memory 1 to the CRT display 4 pixel by pixel. Reference numeral 3 denotes a timing generator. This timing generator 3 supplies the frame memory 1 with the address of display data to be sent to the CRT display 4 and a read timing signal to cause the frame memory 1 to read, and also transfers the read data of the frame memory 1 to the read buffer. 2, it supplies the timing to send one pixel at a time to the CRT display 4. As mentioned above, the array is out of alignment with the display, so in each row, address control is performed for each row, from which word (parallel read/write unit) and from which pixel the data is sent to the CRT display 4, and where it ends. This is also the role of the timing generator 3. The timing generator 3 also supplies horizontal and vertical synchronization signals to the CRT display 4. Reference numeral 4 denotes a CRT display. This CRT display 4 is a raster scan type display, and displays images using horizontal and vertical synchronization signals and a luminance signal. 5 is a DDA (digital differential analyzer), and this DDA 5 converts a figure expressed by a mathematical formula into a pixel example. The conversion result is an XY address and XY flag light data. Reference numeral 6 denotes a segment buffer, and this segment buffer 6 stores figures to be displayed on the CRT display 4 in the form of mathematical expressions. 7 is a controller, and this controller 7 takes out graphic elements one by one from the segment buffer 6, passes them to the DDA 5, and converts them into pixel columns. 8 is a write buffer, and this write buffer 8 temporarily stores the conversion result of the DDA 5 in order to write it into the frame memory 1. The contents of the write buffer 8 vary depending on the state of the XY flag 10.
As shown in Figure 1, when the slope is small,
The XY flag 10 is "X", and the contents of the write buffer 8, as shown in FIG. 5a, store pixel rows arranged in the x direction on the screen of the CRT display 4. Also, when the shape has a large slope as shown in Figure 1, the XY flag 10 is set to "Y".
The contents of the write buffer 8 are shown in Figure 5b.
As shown in , pixel rows arranged in the y direction on the screen of the CRT display 4 are stored. As a matter of course, the write buffer 8 records different data depending on the blinking and color of pixels. The symbols in FIG. 5 are the same as those in FIG. 9 is
This XY address register 9 is set by the DDA5 and indicates the position on the frame memory 1 of the pixel column appearing as a result of conversion by the DDA5. The memory address of the pixel in column i and row j on the screen indicates the position of column j (i+j). When i+jm, the (i+j-m) column indicates the (j+1) row. The XY address register 9 is
It shows representative positions of pixel columns. 10 is XY
flag, and this XY flag 10 is DDA5
The slope of the figure shown in FIG. 1 indicates whether the DDA result is in an "X" state that is long in the x direction or a "Y" state that is long in the y direction. Reference numeral 11 denotes an address converter, and this address converter 10 calculates that the address of the frame memory 1 is shifted by one pixel in the y direction as the address of the frame memory 1 shifts by one pixel in the x direction.

FIG. 6 shows details of the address converter 11. In Fig. 6, 112, 113,...
is a half adder, and half adder 112 is XY
The Y address of address register 9 is input.
Half adder 113 receives the output of half adder 112 as input. Make the same connection below. half adda 1
12, 113, . . . add +1 to each input. The above half adder 112, 11
The outputs of 3, . . . are respectively applied to different columns of the frame memory 1 via the address switch 12.

In FIG. 3, 12 is an address switch, and this address switch 12 changes how addresses are added to the frame memory 1 depending on the state of the XY flag. That is, when the XY flag is "X", the output of the XY address register 9 is directly applied to the frame memory 1. In this case, even if the column is moved one place to the right, the row (Y) address does not change. When the XY flag is "Y", the column (X) address of the output of the XY address register 9 is applied as is, and the output of the address converter 11 is applied to the frame memory 1 as the row (Y) address. In this case, when the column moves one place to the right, the row (Y) appears.
The address will be moved down one by one. That is, by the address switch 12, the address converter 1
Half adders 112, 113, . . .
This is because the output (address in the y direction) takes a different value for each column.

Next, the operation of this embodiment will be explained with reference to FIG. FIG. 7a shows an example that is long in the x direction. DDA
As a result, figures were generated at d(i+1),j, and d(i+2),j. Since it is included in the horizontal read/write words di to d(i+3), we rewrite it in this unit. Since the XY flag 10 is "X", all columns have the same Y address and are stored in the frame memory 1. That is, in the example of FIG. 8, the same address is given to all DRAMs. FIG. 7b shows an example that is long in the y direction.
As a result of DDA, data was generated at (j+1) and (j+2) of row i. Since it is included in d(j+3) from di in the vertical direction, it can be rewritten in this unit. Since the XY flag is "Y", an address is applied via the address converter 11, and as a result, the Y address increases by one as the shift in the x direction increases. As the configuration of frame memory 1 shifts one pixel to the right,
Since the format is to move pixels downward, it is supposed to be written in a predetermined y direction. In other words, in the example of FIG. 8, Y shown in FIG.
Only in the axial direction, the address of the previous DRAM plus 1 can be given to the next DRAM address.

In FIG. 3, no limit is placed on the bit length of the half adder, but it is practically advantageous to set a limit. As an example, it is possible to make the half adder 4 bits and increase the number to 15 bits. In this case, a maximum of 16 pixels can be written in the y direction. In this case, carry cannot be carried out from the 4th bit to the 5th bit, so the write area is limited to a range in which no carry occurs. In order to prevent a carry from occurring in the half adder, the address given to the address converter may be limited and instead written in two times.

Note that in the above embodiment, a memory configuration of m×(n+2) is used for a screen of (m+1)×(n+1), but the same effect can be achieved even with a memory configuration of (m+2)×n. can. In this case CRT
The pixel in the j-th row of the i-column on the display is stored in the j-th row of the (i+j) column on the memory. Further, the half adders 112, 113, . . . perform an operation of subtracting 1.

Effects of the Invention The present invention devises a reading method that spans the entire memory plane, so that relatively multi-bit y
It is possible to perform switching reading in both the direction and the x direction, making it effective for high-speed reading and writing. Another advantage is that there is no need to change the pixel arrangement when reading out for display on a CRT display.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of image processing in a graphic display, and FIGS. 2 a, b, and c are diagrams showing the memory configuration of a conventional graphic display.
FIG. 3 is a block diagram of an apparatus for implementing a graphic display control method in an embodiment of the present invention, FIG. 4 is a diagram showing a memory configuration in an embodiment of the present invention, and FIGS. 5a and 5b are the same. FIG. 6 is a block diagram of the address converter in the same embodiment. FIG. 7 a and b are diagrams each explaining the operation of the same embodiment. FIG. 8 is a specific example of the frame memory 1. An explanation diagram of the operation,
FIG. 9 is a block diagram of writing image information. 1... Frame memory, 2... Read buffer, 3... Timing generator, 4...
CRT display, 5...DDA, 8...Write buffer, 9...XY address, 10...XY flag, 11...Address converter, 12...Address switch, 112, 113...Half adder.

Claims (1)

[Claims] 1. In a device in which the DDA conversion result is written to a frame memory according to a flag representing a gradient state and read out to a raster scan type graphic display, one screen of this graphic display is configured (m+1). For ×(n+1) pixels, it has a frame memory consisting of a plurality of memory units that store (m+1)×(n+1) pixels in an m×n ₁ or (m+2)×n ₂ arrangement, and If the frame memory array is m×n ₁ ,
At the storage location of column i and row j of the frame memory, the column j (i-j≧0) or (i-j+m+1) of the graphic display is stored in column i and row j of the above graphic display.
Store the pixels in column (j-1) row (however, i-j<0), or if the arrangement of the frame memory is (m+2)×n ₂ , store the pixels in column i and row j of the frame memory. , row j (i-j) of the graphic display above (where i-j≧
0) or (j-1) column (i-j+m+1) row (however, i-j<0),
A graphic display characterized in that a plurality of pixels in a plurality of columns and the same row or a plurality of pixels in a plurality of columns and a plurality of rows of the frame memory are simultaneously read out by providing means for giving the same or different addresses to each memory unit. Control method. 2. A graphic display control method according to claim 1, wherein a plurality of half adders are combined and the output of each half adder is provided to a frame memory as a different address.