JPH04295885A - Gradation control clock signal generating circuit for color display device - Google Patents

Abstract

PURPOSE:To allow the gradation characteristic of pulse width modulation to match an electro-optical characteristic by varying a clock period of a gradation control clock signal by a storage circuit so that the color balance of red, green and blue is allowed to match the electro-optical characteristic of each color. CONSTITUTION:After a frequency dividing circuit is reset by a latch signal CL1, a clock signal GCK is inputted to a frequency dividing circuit 4. A frequency division output of 6 bits, which s subjected to frequency division is inputted to an equivalence detecting circuit 5. Six-bit data of a storage circuit 6 is addressed by a count output signal of a count circuit 7, and data of '0' address is inputted to the equivalence detecting circuit 5. Subsequently, when data of the frequency dividing circuit 4 and the storage circuit 6 match with each other, the equivalence detecting circuit 5 outputs a clock signal K. In this case, the clock signal K becomes a gradation control clock signal, can be set arbitrarily by the contents of the data of the storage circuit 6, and a clock period of a gradation control clock signal RGCP becomes an optical adjustment.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention adjusts the color balance of a flat color display device such as a liquid crystal display using an electrical control signal, and provides a gradation control clock signal for a control circuit to obtain a good-looking full-color display quality. Regarding generation circuits.

0002

2. Description of the Related Art Conventionally, as shown in FIG. 5, a flat color display device that displays gradations using a pulse width modulation driving method is driven by a scanning electrode driving circuit 52 of a liquid crystal color panel 53 and a color signal electrode driving circuit 51. The configuration is as follows. Here, each color data RD0-RD3, GD0-GD3, BD0-
BD3 is input to the signal electrode drive circuit 51. These color data are shifted by the shift clock signal CL2, and when data for one scanning line is sent,
It is latched into the line memory circuit by the latch clock signal CL1. Then, a signal obtained by frequency-dividing the gradation control clock signal GCP and the output of the line memory circuit are compared by a decoding circuit to determine the pulse width. Further, the frame signal FRM is input to the scan electrode drive circuit 52 and is used to perform line sequential scanning using the shift clock CL1 (the above-mentioned latch signal). The AC driving control signal M inverts the polarity of the output signals of the signal electrode driving circuit 51 and the signal electrode driving circuit 52 for each frame to perform AC driving.

0003

However, in conventional flat color display devices, a common gradation control clock signal is used for R, G, and B color gradation data. The pulse widths of G and B are not modulated to match the optimal electro-optical characteristics of each color, but are determined uniformly, so the balance between red, green, and blue is disrupted, resulting in color distortion. There were problems with unevenness and the inability to display a clear full color display.

[0004] Therefore, the purpose of the present invention is to adjust the color balance by performing pulse width modulation according to each color, even in the electro-optical characteristics that each color has. The objective is to obtain a beautiful full-color display without color unevenness.

[0005]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a signal electrode drive circuit that uniformly converts red, green, and blue gradation color data using a single gradation control clock signal. Rather than pulse width modulation, red, green,
By applying pulse width modulation according to the electro-optical characteristics of each blue color, a gradation control clock signal is input independently to obtain linear gradation for each color, and each color has a uniform linear gradation. I made it possible.

[0006]

[Operation] In the flat color display device configured as described above, the gradation control clock signal optimizes the clock period so that gradation can be displayed linearly over 16 gradations based on the electro-optical characteristics of each color. Since it is possible to display images in full color, color unevenness can be eliminated and full color display can be achieved.

[0007]

Embodiment FIG. 2 is a block diagram of a flat color display device showing an embodiment of the present invention. In FIG. 2, 23 is a color panel using a flat display element such as a liquid crystal. 21 is a signal electrode drive circuit for driving the signal electrodes of the flat color panel. 22 is a scan electrode drive circuit for driving the scan electrodes.

[0008] RD0 to RD3, GD0 to GD3, BD0
~BD3 are red, green, and blue gradation color data, respectively. M is an AC drive control signal. CL1 is a latch signal for the gradation color data. CL2 is a shift clock signal for the gradation color data. RGCP,G
GCP and BGCP are red, green, and blue gradation control clock signals. FRM is a frame signal for starting scanning.

As described in the conventional example, each gradation color data RD0 to RD3, GD0 to GD3, BD0 to BD3
is input to the signal electrode drive circuit 21. and,
Each color data is shifted by a shift clock signal CL2, and when one line of data is transferred, each gradation color data is latched into a line memory circuit by a latch signal CL1.

Next, each gradation control clock signal R shown in FIG.
GCP, GGCP, and BGCP are input and converted into 4-bit signals by a frequency dividing circuit. Each of these 4-bit signals corresponds to each of the latched gradation color data RD0 to RD3, G.
It is input to the decoder circuit together with D0 to GD3 and BD0 to BD3. This decoder circuit compares the latched gradation data of each color with the frequency-divided 4 bits and outputs an output signal "H" until they match.

Therefore, the decoder circuit outputs an output signal having a pulse width corresponding to the gradation data of each color to the drive circuit. The drive circuit drives the display element by outputting a selected drive voltage for lighting and displaying the display dots during a period of the pulse width of the decoder circuit. FIG. 4 shows that the respective gradation control clock signals BGCP, RGCP, and GGCP have different clock periods. The frequency dividing circuit that divides the frequency of the gradation control clock signal is reset by the latch signal CL1.

Therefore, each gradation color data is both 0,
Assuming the case of 0, 0, 1, the time width BDT of the blue selection drive voltage, the time width RDT of the red selection drive voltage, and the time width RDT of the green selection drive voltage are determined by the timing of one clock of the gradation control clock signals BGCP, RGCP, and GGCP. It can be understood that the time widths GDT of the selection drive voltages are different. Figure 3
shows an example of electro-optical characteristics for R, G, and B (red, green, and blue). This shows that when driven with the same driving voltage, the amount of light transmission differs for each color, making it impossible to display a bright full-color display without color unevenness. Therefore, in the present invention, the pulse width is optimized so that the drive voltage of each color becomes the drive voltage value shown at points g, r, and b as shown in FIG. 3 at the first clock of the gradation control clock signal. It is something that can be done.

An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, 1 is a red gradation control clock signal generation circuit. 2 is a green gradation control clock signal generation circuit. 3 is a blue gradation control clock signal generation circuit. 4 is a frequency dividing circuit for dividing the frequency of the clock signal GCK. 5 is a coincidence detection circuit for detecting coincidence of data. 6 is a storage circuit such as a ROM. 7 is a count circuit.

Since the configurations of the green and blue gradation control clock signal generation circuits 2 and 3 are the same as the red gradation control clock signal generation circuit 1, the red gradation control clock signal generation circuit 1 I will limit myself to this explanation. The clock signal GCK is a clock signal having a period obtained by dividing the time width of one scanning period into 1/64. First, the frequency divider circuit is reset by the latch signal CL1, and then the clock signal GCK is input to the frequency divider circuit 4. divided 6
The bit frequency-divided output is input to the coincidence detection circuit 5. Further, the 6-bit data in the memory circuit 6 is addressed by the count output signal of the count circuit 7, and the data at address 0 is input to the coincidence detection circuit 5. When the data in the frequency dividing circuit 4 and the data in the storage circuit 6 match, the matching detection circuit 5 outputs a clock signal K.

The clock signal K generated in this manner becomes a gradation control clock signal. Therefore, the clock cycle of the gray scale control clock signal RGCP can be arbitrarily set depending on the data contents of the storage circuit, and the clock period of the gray scale control clock signal RGCP can be optimally adjusted.

[0016]

[Effects of the Invention] As explained above, the present invention uses one gradation control clock signal to control all gradation color data in order to control the pulse width of the selected drive voltage of the signal electrode drive circuit. Instead, a gradation control clock signal is provided for each color, and the period of the clock signal can be adjusted so that the electro-optical characteristics of each color are optimally matched.The gradation control clock signal generation circuit is Since it can be set arbitrarily using available input circuits, it can be incorporated into a color display device without changing the circuit, which has the effect of eliminating color unevenness and realizing a beautiful full-color display.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a gradation control clock signal generation circuit showing one embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a flat color display device showing an embodiment of the present invention.

FIG. 3 is an explanatory diagram showing that electro-optical characteristics differ for each color.

FIG. 4 is an explanatory diagram showing the timing of a gradation control clock signal.

FIG. 5 is a block diagram showing the configuration of a conventional flat color display device.

[Explanation of symbols]

1 Red gradation control clock signal generation circuit 2 Green gradation control clock signal generation circuit 3 Blue gradation control clock signal generation circuit 4 Frequency division circuit 5 Coincidence detection circuit 6 Memory circuit 7 Count circuit 21 Signal electrode drive circuit 22 Scanning electrode drive circuit 23 Color display panel

Claims (1)

[Claims] 1. A color display panel having a matrix structure of scanning electrodes and R, G, and B (red, green, and blue) color signal electrodes, and a color display panel having a matrix structure of scanning electrodes and R, G, and B (red, green, and blue) color signal electrodes; A color signal electrode drive circuit configured to input tone color data and a tone control clock signal for controlling the output time width of the selected drive voltage, and output a selected drive voltage with a pulse width corresponding to the tone color data. and a gradation clock signal generation circuit for a flat color display device comprising a scan electrode drive circuit for driving the scan electrode, a frequency division circuit for frequency dividing the clock signal, and the gradation clock signal. , a memory circuit that uses the output of the count circuit as an address signal, and a coincidence circuit for detecting coincidence between the output of the frequency dividing circuit and the output of the memory circuit, and the coincidence circuit A gradation control clock signal generation circuit for a color display device whose output is the gradation control clock signal.