JPH04285793A - Dynamic ram - Google Patents

Abstract

PURPOSE:To secure stable operations for each of the dynamic RAM being produced despite of the variations in process conditions. CONSTITUTION:In a type of the dynamic RAM, which latches the signals in a memory cell through a sense amplifier during a read out period, the sense amplifier, a column gate and an active load circuit are each configured by field effect transistors and each of the field effect transistors are constructed so that the channel length of these transistors are essentially the same with respect to each other.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM, and more particularly to a dynamic RAM (random access memory) equipped with a sense amplifier that latches the signal of a selected dynamic memory cell onto a bit line of each column. .

In dynamic RAM, efforts are being made to shorten the access time from address input to data output of each memory cell as much as possible to enable high-speed operation. One type of dynamic RAM capable of high-speed operation is one in which row addresses are fixed and memory cells can be continuously accessed only by inputting column addresses. In this type of dynamic RAM,
A sense amplifier is provided for each column, and after a signal from a selected memory cell is latched onto a bit line by the sense amplifier, column selection is performed in a static manner.

0003

2. Description of the Related Art The above type of dynamic RAM will be explained with reference to FIGS. 1 and 2. 1 and 2 are a schematic circuit diagram and a block diagram of a dynamic RAM, respectively, and both are diagrams for explaining the configuration of an embodiment of the present invention and a conventional dynamic RAM.

As shown in FIG. 2, the memory array 1 includes:
It is equipped with a large number of memory cells arranged in columns and rows, and one row is selected by word lines WL1 to WLn selected by a row decoder 8 to which a row address is input, and a column to which a column address is input. One column is selected by a signal from decoder 9.

When a row address is input at the time of reading, the memory cells arranged in the row in each column are brought into conduction with one of the corresponding bit line pair by the transition of the word lines WL1 to WLn to the H level. Data in the memory cell is latched onto bit line pair 2, 2'. Next, when a column address is input, the bit line pair 21, 21' of the selected column is brought into conduction with the bus lines 5, 5' forming the data line through the conduction of the column gate transistor 41. The data of the memory cells that have been transmitted are transmitted via the bit line pair 21, 21' and the bus lines 5, 5'.
It is read by the main amplifier 7.

The active load circuit 6 is configured as an N-channel transistor, and is turned on by a signal φR that attains an H level during reading, thereby connecting the high potential power supply VCC and the bus lines 5, 5'. By using an N-channel transistor as the active load circuit 6, the bus lines 5, 5'
The H-level potential can be suppressed by the threshold voltage of the N-channel transistor. Also, the bus line that is electrically connected to one bit line that is at L level is determined by the ratio of the series on-resistance of transistor Q8 or Q9 that constitutes the active load circuit and Q6 (Q7) and Q3 (Q5). limited by level. Since the potential amplitude is limited to a small value, when the bus lines 5, 5', which have large parasitic capacitances, make a bidirectional transition between the H level and the L level, the transition is accelerated and the signal read period is shortened.

In the dynamic RAM of the above type, MOS transistors are generally used for each transistor constituting the sense amplifier 31, column gate 41, and active load circuit 6 in consideration of low power consumption and high integration. . Of these, the MOS that constitutes the sense amplifier 31
The channel lengths of the transistors Q2 to Q5 are made long in order to detect as small a voltage as possible, while the column gate 41 and the active load circuit 6
Each of the MOS transistors Q6 to Q9 constituting the circuit is formed to have a short channel length in order to increase the driving ability as much as possible.

[0008]

Generally, it is difficult to keep process conditions such as temperature constant during the manufacture of semiconductor devices, and differences in process conditions cause variations in the characteristics of each circuit element. Therefore, the dynamic RAM of the above type also has a problem in that the characteristics of its circuit elements vary due to variations in process conditions.

For example, M constituting the active load circuit 6
When the channel lengths of OS transistors Q8 and Q9 are formed short, in this dynamic RAM, bus lines 5,
5' amplitude becomes small, increasing the risk of malfunction in the main amplifier 7. In the opposite case, the amplitude of bus lines 5, 5' becomes large, and the level transition of the bus lines becomes slow, resulting in high-speed operation. Both affect the basic performance of dynamic RAM.

[0010] The present invention is directed to the conventional dynamic RA described above.
In view of the M problem, the potential amplitude of the data line does not differ for each dynamic RAM manufactured, despite differences in process conditions during manufacturing, and there is no problem with high speed and accuracy of signal transmission. It is an object of the present invention to provide a dynamic RAM that maintains a predetermined performance without causing any problems.

[0011]

Means for Accomplishing the Object In order to achieve the above object, the dynamic RAM of the present invention has a large number of memory cells (
11 to 1n), bit lines (21, 21') arranged for each column of memory cells (11 to 1n), and rows arranged corresponding to each bit line (21, 21'). Each one of the memory cells (11 to 1n) selected by the address
) to the respective bit lines (21, 21');
Column gates (41) are arranged corresponding to the bit lines (21, 2') and are selected by the column address and are made conductive.
data lines (5, 5') arranged to be electrically conductive with the data line (1');
an active load circuit (6) that limits the potential amplitude of the data lines (5, 5') to a predetermined range; The dynamic RAM is configured of field effect transistors, each of which is characterized in that the channel lengths of the field effect transistors are substantially equal to each other.

0012

[Operation] The structure in which the channel lengths of the field effect transistors of the sense amplifier, column gate, and active load circuit are formed to be substantially equal to each other prevents variations in the channel lengths of these transistors due to fluctuations in process conditions. Even if a
The potential amplitude of the data line does not vary from time to time.

[0013]

[Embodiment] This will be explained with reference to FIG. In the figure, a memory array 1 includes a large number of memory cells 11 to 1n in one illustrated column, and further includes a large number of columns similar to this column. Each of the memory cells 11 to 1n is electrically connected to a capacitor C11 to C1n that stores the logic signal level "H" or "L" as a voltage signal based on accumulated charges, and the H level of any one of the many word lines WL1 to WLn. and N-channel transistors Q11-Q1n that transmit voltage signals stored on capacitors C11-C1n to either bit line 21, 21'.

The sense amplifier 31 includes two sets of CMOS transistors driven by sense amplifier power lines PSA and NSA.
Each CMOS transistor 32, 33 has its commonly connected gate connected to the series connection node n2, n1 of the source-drain path of the other CMOS transistor 33, 32.
Each one of the bit lines 21' and 21 is connected to the other bit line 21'. The sense amplifier power supply lines PSA and NSA are held at half the potentials VCC and VSS of the high potential and low potential power supplies, respectively, during the reset period, and transition to approximately the high potential VCC and low potential VSS levels, respectively, during the read period. do.

The bit line pair 21, 21' is connected to the bus line 5, via a pair of N-channel transistors Q6, Q7 of a column gate 41, which is made conductive by a column selection signal CLSm.
The bus lines 5, 5' can be electrically connected to each bit line pair via each column gate, and are connected to the input of the main amplifier 7. Active load circuit 6 includes a pair of N-channel transistors Q8 and Q9 that are rendered conductive by read signal φR that attains an H level during a read period to conduct conduction between high potential power supply VCC and bus lines 5 and 5'.

Dynamic RAM configured as above
When reading data, a row address is first input, one of the word lines WL1 to WLn becomes H level, and the data in the memory cells of each column selected by the word line is read. The data is transmitted to one of the bit line pairs and latched by sense amplifier 7 for each bit line pair. For example, if the memory cell 11 is selected in the illustrated column and its data is logic "H", the sense amplifier 31
Of the CMOS transistors 32 and 33, the N-channel transistor Q5 is turned on and the bit line 21' is connected to VS.
The bit line 21 is maintained at the S level and the P channel transistor Q2 is turned on to maintain the bit line 21 at the VCC level.

When a column address is input, one selected column gate becomes conductive, and the corresponding bit line pair and bus lines 5, 5' become conductive. On the other hand, since the active load circuit 6 becomes conductive in response to the H level of the read signal φR, the high potential power supply VCC, the transistors Q8 and Q9 of the active load circuit, the bus lines 5 and 5', and the transistors Q6 of the column gate 41 , Q7, each bit line 21, 21',
Each CMOS transistor 32 and 33 of the sense amplifier 31
Among them, the conductive P-channel transistor or N-channel transistor, and the sense amplifier power supply line PSA
Alternatively, a circuit leading to the NSA is formed. As a result, in the case of the previous example in which the data of the selected memory cell is "H", one bus line 5 goes to H level and the other bus line 5 goes to H level.
' goes to L level, and the main amplifier 7 outputs the data.
H” is detected.

In the above example, bus line 5 is electrically connected to one bit line 21, which is maintained at the VCC level, and to the VCC power supply via N-channel transistor Q8. The bus line 5 has column gate transistors Q6 and Q7 connected to N
The N-channel transistor Q8, which is a channel transistor and is an active load circuit that has a large drive capability and can raise the potential of the bus line, is turned on by the threshold voltage Vth. As a result, the potential is ultimately maintained at VCC-Vth during the read period.

The other bus line 5' is connected to a high potential power supply VC via a transistor Q9 of an active load circuit 6.
On the other hand, the transistor Q7 of the column gate 41, the bit line 21' on the other hand, and the CM of the sense amplifier 31
It is electrically connected to the sense amplifier power supply line NSA via the N-channel transistor Q5 of the OS transistor 33, which is electrically conductive. Therefore, the bus line 5' is connected to the N-channel transistor Q9 of the active load circuit 6, the N-channel transistor Q7 of the column gate 41, and the sense amplifier 3.
Since the voltage is divided by one N-channel transistor Q5, the potential is lower than the potential of the one bus line 5 by the voltage value α. This α is the value of the aforementioned potential amplitude of the bus line, and from the viewpoint of the detection sensitivity of the sense amplifier 7 and the transition speed of the potential level, it is required that the value does not vary among individual semiconductors.

The values of the potentials VDB and α of the bus line 5' at the L level are as follows from the above voltage division condition: VDB=VCC-Vth-α=VCC(RQ7
+RQ5)/(RQ9+RQ7+RQ5) (1). However, RQ9, RQ7 and RQ5 are on-resistances of transistors Q9, Q7 and Q5, respectively, and Vth is N
This is the threshold voltage of channel transistor Q9.

Generally, the on-resistance of a MOS transistor is
It is known that the on-resistance RQ of each of the MOS transistors Q9, Q7, and Q5 is proportional to the channel length.
RQ9=
C9*LQ9, RQ7=C7*LQ7, RQ5=C5*
It can be expressed as LQ5. However, C9, C7 and C
5 is a constant that is determined by the channel width of each MOS transistor and does not depend on the channel length.

In the present invention, each MOS transistor Q9,
The channel lengths of Q7 and Q5 are formed to be equal to each other, and LQ9=LQ7=LQ5. Therefore, the right side of equation (1) above is VCC(C7+C5)/(C9+C
7+C5), and from now on, α is α=VCC-Vth-VCC(C7+C5)/
(C9+C7+C5) (2) is determined.

[0023] These channel lengths are
It is known that even if its value varies due to variations in process conditions during manufacturing, it varies in the same way for each MOS transistor manufactured under the same process conditions. Therefore, the potential determined by the above formula The amplitude α does not vary due to differences in process conditions.

In the dynamic RAM of the above embodiment, the channel length of each MOS transistor of the sense amplifier 31, column gate 41, and active load circuit 6 is as follows.
Each MOS arranged in other circuit elements, such as a write circuit, etc.
It is formed longer than the channel length of the transistor. When the channel length is long, it is difficult to be affected by variations in channel length due to variations in process conditions, so it is particularly possible to maintain the potential amplitude constant.

[0025]

[Effects of the Invention] As explained above, according to the present invention,
Depending on differences in process conditions, individual dynamic RAM
Even if the channel lengths of the MOS transistors vary from time to time, the channel lengths of the MOS transistors that constitute the dynamic RAM and determine the value of the potential amplitude of the bus line are formed to be equal to each other, so the potential amplitude of the bus line can be changed individually. We can provide a dynamic RAM that maintains both high-speed operation and signal transmission accuracy without the risk of fluctuations.
This greatly contributes to the stability of M's operation.

[Brief explanation of the drawing]

FIG. 1: One embodiment of the present invention and conventional dynamic RA
It is a circuit diagram of M.

FIG. 2 is a block diagram of the dynamic RAM of FIG. 1;

[Explanation of symbols]

1 Memory array 11
~1n Memory cells 2, 21, 21'
bit line

Claims (2)

[Claims] 1. A large number of memory cells (11 to 1n), bit lines (21, 21') arranged for each column of the memory cells (11 to 1n), and each bit line (21, 21'). ′)
A sense amplifier (31) is arranged corresponding to the bit line (21, 21') and latches the signal of each one of the memory cells (11 to 1n) selected by the row address to the bit line (21, 21').
), a column gate (41) arranged corresponding to each of the bit lines (21, 21') and turned on when selected by a column address; (21, 21') and a data line (5, 5') arranged to be electrically conductive with the data line (5, 5').
), the sense amplifier (31), the column gate (41), and the active load circuit (6) each include a field effect transistor. A dynamic RAM characterized in that the channel lengths of the respective field effect transistors are formed to be substantially equal to each other. 2. The channel length of each of the field effect transistors constituting the sense amplifier (31), the column gate (41), and the active load circuit (6), respectively, is
2. The channel length of the field effect transistor according to claim 1, wherein the channel length is longer than the channel length of a field effect transistor constituting circuit elements other than the sense amplifier (31), the column gate (41), and the active load circuit (6). Dynamic R
A.M.