JPH04284731A - Demodulator - Google Patents

Abstract

PURPOSE:To enhance an equalization capability of a transversal filter type equalizer by varying a limit of a tap coefficient in response to the state of synchronization and asynchronization of the demodulator. CONSTITUTION:An asynchronization detection circuit 105 detects asynchronization of a demodulator 11 to send a signal S. The signal S goes to a '0' level at the synchronization and goes to a '1' level at the asynchronization and is inputted to a transversal filter type equalizer 12. The signal S is inputted a tap coefficient limit changeover circuit 104 to limit a maximum value of a tap control signal of a transversal filter 102. A signal generated from a tap coefficient control signal generating circuit 103 is outputted to each tap of the filter 102 without being limited at the synchronization. A maximum value is limited at each tap of the filter 102 at the synchronization. The filter 102 controls each tap to equalize the inter-code interference in the propagation line and outputs an output digital signal digitized by a terminal 2. Through the configuration above, an excellent lock characteristic is obtained.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation device using a demodulator and a transversal filter type equalizer in digital microwave radio communications.

0002

2. Description of the Related Art Conventionally, with reference to FIG. 4, in a digital wireless transmission system, an antenna 108a of a transmitting device 108 for transmitting a modulated signal from a modulating device 107 and an antenna 109a of a receiving device 109 are connected to each other. Multipath fading occurring in the propagation path, generally due to waveform distortion due to two-wave interference fading, causes deterioration in line quality. On the other hand, it is known that waveform distortion due to two-wave interference fading can be improved by applying a transversal filter type equalizer to the demodulator 110.

As is well known, there are two types of transversal filters: one that consists of an intermediate frequency (IF) band, and one that consists of a baseband. Transversal filters configured in the baseband include analog types that use an analog delay line and analog integrator, and ones that use a shift register (SR) for the delay circuit and an up/down counter (U/D counter) as the integrator. There is a digital form that can be used. Therefore, there are two types of transversal filter type equalizers: an IF type and a baseband type, and the baseband type includes an analog type and a digital type.

FIG. 5 shows a conventional example of a demodulation device using a digital transversal filter type equalizer. In FIG. 5, this demodulation device includes an input terminal 1, a demodulator 11
, an A/D converter 101, and a transversal filter type equalizer 12, and the equalization operation is performed by digital signal processing.

[0005] The operation of a conventional example of a demodulator will be briefly described with reference to FIGS. 4 and 5. The IF signal is synchronously detected by the demodulator 11 via the input terminal 1 to become an analog baseband signal, and further sampled and quantized by the A/D converter 101 to become a demodulated digital signal, which is then subjected to transversal filter type equalization. The signal is supplied to the transversal filter 102 of the device 12 and the control signal generator 103 as a control signal.

Referring to FIG. 6, control signal generation circuit 103
are the identification information signal (polarity signal) D of the output signal of the A/D converter 101 and the error information signal E of the output digital signal whose waveform distortion has been equalized by the transversal filter type equalizer 12. and as input. The control signal generation circuit 103 includes a transversal filter 102
A tap coefficient control signal for controlling is generated and output to the tap coefficient limiting circuit 106. Tap coefficient limiting circuit 10
At 6, the tap coefficient limit signal from the control signal generation circuit 103 is input to the limiter circuits 30 to 32 to limit the maximum value of the tap control signal, and the transversal filter 10
Output to each tap of 2.

In the transversal filter 102, A
The inter-symbol interference is equalized for the output digital signal of the /D converter 101 based on the tap coefficient control signal from the tap coefficient limiting circuit 106, and the equalized output digital signal is output from the output terminal 2.

Next, control signal generating circuit 103 and tap coefficient limiting circuit 106 will be explained. In FIG. 6, the input identification information signal D is input to the flip-flop circuit 2.
1, it is delayed by 1 bit (1 clock period),
It is output to exclusive OR circuits 24-26. The error information signal E is divided into two branches, one of which is input to the exclusive OR circuit 26, and the other is input to the flip-flop circuit 22, delayed by one bit, and output from the flip-flop circuit 22. The output signal from the flip-flop circuit 22 is output to the exclusive OR circuit 25 and the flip-flop circuit 23. This output signal is output to the exclusive OR circuit 24. In this way, the exclusive OR circuits 24 to 2
6, the error information signal E shifted by 1 bit in time relation
and the identification information signal D and output as a correlation signal. The correlation signals output from the exclusive OR circuits 24 to 26 are respectively input to up/down counter circuits (U/
D counters 27 to 29 perform an averaging operation and output to limiter circuits 30 to 32 of the tap coefficient limiting circuit 106. FIG. 3 is an example of a transversal filter and is well known, so a description thereof will be omitted. Transversal filter 102
A limiter circuit 31 for outputting a tap coefficient control signal Co that controls a digital multiplier 36 of the center tap of
Now, it is desired to limit the maximum value of the tap coefficient control signal CO 2 , that is, the tap coefficient limit value is set to 1.

On the other hand, in the limiter circuit 30 and limiter circuit 32 for outputting the tap coefficient control signals C-1 and C+1 that control the -1 tap and +1 tap of the transversal filter 102, the tap coefficient control signal C- is output. 1 and C+1 are limited to 1/2.

Tap coefficient control signals C-1, C0, and C+1 outputted from the limiter circuits 30 to 32 control each tap of the transversal filter 102, and eliminate intersymbol interference due to multipath fading and the like occurring in the propagation path. become Incidentally, the equalization ability for improving fading can be measured by a simulator (not shown) provided between modulator 107 and demodulator 110. FIG. 7 shows the amplitude ratio ρ (notch depth) between the main wave forming the fading and the interference wave with respect to the fading center frequency fO (notch frequency).

[0011]

[Problems to be Solved by the Invention] The conventional demodulator described above uses a transversal filter type equalizer so that the demodulator can quickly converge when the demodulator loses synchronization due to fading or the like. The maximum value of the tap coefficient control signal controlling each tap is limited by a limiter circuit. In other words, the maximum value of the tap coefficient control signal is limited regardless of whether the demodulator is synchronous or asynchronous. Therefore, it cannot be said that the transversal filter type equalizer always exhibits its inherent equalization ability. As a result, the depth of the notch is small, resulting in a loss of improvement (signature characteristics). Therefore, the technical problem of the present invention is to provide demodulation that can always fully utilize the equalization ability of the transversal filter type equalizer by varying the limit value of the tap coefficient depending on the synchronous or asynchronous state of the demodulator. It's about getting the equipment.

0012

[Means for Solving the Problems] According to the present invention, in a demodulation device that is used on the demodulation side of a digital wireless communication system and is equipped with a transversal filter type equalizer that equalizes propagation distortion, it is possible to synchronize the demodulator. an asynchronous detection circuit for detecting out-of-sync; a control signal generation circuit for generating tap coefficients for the transversal filter type equalizer; and two types of tap coefficient limit values for synchronization and non-synchronization of the demodulator. and a tap coefficient limit value switching circuit for switching between the two types of tap coefficient limit values based on the output of the asynchronous detection circuit. Also,
In this demodulator, the tap coefficient limit value switching circuit limits tap coefficients other than the center tap of the transversal filter to a value smaller than 1 when the output of the asynchronization detection circuit indicates asynchronization of the demodulator, and There is obtained a demodulator characterized in that it operates so as not to limit the tap coefficients when the demodulator indicates synchronization.

[0013]

[Operation] When the demodulator is in the synchronized state, the limit value of the center tap tap coefficient C0 is set without limiting the maximum value of the tap coefficient control signal that limits each tap of the transversal filter type equalizer. When set to 1, tap coefficients C-1, C+ of ±1 taps other than the center tap
1, the limit value is also set to 1. On the other hand, in asynchronous mode, if the limit value of the tap coefficient control signal for the center tap is set to 1, as in the past, for ±1 taps other than the center tap, the limit value of the maximum value of the tap coefficient control signal is set to be less than 1. Limit to a small predetermined value (for example, the limit value is 1/2 at ±1 tap).

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a demodulator according to an embodiment of the present invention. Regarding the same components as the conventional example shown in FIG.
The same reference numerals are given, and the explanation thereof will be omitted. Hereinafter, a method of switching each tap coefficient control signal of the transversal filter type equalizer 12, which is a component according to the present invention, will be explained.

The IF signal is sent to the demodulator 1 via the input terminal 1.
1, it is synchronously detected and becomes an analog baseband signal. This analog baseband signal is sent to the A/D converter 1
01, it is sampled and quantized to become a demodulated digital signal, which is output to the transversal filter type equalizer 12.

In this embodiment, an asynchronous detection circuit 105 connected to the demodulator 11 detects asynchrony in the demodulator 11 and outputs an asynchronous detection signal S. The asynchronous detection signal S has a “0” level during synchronization, and a “1” level when non-synchronized.
"Transversal filter type equalizer 12 as a level
is input.

In the transversal filter type equalizer 12, the asynchronous detection signal S is input to a tap coefficient limit value switching circuit 104 that limits the maximum value of the tap coefficient control signal that controls each tap of the transversal filter 102. . During synchronization, the asynchronous detection signal S becomes a "0" level, and the tap coefficient control signal is output to each tap of the transversal filter 102 without being limited by the maximum value in the tap coefficient limit value switching circuit 104.

[0018] Furthermore, during asynchronous time, the asynchronous detection signal S is at the "1" level, and the maximum value of the tap coefficient control signal is limited for each tap of the transversal filter 102 in the tap coefficient limit value switching circuit 104. It is output to each tap of the transversal filter 102. The transversal filter 102 controls each tap using a tap coefficient control signal, equalizes intersymbol interference due to multipath fading in the propagation path, and outputs an equalized output digital signal from the output terminal 2.

FIG. 2 shows an example of the configuration of the control signal generation circuit 103 and the tap coefficient limit value switching circuit 104. As shown in FIG. 2, the control signal generation circuit 103 includes flip-flop circuits (F/F) 21 to 23, exclusive OR circuits 24 to 26 which are correlation detection circuits, and up/down counters (U/D counters) 27 to 23. The tap coefficient limit value switching circuit 104 is composed of limiter circuits 30 to 32. The input identification information signal D is delayed by one bit (one clock cycle) in the flip-flop circuit 21 and output to the exclusive OR circuits 24 to 26. In this embodiment, the limiter circuits 30 to 32 receive the asynchronous detection signal S.
This differs from the conventional example in that the limit value of the tap coefficient control signal is switched depending on the level "0" or "1" of the tap coefficient control signal.

Furthermore, the error information signal E is branched into two branches, one of which is input to the exclusive OR circuit 26, and the other is input to the flip-flop circuit 22 and output from the flip-flop circuit 22 with a delay of one bit. The output signal of the flip-flop circuit 22 is output to the exclusive OR circuit 25 and the flip-flop circuit 23. This output signal is
It is output to the exclusive OR circuit 24. The exclusive OR circuits 24 to 26 correlate the error information signal shifted by one bit in time relation with the identification information signal and output a correlation signal. The correlation signals that are the outputs of the exclusive OR circuits 24 to 26 are sent to an up/down counter circuit (U/D counter) 2.
7 to 29, averaged, and output to the limiter circuit 30.
~32 is output.

The limiter circuits 30 to 32 input the asynchronous detection signal S from the asynchronous detection circuit 105, and the demodulator 1
1 is synchronized, the asynchronous detection signal S is “0”
The limit value that limits the maximum value of the tap coefficient control signals C-1 and C+1 that control the taps other than the center tap among the taps of the transversal filter 102 is set to 1 in the same way as the limit value of the center tap. As,
To output to each tap without limiting the tap coefficient control signal. Furthermore, during asynchronous time, the asynchronous detection signal S is “1”.
" level, and the limiter circuits 30 to 32 reduce the limit value of the maximum value of the tap coefficient control signals C-1 and C+1 to 1/2.
output to each tap. However, in the tap coefficient control signal CO of the center tap, the maximum limit value is fixed to "1" regardless of whether it is synchronous or asynchronous.

Although the present description has been made regarding a one-dimensional three-tap transversal filter, a transversal filter can usually be realized using a two-dimensional model as well. Although a digital baseband transversal equalizer composed of digital multipliers and adders has been described, the present invention can also be applied to an IF type or baseband type analog transversal equalizer using an analog type transversal filter. It goes without saying that it is possible.

[0023]

As explained above, according to the demodulator of the present invention, by switching the maximum value of the tap coefficient control signal of the transversal filter between synchronization and non-synchronization, the tap coefficient control signal is By fixing the maximum value of the signal, it is possible to eliminate the loss of the amount of improvement (signature) due to not being able to utilize the inherent equalization ability of the transversal filter type equalizer, and when out of synchronization, the tap coefficient control signal is limited. By doing so, there is an effect that good drawing characteristics can be obtained as before.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a demodulator according to an embodiment of the present invention.

2 is a diagram showing a control signal generation circuit 103 and a tap coefficient limit value switching circuit 104 of FIG. 1. FIG.

[FIG. 3] Transversal filter 10 of FIG. 1 or FIG. 5
It is a figure showing 3.

FIG. 4 is a conceptual diagram showing a digital wireless transmission system.

FIG. 5 is a diagram showing the configuration of a conventional demodulator.

6 is a diagram showing the control signal generation circuit 103 and tap coefficient limiting circuit 106 of FIG. 5. FIG.

FIG. 7: Signa in the present invention and a conventional demodulator
FIG. 2 is a diagram showing true characteristics.

[Explanation of symbols]

1 Input terminal 2 Output terminal 11 Demodulator 12 Transversal filter type equalizer 101
A/D converter 102 Transversal filter 103
Control signal generation circuit 104 Tap coefficient limit value switching circuit 105
Asynchronous detection circuit 106 Tap coefficient limiting circuits 21 to 23 Flip-flop circuits 24 to 26
Exclusive OR circuits 27-29 Up-down counter circuits 30-3
2 Limiter circuits 33-34 Flip-flop circuits 35-37
Digital multiplier 38 Digital adder 107 Modulating device 108 Transmitting device 109 Receiving device 110 Demodulating device

Claims (2)

[Claims] 1. A demodulation device used on the demodulation side of a digital wireless communication system and equipped with a transversal filter type equalizer for equalizing propagation distortion, comprising: an asynchronization detection circuit for detecting desynchronization of a demodulator; A control signal generation circuit that generates tap coefficients of the transversal filter type equalizer and two types of tap coefficient limit values for the synchronization and asynchronous times of the demodulator are set in advance, and based on the output of the asynchronous detection circuit. , and a tap coefficient limit value switching circuit that switches between the two types of tap coefficient limit values. 2. The demodulator according to claim 1, wherein the tap coefficient limit value switching circuit changes the tap coefficients other than the center tap of the transversal filter to 1 when the output of the asynchronization detection circuit indicates asynchronization of the demodulator. A demodulator, characterized in that it operates to limit tap coefficients to a smaller value and not limit tap coefficients when the output indicates synchronization of the demodulator.