JPH04273165A - Manufacture of lateral double-diffusion type mosfet - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a lateral MOSFET which can suppress increase of ON-resistance while preventing breakdown and deterioration of characteristic of a gate insulating film by lowering the electrical field between gate and drain. CONSTITUTION:A lateral MOSFET is manufactured by forming a gate 3 in the predetermined region at the surface of a semiconductor substrate 1 having a first conductivity type via gate insulating films 2, 15, a base region 4 having a second conductivity type and drain regions 7, 11 having the first conductivity type are formed using this gate 3 and a source region 5 of the first conductivity type is formed in this base region 4. In this case, after doping an impurity of the first conductivity type to the surface of the semiconductor substrate 1, impurity is diffused in such a manner that smooth distribution of concentration of this impurity may be obtained, in order to form a drain region 11 of the first conductivity type. Otherwise, using a field oxide film 19 to a part of a gate insulating film 15, the film gradually becomes thick as it goes to the drain regions 7, 11 from the source region 4.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is a lateral double-diffused MOSFET that can suppress an increase in on-resistance while preventing deterioration of MOSFET characteristics caused by a high electric field between the drain and gate.
The present invention relates to a method for manufacturing an SFET.

0002

2. Description of the Related Art An example of a conventional horizontal double diffusion MOSFET is shown in FIG. In FIG. 17, 1 is N
This is an N- type epitaxial layer formed on a + or P+ type silicon substrate, and a polysilicon film 3 (hereinafter referred to as a gate as appropriate) is formed on a predetermined region of the surface of this epitaxial layer 1 via a SiO2 film 2. 3) is formed. Reference numerals 4 and 5 designate a P type base region and an N+ type source region which are formed in a self-aligned manner by a double diffusion method using an SiO2 film 2, a polysilicon film 3, and a mask (not shown). Reference numeral 6 represents a base contact for electrical connection to the base region 4, and reference numeral 7 represents an N+ type drain contact region (hereinafter referred to as drain contact 7 as appropriate). Finally, an interlayer insulating film 8 such as PSG is formed.
A drain electrode 9 and a source electrode 10 are formed via them.

Horizontal double diffusion MOSF with the above configuration
When a positive voltage is applied to the gate 3 of ET, P below the gate 3
An inversion layer is formed on the surface of the shaped base region 4 and current flows therethrough. At this time, the N-type epitaxial layer 1 under the gate 3
An accumulation layer is formed on the surface of the device, resulting in a reduction in on-resistance.

Next, when the gate voltage is below the threshold voltage, the MO
The operation when the SFET is in the cutoff state will be explained. When a drain voltage is applied, a depletion layer is formed at the junction between the P type base region 4 and the N- type epitaxial layer 1 as shown by the broken line K in FIG. At this time, gate 3 acts as a field plate, and N below gate 3
The surface of the − type epitaxial layer 1 is depleted. In other words, the voltage between the drain and the gate causes the N-
A depletion layer is formed on the surface of the epitaxial layer 1. especially,
When the gate insulating film 2 is thin, the electric field between the drain and the gate becomes strong, and the electric field becomes highest near the drain contact region 7 as shown at point A in FIG.

[0005] This high electric field causes the following disadvantages. That is, the gate insulating film 2 may break down due to the high electric field, which may cause destruction of the MOSFET. Furthermore, due to the high electric field, the N-type epitaxial layer 1 at point A breaks down, many electron-hole pairs are generated, and the MOSFET is destroyed. Characteristics may deteriorate.

FIG. 18 is a diagram showing an example of a conventional horizontal double diffusion MOSFET that solves this problem. Since its main structure is the same as that of the MOSFET shown in FIG. 17, the same components are given the same reference numerals and the explanation thereof will be omitted, but the following points are different.

That is, in the structure shown in FIG. 17, the gate 3 and the drain contact 7 have a portion where they overlap in the vertical direction, whereas in the structure shown in FIG. The surface of the N-epitaxial layer 1 between the N-type epitaxial layer 1 and the drain contact 7 is covered with an interlayer insulating film 8.

In this way, if the gate 3 and the drain contact 7 are formed at separate positions, the electric field (especially the maximum electric field) at point A is suppressed compared to the configuration shown in FIG. As a result, destruction of the gate insulating film 2 and deterioration of characteristics are prevented.

[0009]

[Problem to be solved by the invention] However, FIG.
In the conventional lateral double-diffused MOSFET shown in FIG. No accumulation layer is formed on the surface. Therefore, a new problem occurs in that a parasitic series resistance as shown by R in FIG. 18 occurs and the on-resistance increases.

In particular, in the case of a high breakdown voltage MOSFET, since it is necessary to lower the impurity concentration of the N-type epitaxial layer 1 in order to increase the breakdown voltage, the increase in on-resistance becomes particularly noticeable.

An object of the present invention is to provide a method for manufacturing a lateral double-diffused MOSFET that can suppress an increase in on-resistance while reducing the electric field between the gate and drain to prevent breakdown of the gate insulating film and deterioration of characteristics. Our goal is to provide the following.

0012

[Means for Solving the Problems] To explain one embodiment in conjunction with FIGS. 1, 7 and 14, the present invention provides gate insulation in a predetermined region on the surface of a semiconductor substrate 1 of a first conductivity type. A gate 3 is formed through the film 2, and a base region 4 of the second conductivity type and a drain region 11 of the first conductivity type are formed on the surface of the semiconductor substrate 1 using the gate 3 as a mask. The present invention is applied to a method of manufacturing a lateral double-diffused MOSFET by forming a source region 5 of the first conductivity type within the lateral double-diffused MOSFET. In the first aspect of the invention, the surface of the semiconductor substrate 1 is doped with an impurity of the first conductivity type, and then the impurity is diffused so that the concentration distribution of the impurity changes smoothly. 11 achieves the above objectives. Further, in the invention of claim 2, after forming an oxide film on the surface of the semiconductor substrate 1,
A field oxide film that is thicker than the surrounding oxide film is formed on a part of this oxide film by selective oxidation method, and a gate 3 is formed so as to straddle both these oxide films and the field oxide film, so that the source region 4 and the drain region are The above-mentioned object is achieved by forming the gate insulating film 15 whose thickness gradually increases toward the direction of the gate insulating film 15. Furthermore, in the invention of claim 3, after forming an oxide film on the surface of the semiconductor substrate 1, a field oxide film having a thicker thickness than the surrounding area is formed on a part of this oxide film by a selective oxidation method, and these oxide films and By forming the gate 3 so as to straddle both of the field oxide films, a gate insulating film 15 is formed whose thickness increases smoothly from the source region 4 toward the drain region 11, and the semiconductor layer on the drain region 11 side is further formed. The above objective is achieved by doping the surface of the substrate with an impurity of the first conductivity type and then diffusing the impurity so that the impurity concentration distribution changes smoothly to form the drain region 11 of the first conductivity type. be done.

[0013]

[Operation]-Claim 1- The drain region 11 of the first conductivity type formed on the surface of the semiconductor substrate 1 of the first conductivity type is formed so that its impurity concentration distribution changes smoothly. Electrode 3
The electric field underneath changes smoothly, and the electric field between the gate and drain is relaxed. On the other hand, since the drain region 11 is formed using the gate 3 formed on the surface of the semiconductor substrate 1 as a mask, the gate 3 and the drain region 11
are formed very close together. -Claim 2- Since the gate insulating film 15 is formed so that its film thickness increases smoothly from the source region to the drain region, the field plate effect caused by the gate electrode 3 is alleviated on the drain side. The electric field under the gate electrode 3 changes smoothly, and the electric field between the gate and the drain is relaxed. On the other hand, since the drain region 7 is formed using the gate 3 formed on the surface of the semiconductor substrate as a mask, the gate 3 and the drain region 7 are formed very close to each other. -Claim 3- While the gate insulating film 15 is formed so that its film thickness increases smoothly from the source region to the drain region, the impurity concentration distribution of the drain region 11 formed on the surface of the semiconductor substrate 1 is Since the gate electrode 3 is formed so that it changes smoothly, the field plate effect caused by the gate electrode 3 is alleviated on this drain side, and the gate electrode 3
The electric field underneath changes smoothly, and the electric field between the gate and drain is relaxed. On the other hand, since the thickness of the gate insulating film 15 increases smoothly from the base region 4 toward the drain region 11, the surface accumulation layer formed when the MOSFET is turned on also decreases smoothly. On the other hand, in the region where the surface accumulation layer gradually weakens, the drain region 11
Since the impurity concentration increases smoothly, the parasitic series resistance from the base region 4 to the drain region 11 can be made very low.

[0014] In the section of means and effects for solving the above-mentioned problems that explains the structure of the present invention, figures of embodiments are used to make the present invention easier to understand. It is not limited to.

[0015]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. -First Example- FIG. 1 is a diagram showing a MOSFET manufactured by a first example of the method for manufacturing a horizontal double diffusion MOSFET according to the present invention. In the following description, the same reference numerals are given to the same components as in the conventional example described above, and the description thereof will be simplified.

The difference between the conventional example and this embodiment is that the MOSFET of this embodiment has a drain region 11 in which the impurity concentration distribution changes smoothly. That is, in this embodiment, an N-type drain region 11 is formed in a predetermined region on the surface of the N- type epitaxial layer 1 that is different from the P-type base region 4, and the N+-type drain contact region 7 is It is formed on the surface of the drain region 11. The N-type drain region 11 is formed so that its impurity concentration distribution changes smoothly at the boundary with the N-type epitaxial layer 1. Further, in this embodiment, like the conventional example shown in FIG. 17, the gate 3 and the drain contact 7 have a vertically overlapping portion.

Next, a first embodiment of the method for manufacturing a horizontal double diffusion MOSFET according to the present invention will be described with reference to FIGS. 2 to 6. (1) Gate Formation (FIG. 2) After growing an N- type epitaxial layer 1 on an N+ or P+ type silicon substrate (not shown), an SiO2 film 2, which will become a gate insulating film, is formed on its surface by an oxidation process. Furthermore, using a mask (not shown), a polysilicon film 3 serving as a gate is formed in a predetermined region on the surface of the SiO2 film 2.

(2) Base and drain formation (Fig. 3,
(FIG. 4) P-type and N-type impurities are doped into the base region 4 and drain region 11 on the surface of the N-type epitaxial layer 1 using the gate 3 and a mask (not shown) (FIG. 3). Next, the P-type and N-type impurities are diffused at high temperature for a long time to form P-type base region 4 and N-type drain region 11. Conditions such as the temperature and diffusion time of the diffusion process are appropriately selected so that the impurity concentration distribution changes smoothly as shown in FIG. 5 at the boundary between the N-type drain region 11 and the N-type epitaxial layer 1. .

(3) Formation of sources, contacts, etc. (FIG. 6) Using the gate 3 as a mask, the gate insulating film 2 is etched. Next, a predetermined region on the surface of the base region 4 and a predetermined region on the surface of the drain region 11 are doped with impurities and diffused to form the N+ type source region 5, the P+ type base contact region 6, and the N+ type drain contact region. form 7. Finally, the PS which becomes the interlayer insulating film 8
A G film is deposited, contact holes are made at predetermined locations, and aluminum (Al) electrodes (drain electrode 9, source electrode 10) are formed.

By the manufacturing method described above, a horizontal double diffusion MOSFET as shown in FIG. 1 can be manufactured. Here, in this embodiment, the N-type drain region 11 and the N-
Since the impurity concentration distribution at the boundary with the epitaxial layer 1 changes smoothly, the electric field under the gate electrode 3 also changes smoothly. Therefore, the field plate effect caused by the gate 3 as in the conventional example is alleviated (particularly on the drain side), and the concentration of electric field near the N+ type drain contact region 7 can be suppressed, and electron-hole pairs (hot carriers) can reduce the occurrence of Therefore, according to this embodiment, it is possible to prevent breakdown of the gate insulating film 2, breakdown of the N-type epitaxial layer 1, breakdown of the MOSFET due to hot carriers, and deterioration of characteristics as in the conventional example.

Furthermore, in this embodiment, the gate 3 and the drain
Since the structure is such that the contact 7 overlaps with the contact 7, it is possible to suppress an increase in parasitic series resistance and on-resistance as in the conventional example in which the gate 3 and the drain contact 7 are formed apart.

In particular, in the case of a high voltage MOSFET, N-
While it is necessary to reduce the concentration of the type epitaxial layer 1, in order to obtain good ohmic contact characteristics, N+
It is necessary to increase the concentration of the shaped drain contact region 7, and there is a strong tendency for electric field concentration and on-resistance to increase near the drain contact, so the effect of forming the drain region 11 as in this example is is big.

-Second Example- FIG. 7 shows a horizontal double diffusion MOSFET manufactured by a second example of the method for manufacturing a horizontal double diffusion MOSFET according to the present invention.
It is a figure showing FET. The difference between this embodiment and the first embodiment described above is that instead of the drain region 11 of the first embodiment, the thickness of the gate insulating film is made different between the source (base) side and the drain side. be. That is, in this embodiment, the thickness of the gate insulating film (SiO2 film) 15 in the vicinity of the N+ type drain contact region 7 is formed to be thicker than in other parts, and the film thickness is smooth at the boundary. It's changing. Note that in this embodiment as well, as in the conventional example shown in FIG.
It has a portion where the contacts 7 overlap vertically.

Next, a second embodiment of the method for manufacturing a horizontal double diffusion MOSFET according to the present invention will be described with reference to FIGS. 8 to 13. (1) Oxide film formation (FIG. 8) After growing an N- type epitaxial layer 1 on an N+ or P+ type silicon substrate (not shown), an oxide film 18 is formed on its surface by an oxidation process. Next, a Si3N4 film 17 is formed on the surface of the oxide film 18, and a portion thereof is removed.

(2) Field oxide film formation (FIG. 9)
Using the Si3N4 film 17 as a mask, LOCOS (LOCOS)
A field oxide film (insulating film) 19 is formed by al oxidation of silicon. This field oxide film 19 is integrated with the surrounding oxide film 18,
The oxide film 18 is thicker than the oxide film 18, and about half of the film thickness is buried in the N-type epitaxial layer 1. Further, the field oxide film 19 is made of Si3N4
It grows laterally from the edge of the membrane 17, and the cross-sectional shape of this biting portion 19a is similar to that of a bird's beak.
The film thickness changes smoothly as shown in bird's beak). Therefore, this biting portion 19a is also called a bird's beak. The film thickness distribution of this field oxide film 19 can be controlled by thermal oxidation conditions.

(3) Gate formation (FIGS. 10 and 11)
After removing the Si3N4 film 17 from the insulating films 18 and 19 (see FIG. 10), the gate 3 is removed using a mask (not shown).
A polysilicon film is formed on the insulating films 18 and 19 (see FIG. 11). This gate 3 is formed in a region spanning both thin oxide film 18 and field oxide film 19.

(4) Formation of base, source, drain, etc. (FIGS. 12 and 13) Field oxide film 19 other than the area where gate 3 is formed
is removed by etching. Next, a P type base region 4, an N+ type source region 5, and an N+ type contact region 7 which is a drain region are formed using a double diffusion method, and further a P+ type base contact region 6 is formed. Finally, after removing the oxide film 18 using the gate 3 as a mask, a PSG film that will become the interlayer insulating film 8 is deposited, contact holes are opened at predetermined locations, and each aluminum (Al) electrode (drain electrode 9
, a source electrode 10) is formed.

By the manufacturing method described above, a horizontal double diffusion MOSFET as shown in FIG. 7 can be manufactured. In this embodiment, since the thickness of the gate insulating film 15 increases smoothly from the source side to the drain side, the electric field under the gate electrode 3 also changes smoothly. Therefore, the field plate effect caused by the gate 3 as in the conventional example is alleviated on the drain side, suppressing the concentration of electric field near the N+ type drain contact region 7, and suppressing the generation of electron-hole pairs (hot carriers). can be reduced. Therefore, according to this embodiment, the same effects as those of the first embodiment described above can be obtained.

Furthermore, since this embodiment also has a structure in which the gate 3 and drain contact 7 overlap, parasitic series resistance and on-off are avoided, unlike in the conventional example in which the gate 3 and drain contact 7 are formed apart. It is possible to suppress an increase in resistance.

-Third Example- FIG. 14 shows a horizontal double diffusion MOSFET manufactured by a third example of the method for manufacturing a horizontal double diffusion MOSFET according to the present invention.
It is a figure showing SFET. The MOSFET of this example is
This embodiment combines the features of the first embodiment and the second embodiment described above.

That is, in this embodiment, an N-type drain region 11 is formed in a predetermined region on the surface of the N- type epitaxial layer 1 that is different from the P-type base region 4, and the N+-type drain contact region 7 is This N type drain region 1
It is formed on the surface of 1. The N-type drain region 11 is
It is formed so that the impurity concentration distribution changes smoothly at the boundary with the N-type epitaxial layer 1. Furthermore, in this embodiment, the thickness of the gate insulating film (SiO2 film) 15 in the vicinity of the N-type drain region 11 is formed thicker than in other parts, and the film thickness changes smoothly at the boundary. ing. Note that in this embodiment as well, the gate 3 and the drain contact 7 have a vertically overlapping portion, similar to the conventional example shown in FIG.

Next, a third embodiment of the method for manufacturing a horizontal double diffusion MOSFET according to the present invention will be described with reference to FIGS. 15 and 16. (1) Oxide film and gate formation After growing an N- type epitaxial layer 1 on an N+ or P+ type silicon substrate (not shown), an SiO2 film 18 is formed on its surface by an oxidation process. Next, SiO2
A Si3N4 film 17 is formed on the surface of the film 15, and a portion thereof is removed. Next, using the Si3N4 film 17 as a mask,
A field oxide film (insulating film) 19 is formed by LOCOS. Further, after removing the Si3N4 film 17 from above the insulating films 18 and 19, a polysilicon film which will become the gate 3 is formed on the insulating films 18 and 19 using a mask not shown. This gate 3 consists of a thin oxide film 18 and a field oxide film 1.
9 is formed in the area spanning both sides. Note that the above steps are similar to those in the second embodiment described above, and illustration thereof is omitted.

(2) Base and drain formation (FIG. 15)
) Field oxide film 1 other than the part where gate 3 is formed
9 is removed by etching. Next, using the gate 3 and a mask (not shown), P-type and N-type impurities are doped into locations on the surface of the N-type epitaxial layer 1 that will become the base region 4 and drain region 11. Furthermore, the P-type and N-type impurities are diffused for a long time under high temperature to form the P-type base region 4 and the N-type drain region 11.
form.

(3) Formation of sources, contacts, etc. (FIG. 16) Using the gate 3 as a mask, the gate insulating film 2 is etched. Next, a predetermined region on the surface of the base region 4 and a predetermined region on the surface of the drain region 11 are doped with impurities and diffused to form the N+ type source region 5 and the P+ type base region.
A contact region 6 and an N+ type drain contact region 7 are formed. Finally, after removing the oxide film 18 using the gate 3 as a mask, a PSG film that will become the interlayer insulating film 8 is deposited, contact holes are opened at predetermined locations, and each aluminum (Al
) electrodes (drain electrode 9, source electrode 10) are formed.

Therefore, according to this embodiment, the first and second
The same effects as in the embodiment can be obtained.

In particular, in this embodiment, the optimum on-resistance can be obtained by appropriately selecting the impurity concentration distribution of the drain region 11 and the rate of change in the film thickness of the gate insulating film 153. This is due to the following reasons. That is, when proceeding from the base region 4 to the drain region 11, as the thickness of the gate insulating film 15 increases smoothly, the surface accumulation layer formed when the MOSFET is turned on also decreases smoothly. On the other hand, in a region where the surface accumulation layer gradually weakens, the impurity concentration in the drain region increases smoothly. As a result, a current path from the base region 4 to the drain region 11 can be secured, and parasitic series resistance can be suppressed to the utmost.

Note that the horizontal double diffusion MOSFET of the present invention
The details of the manufacturing method are not limited to the above embodiments, and various modifications are possible.

[0038]

As described in detail above, according to the present invention, the impurity concentration distribution in the drain region can be smoothly changed, or the thickness of the gate electrode can be formed so that it becomes thicker toward the drain region. Therefore, the electric field under the gate electrode changes smoothly, and the field plate effect due to the gate electrode can be alleviated on the drain side. Therefore, it suppresses the concentration of electric field between the gate and drain as in the conventional case, and prevents damage to the gate insulating film and MOS
Deterioration of FET characteristics can be prevented. Moreover,
Since the drain region is formed using the gate as a mask, the gate and drain regions are formed close to each other, suppressing increases in parasitic series resistance and on-resistance that would occur if the gate and drain regions were formed apart. be able to.

[Brief explanation of the drawing]

FIG. 1: Horizontal double diffusion MOS, which is the first embodiment of the present invention.
Horizontal double diffusion MOS manufactured by FET manufacturing method
It is a sectional view showing FET.

[Fig. 2] Horizontal double diffusion MOS which is the first embodiment of the present invention
FIG. 3 is a process diagram for explaining a method for manufacturing an FET.

FIG. 3 is a process diagram following FIG. 2.

FIG. 4 is a process diagram following FIG. 3.

FIG. 5: Horizontal double diffusion MOS according to the first embodiment of the present invention.
FIG. 3 is a diagram showing an impurity concentration distribution inside the drain region of the FET.

FIG. 6 is a process diagram following FIG. 4.

FIG. 7: Horizontal double diffusion MOS, which is a second embodiment of the present invention.
Horizontal double diffusion MOS manufactured by FET manufacturing method
It is a sectional view showing FET.

FIG. 8: Horizontal double diffusion MOS, which is a second embodiment of the present invention.
FIG. 3 is a process diagram for explaining a method for manufacturing an FET.

FIG. 9 is a process diagram following FIG. 8.

FIG. 10 is a process diagram following FIG. 9.

FIG. 11 is a process diagram following FIG. 10.

FIG. 12 is a process diagram following FIG. 11.

FIG. 13 is a process diagram following FIG. 12.

FIG. 14: Horizontal double diffusion MO which is the third embodiment of the present invention
Horizontal double diffusion MO manufactured by SFET manufacturing method
FIG. 3 is a cross-sectional view showing an SFET.

FIG. 15: Horizontal double diffusion MO which is the third embodiment of the present invention.
FIG. 3 is a process diagram for explaining a method for manufacturing an SFET.

FIG. 16 is a process diagram following FIG. 15.

FIG. 17 is a cross-sectional view showing an example of a conventional horizontal double diffusion MOSFET.

FIG. 18 is a sectional view showing another example of a conventional horizontal double diffusion MOSFET.

[Explanation of symbols]

1 N-type epitaxial layers 2, 15 Gate insulating film 3 Gate 4 P-type base region 5 N+-type source region 6 P+-type base contact region 7 N+-type drain contact region 9 Drain electrode 10 Source electrode 11 N-type drain region 17 Si3N4 film 18 Oxide film 19 Field oxide film

Claims (3)

[Claims] 1. A gate is formed in a predetermined region on the surface of a semiconductor substrate of a first conductivity type via a gate insulating film, and using this gate as a mask, a base region of a second conductivity type and a base region of a second conductivity type are formed on the surface of the semiconductor substrate. A method for manufacturing a lateral double-diffused MOSFET by forming a drain region of one conductivity type and a source region of the first conductivity type in the base region, wherein impurities of the first conductivity type are added to the surface of the semiconductor substrate. A lateral double-diffusion MOSF characterized in that a drain region of the first conductivity type is formed by doping the impurity and then diffusing the impurity so that the impurity concentration distribution changes smoothly.
ET manufacturing method. 2. A gate is formed in a predetermined region on the surface of a semiconductor substrate of a first conductivity type via a gate insulating film, and using this gate as a mask, a base region of a second conductivity type and a base region of a second conductivity type are formed on the surface of the semiconductor substrate. In the method of manufacturing a horizontal double diffused MOSFET by forming a drain region of one conductivity type and a source region of the first conductivity type in the base region, after forming an oxide film on the surface of the semiconductor substrate. A field oxide film that is thicker than the surrounding oxide film is formed on a part of this oxide film by selective oxidation, and a gate is formed so as to straddle both these oxide films and the field oxide film, thereby connecting the source region to the drain region. A method for manufacturing a lateral double-diffused MOSFET, characterized by forming a gate insulating film whose thickness gradually increases toward the opposite side. 3. A gate is formed in a predetermined region on the surface of the semiconductor substrate of the first conductivity type via a gate insulating film, and using the gate as a mask, a base region of the second conductivity type and a base region of the second conductivity type are formed on the surface of the semiconductor substrate. In the method of manufacturing a horizontal double diffused MOSFET by forming a drain region of one conductivity type and a source region of the first conductivity type in the base region, after forming an oxide film on the surface of the semiconductor substrate. A field oxide film that is thicker than the surrounding oxide film is formed on a part of this oxide film by selective oxidation, and a gate is formed so as to straddle both these oxide films and the field oxide film, thereby connecting the source region to the drain region. After forming a gate insulating film whose film thickness gradually increases toward the opposite side, and doping the surface of the semiconductor substrate on the drain region side with an impurity of the first conductivity type, the concentration distribution of this impurity changes smoothly. Horizontal double diffusion M characterized in that a drain region of the first conductivity type is formed by diffusing impurities into
Method of manufacturing OSFET.