JPH04271520A - Multi-pll synthesizer - Google Patents

Abstract

PURPOSE:To make the reference frequency of a PLL synthesizer high and to vary the frequency range in a simple and delicate way even in an MHz band. CONSTITUTION:This synthesizer is provided with less number of components and adjustment positions such that the output of a mixer 17 for which the outputs of VCOs 14, 21 of two sets of PLLs sharing the reference freqnency of a single fixed oscillator 11 are connected via a fixed frequency divider 18 is fed back to the one PLL.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-resolution multi-PLL synthesizer used for frequency control of in-vehicle telephones, radio equipment, etc.

Generally, a frequency phase locked (PLL) circuit is
When a 1/N frequency divider (N is the frequency division number) is inserted between the voltage controlled oscillator (VCO) and the phase comparator (P/C), the VC
The oscillation frequency of O is N times the output frequency (reference frequency) fr of the reference oscillation source, but the above P/C is equal to the reference frequency and V
The phase difference with the frequency fD obtained by dividing the CO output frequency by N is detected, and the DC voltage smoothed by passing through a low-pass filter (LPF) is applied as a control voltage for the VCO output frequency, and the VCO output frequency is is operated so that it matches the phase of the reference frequency.

By the way, in a PLL synthesizer that selectively switches between multiple channels, the switching time between channels increases in proportion to the number of channels. In addition, when the channel spacing is narrow, the reference frequency must be lowered in order to finely vary the VCO output frequency, so the time constant of the low-pass filter LPF must be adjusted as a condition for maintaining the frequency stability of the PLL. You'll have to take a big shot. As a result, it takes a long time for the frequency to stabilize when switching channels, and the VCO changes at fine frequency intervals.
Not only is it difficult to change the output frequency, but it is also extremely difficult in practice to control a wide variable frequency range.

On the other hand, if two sets of conventional PLL systems are adopted as a high-resolution frequency synthesizer and a low frequency interval below the reference frequency is selected, when selecting and switching multiple channels, the frequency division number N of the frequency divider is The variable range becomes too large, and there is a risk that the carrier-to-noise ratio will deteriorate.

For example, the conventional double loop shown in FIG.
The synthesizer appropriately controls the frequency division ratio of the programmable dividers 3-1 and 3-2, which are variable frequency dividers.
A fixed oscillator 1 in which a step change in the synthesized frequency, that is, a change in the channel spacing frequency, oscillates different frequencies.
The difference between the reference frequencies is -1 and 1-2.

Although this circuit can produce fine step changes in frequency, it requires the provision of individual fixed oscillators with different oscillation frequencies, which is troublesome in terms of synthesizer production.

What is more inconvenient is that the relationship between the frequency division numbers N1 and N2 of the variable frequency dividers 3-1 and 3-2 and the reference frequency for the synthesized frequency fr2N2 -fr1N1 output from the FILT is determined by, for example, a filter. Assuming that the lower side wave is extracted, the above synthesized frequency is fr
1(N2 - N1) + N2 (fr2 - fr1) holds, and if N1 and N2 are each changed by the same number of division numbers, the frequency can be changed in steps of fr2 - fr1, but if you have as many as 800 channels, If you try to change it, if fr1=800KHz, VCO1
The range in which the frequency of 5-1 should be changed is fr1N1
= 800 x 800 = 640 MHz, which means that it cannot be put to practical use.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to obtain a multi-PLL synthesizer that eliminates the above-mentioned conventional drawbacks, reduces the number of parts and adjustment parts of the entire synthesizer, and enables simple and fine frequency variation. be.

[0009]

[Means for solving the problem] A reference oscillation frequency is commonly taken out from a single fixed oscillator, and the frequency division ratio of the variable frequency divider which is the frequency variable means of each PLL system is individually changed,
A fixed frequency divider is inserted on one input side of a mixer that adds the outputs of both PLL systems.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the circuit configuration of a multi-PLL synthesizer of the present invention, in which 11 is a fixed oscillator that outputs a single common oscillation frequency, 12 is a phase comparator, 13 and 20 are low-pass filters, and 14 is a fixed oscillator that outputs a single common oscillation frequency. , 21 is a voltage controlled oscillator, 15, 2
2 is a variable frequency divider, 16 is a band pass filter for removing unnecessary waves, 17 is a mixer, 18 is a fixed frequency divider for dividing the number of steps, and PLL1 and PLL2 are phase synchronization systems, respectively.

In the above circuit configuration, the output frequency f0
Assuming that 1 extracts the lower side wave by BPF16,
f01=N1 fr +N2 fr /N3, and the output frequency can be varied in steps of fr/N3. Also, since N1 and N2 can be varied independently, if the frequency division number N1 of the variable frequency divider 15 is set to 32 and that of the variable frequency divider 22 is set to 25, the number of channels that can be set is 32 x 25 = 800 channels. The frequency variable range of VCO1 is 8
00 KHz×32=25.6 MHz, and it can be seen that this value is sufficiently practical compared to the conventional example.

0012

[Effects of the invention] Since the reference frequency is obtained from a single fixed oscillator, the number of parts is reduced and the trouble of making adjustments individually is eliminated.Each variable frequency divider can be varied independently, and one VCO output can be adjusted separately. Since mixing is performed outside the PLL via a fixed frequency divider, the amount of change in the output frequency of the VCO can be selected to a low minimum step frequency below the reference frequency.
A high reference frequency can be adopted. As a result, lock-up time can be extremely shortened without impairing spurious properties.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a multi-PLL synthesizer according to the present invention.

FIG. 2 is a circuit configuration diagram of a conventional double PLL synthesizer.

[Explanation of symbols]

Claims (1)

[Claims] Claim 1: An independent PLL having a separate reference oscillation source.
In a double PLL synthesizer in which two systems are coupled by a feedback circuit that compares the frequency obtained by mixing the voltage-controlled oscillation frequencies of each PLL system with the reference frequency of one PLL system, the reference oscillation source is A single fixed oscillator shared by a set of PLL systems and a frequency divider that divides the output frequency of the voltage controlled oscillator of one PLL system and the output of the voltage controlled oscillator of the other PLL system are added respectively. the mixer, and a circuit that feeds back the mixed frequency of the mixer to the first phase comparator via the first variable frequency divider of the one PLL system to which the mixed frequency of the mixer is applied via a band-pass filter. A multi-PLL synthesizer characterized by: