JPH04278570A - Lead frame for ic use - Google Patents
Lead frame for ic useInfo
- Publication number
- JPH04278570A JPH04278570A JP4044091A JP4044091A JPH04278570A JP H04278570 A JPH04278570 A JP H04278570A JP 4044091 A JP4044091 A JP 4044091A JP 4044091 A JP4044091 A JP 4044091A JP H04278570 A JPH04278570 A JP H04278570A
- Authority
- JP
- Japan
- Prior art keywords
- leads
- lead
- line use
- lead frame
- power line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008878 coupling Effects 0.000 abstract description 6
- 238000010168 coupling process Methods 0.000 abstract description 6
- 238000005859 coupling reaction Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 5
- 230000010355 oscillation Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明はＩＣ用リードフレームに
関し、特に高周波ＩＣ用リードフレームに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for an IC, and more particularly to a lead frame for a high frequency IC.
【０００２】0002
【従来の技術】従来、高周波ＩＣに使用されるリードフ
レームは、図３に示すように通常チップ裏面をグランド
電位とするためにチップマウント面５をグランドライン
用リード３により外部に引出し、且つそのリード３はパ
ッケージの四隅のうちのいずれかに設置されていた。2. Description of the Related Art Conventionally, as shown in FIG. 3, a lead frame used in a high frequency IC usually has a chip mounting surface 5 extended to the outside through a ground line lead 3 in order to set the back surface of the chip to a ground potential. Lead 3 was placed at one of the four corners of the package.
【０００３】その理由はパッケージが実装される回路基
板のグランド電極は大きなパターンを用い、高周波に於
いてもインピーダンスが十分低くなる様設計されていて
、グランドライン用リード３がパッケージの四隅以外に
設置されると実効基板の設計が比較的困難になる為であ
った。The reason for this is that the ground electrode of the circuit board on which the package is mounted uses a large pattern and is designed to have sufficiently low impedance even at high frequencies, and the ground line lead 3 is installed outside the four corners of the package. This was because designing an effective board would be relatively difficult.
【０００４】0004
【発明が解決しようとする課題】この従来のリードフレ
ームは、回路基板への実装の便宜さはあるものの、パッ
ケージの四隅に設置されたグランドライン用リードは高
周波信号リード間，或いは高周波信号リードと電源リー
ド間の電磁結合に対する遮へい効果が極めて少なく、高
周波用ＩＣチップを装着した場合に安定動作が難しく、
発振を起こすことがあった。[Problems to be Solved by the Invention] Although this conventional lead frame is convenient for mounting on a circuit board, the ground line leads installed at the four corners of the package are between the high frequency signal leads or between the high frequency signal leads. The shielding effect against electromagnetic coupling between power supply leads is extremely low, making it difficult to operate stably when a high frequency IC chip is installed.
Oscillation may occur.
【０００５】[0005]
【課題を解決するための手段】本発明のＩＣ用リードフ
レームは、チップマウント面に接続した少なくとも２個
以上のグランドライン用リードをパッケージの四隅以外
に設定し、且つグランドライン用リードは信号ライン用
リードと電源ライン用リードの間に設定している。[Means for Solving the Problems] In the IC lead frame of the present invention, at least two or more ground line leads connected to the chip mounting surface are set outside the four corners of the package, and the ground line leads are connected to the signal line. It is set between the power line lead and the power line lead.
【０００６】[0006]
【実施例】次に本発明について図面を参照して説明する
。図１（ａ）は本発明の第１の実施例の部品図、図１（
ｂ）は６ピンパッケージに使用した場合のリードフレー
ムの実装図である。リードフレームのチップマウント面
５に接続された２個のグランドライン用リード３が信号
ライン用リード２と電源ライン用リード４の間に設定さ
れており、信号ライン用リード２と電源ライン用リード
４の電磁結合を減少させる作用がある。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1(a) is a parts diagram of the first embodiment of the present invention, FIG.
b) is a mounting diagram of the lead frame when used in a 6-pin package. Two ground line leads 3 connected to the chip mounting surface 5 of the lead frame are set between the signal line lead 2 and the power line lead 4. It has the effect of reducing electromagnetic coupling.
【０００７】図２（ａ）は本発明の第２の実施例の部品
図、図２（ｂ）は８ピンパッケージに使用した場合のリ
ードフレームの実装図である。本実施例のリードフレー
ムは第１の実施例と同様にチップマウント面５ａに接続
された２個のグランドライン用リード３が信号ライン用
リード２と電源ライン用リード４の間に設定されており
、信号ライン用リード２と電源ライン用リード４の電磁
結合を減少させる作用がある。FIG. 2(a) is a component diagram of a second embodiment of the present invention, and FIG. 2(b) is a mounting diagram of a lead frame when used in an 8-pin package. In the lead frame of this embodiment, two ground line leads 3 connected to the chip mounting surface 5a are set between the signal line lead 2 and the power line lead 4, as in the first embodiment. This has the effect of reducing electromagnetic coupling between the signal line lead 2 and the power line lead 4.
【０００８】第１，第２の実施例で、５００ＭＨｚ帯利
得３５ｄＢの広帯域増幅器に於いて発振によるＩＣ特性
の歩留りが７５％から１００％に改善された。In the first and second embodiments, the yield of IC characteristics due to oscillation was improved from 75% to 100% in a wideband amplifier with a 500 MHz band gain of 35 dB.
【０００９】[0009]
【発明の効果】以上説明したように本発明は、チップマ
ウント面に接続した少なくとも２個以上のグランドライ
ン用リードをパッケージの四隅以外に設定し且つグラン
ドライン用リードを信号ライン用リードと電源ライン用
リードの間に設定しているので、高周波信号リード間或
いは高周波信号リードと電源ライン用リード間の電磁結
合に対する遮へい効果が大きい５００ＭＨｚ帯利得３５
ｄＢの広帯域増幅器に於いて発振によるＩＣ特性の歩留
りが７５％から１００％に改善された。パッケージを実
装する基板上のグランド電極の寸法に制約があるので高
周波に於けるインピーダンスは十分低減できないものの
、総合的に見てＩＣの高周波特性の歩留り向上を可能に
した。As explained above, the present invention provides at least two ground line leads connected to the chip mounting surface at locations other than the four corners of the package, and the ground line leads are connected to the signal line leads and power supply lines. 500MHz band gain 35, which has a large shielding effect against electromagnetic coupling between high frequency signal leads or between high frequency signal leads and power line leads.
In a dB wideband amplifier, the yield of IC characteristics due to oscillation has been improved from 75% to 100%. Although impedance at high frequencies cannot be reduced sufficiently due to restrictions on the dimensions of the ground electrode on the board on which the package is mounted, overall it has made it possible to improve the yield of high frequency characteristics of ICs.
【図１】（ａ），（ｂ）はそれぞれ本発明の第１の実施
例の部品図および６ピンパッケージに使用した場合の実
装図である。FIGS. 1(a) and 1(b) are a component diagram and a mounting diagram of a first embodiment of the present invention when used in a 6-pin package, respectively.
【図２】（ａ），（ｂ）はそれぞれ本発明の第２の実施
例の部品図および８ピンパッケージに使用した場合の実
装図である。FIGS. 2(a) and 2(b) are a component diagram and a mounting diagram of a second embodiment of the present invention when used in an 8-pin package, respectively.
【図３】従来のＩＣ用リードフレームの一例の部品図で
ある。FIG. 3 is a component diagram of an example of a conventional IC lead frame.
１ フレーム ２ 信号ライン用リード ３ グランドライン用リード ４ 電源ライン用リード ５ チップマウント面 ６ パッケージ本体 ７ ボンディングワイヤ ８ 半導体集積回路チップ 1 Frame 2 Signal line lead 3 Ground line lead 4 Power line lead 5 Chip mount surface 6 Package body 7 Bonding wire 8 Semiconductor integrated circuit chip
Claims (1)
面に一端がそれぞれ接続されている少なくとも２個以上
のグランドライン用リードがパッケージの四角を除くフ
レームの位置に対応して結合され、信号ライン用リード
と電源ライン用リードが前記グランドライン用リードを
挟んで前記フレームで結合されることを特徴とするＩＣ
用リードフレーム。[Claim 1] At least two or more ground line leads each having one end connected to a chip mounting surface on which an IC chip is mounted are connected at positions on the frame excluding the squares of the package, and the signal line leads are and a power line lead are coupled to each other by the frame with the ground line lead interposed therebetween.
lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4044091A JPH04278570A (en) | 1991-03-07 | 1991-03-07 | Lead frame for ic use |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4044091A JPH04278570A (en) | 1991-03-07 | 1991-03-07 | Lead frame for ic use |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04278570A true JPH04278570A (en) | 1992-10-05 |
Family
ID=12580705
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4044091A Pending JPH04278570A (en) | 1991-03-07 | 1991-03-07 | Lead frame for ic use |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04278570A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6319525B1 (en) * | 2017-05-26 | 2018-05-09 | 三菱電機株式会社 | Semiconductor device |
-
1991
- 1991-03-07 JP JP4044091A patent/JPH04278570A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6319525B1 (en) * | 2017-05-26 | 2018-05-09 | 三菱電機株式会社 | Semiconductor device |
| WO2018216219A1 (en) * | 2017-05-26 | 2018-11-29 | 三菱電機株式会社 | Semiconductor device |
| US10923444B1 (en) | 2017-05-26 | 2021-02-16 | Mitsubishi Electric Corporation | Semiconductor device |
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