JPH0427527B2 - - Google Patents

Description

[Detailed Description of the Invention] <Technical Field> The present invention relates to a matrix type liquid crystal display device.
In particular, the present invention relates to the structure of a drive circuit section of a matrix type liquid crystal display device in which an addressing switching transistor is added to each picture element in a matrix type display pattern.

<Prior art> A matrix type liquid crystal display device that uses nonlinear elements to drive liquid crystal display uses thin film transistors for addressing (hereinafter referred to as
Abbreviated as TFT. ) in a matrix, it is possible to obtain a high-contrast display equivalent to static drive even when performing multiplex drive with a small duty ratio, i.e., multiple lines.
TFT active matrix type liquid crystal display devices are known.

Some driving systems for this TFT active matrix type liquid crystal display device have circuit configurations and signal waveforms as shown in FIGS. 5 and 6. In the figure, 11 is a liquid crystal display panel, and a TFT 11c is connected to the intersection of a row electrode 11a and a column electrode 11b as shown in the figure. 11d is the capacitance of the liquid crystal layer. 12 is a row electrode driver mainly consisting of a shift register;
The scanning pulse S is sequentially shifted by the clock φ1 from the gate signal control section 13 and output to each row electrode. When the total scanning period of this row electrode is T and the number of scanning lines is N, the scanning period H is expressed as H=T/N. A pulse voltage having a pulse width equal to this scanning period H is sequentially applied to each row electrode so as to turn on the TFT 11c row by row. 14 is an example electrode driver, which is a drive system that samples and holds data directly to the display panel (hereinafter referred to as panel SH).
(hereinafter referred to as a driver SH drive method) and a drive method in which the column electrode driver has a function of sampling and holding data (hereinafter referred to as a driver SH drive method). As shown in FIG. 7, the panel SH drive type column electrode driver consists of a shift register 31, a sampling switch 32, etc., and clocks data serially sent from the data signal control section 15 at timings corresponding to each column. It is sampled in synchronization with φ2, outputted to the column electrodes sequentially, and written to the liquid crystal layer through the TFT 11c. In this driving method, data sampling and writing into the liquid crystal layer through the TFT 11c are performed within the same horizontal scanning period. Next, using Figures 8 and 9, the driver SH
The drive method will be explained. shift register 41
The sampling switch 42 is turned on in synchronization with the output of the capacitor 43, and a charge corresponding to the data signal is stored in the capacitor 43. Next, a discharge pulse signal located in the first half of the horizontal blanking period is applied to Cl,
The remaining charge is discharged to form a reference state. Next, when a transfer pulse signal located in the latter half of the horizontal blanking period is applied to Cg, the charge stored in the capacitor 43 is transferred to the transistor 44.
is transferred to and output. With the Uko drive method, data is written to the liquid crystal in the next 1H after sampling.

In these driving methods, the time constant for charging the display pixel electrode T _ON =R _ON・C _LC (R _ON is the on-resistance of the transistor, and C _LC is the capacitance of the liquid crystal layer) is compared with the width H of the scanning pulse. It is desirable to set it to be sufficiently small so that sufficient charging is performed until the potential of the display picture element electrode becomes equal to the potential of the data signal waveform. If the charging time constant T _ON is not a sufficiently small value compared to the width H of the scanning pulse, the TFT will turn off before the voltage output to the column electrodes can charge the liquid crystal to the required potential through the TFT. This results in deterioration of display characteristics. Furthermore, in such a state, the voltage applied to the liquid crystal layer changes depending on the value of the charging time constant T _ON , so if there are variations in R _OH and C _CL values for each pixel of the liquid crystal display panel, the effect will be appears in the display contrast, and becomes a major hindrance in displays that require intermediate tones, such as television images.

<Object of the Invention> The present invention has been made in view of the above-mentioned problems in conventional drive circuits for matrix-type liquid crystal display devices, and is novel and useful as it consumes less power and can be easily miniaturized and highly integrated. It is an object of the present invention to provide a structure of a drive circuit for a liquid crystal display device.

<Basic Principles and Examples> Hereinafter, examples will be described in which the drive circuit section of the liquid crystal display device according to the present invention is applied to a liquid crystal television.

FIG. 4 is a waveform diagram illustrating the basic principle of the present invention. The picture element in the i-th row and j-th column will be described below as an example. In FIG. 4, A is the i-th scanning pulse. This scan pulse has a width of 2H, and is a combination of the conventional i-th row scan pulse, Si part, 1H, and the conventional (i-1) row scan pulse, Si-1 part, 1H. Let 2H be the scanning pulse for the i-th row. Figure 4B shows the data signal waveform of the j-th column.
V _i-1 and Vi are data voltages corresponding to the i-1th row and the i-th row, respectively. FIG. 4C shows the charging characteristic (curve lA) according to the conventional driving method when the time constant T _ON for charging the display picture element electrode is not sufficiently smaller than H, and the charging characteristic (curve lA) according to the driving method according to the present invention. Curve lB) is shown. In the case of the conventional driving method, since the i-th scanning pulse is Si, the charging characteristic is as shown by the curve lA in Figure 4C, and charging is performed toward the potential of Vi, but T _ON is not sufficient compared to H. Because it is so small, it can only be charged up to the potential of V _A. On the other hand, in the case of the driving method of the present invention, first S _i-1
At this point, charging is performed toward V _i-1 , and then
The Si part is charged toward Vi, which is the potential of the main body. As a result, the charging characteristic is such that charging is performed to a potential _VB higher than the charging potential _VA in the case of the conventional driving method, as shown by the curve 1B in FIG. 4C. In this way, in the present invention, by expanding the scanning pulse width from the conventional 1H to 1H earlier to make the overall 2H, it is possible to charge the display pixel electrodes without affecting the display position in any way. Even if the constant T _ON is not sufficiently small compared to H, the same effect as setting T _ON =R _ON・C _CL to 1/2 without widening the pulse width can be obtained, and good contrast can be obtained. can. Note that the same effect can be obtained by extending the scanning pulse width from the conventional 1H to the rear by 1H to make the overall width 2H, but in this case, the display is
It shifts down by 1H.

Next, the present invention will be explained according to examples. FIG. 1 is a circuit diagram of a row electrode driver showing one embodiment of the present invention. A case will be described in which the terminals of the row electrodes of the liquid crystal display panel are driven in both left and right end directions, and are driven alternately left and right in time. To set the pulse width of the output signal to 1H for right side extraction, set the R/ terminal to "1", the B/ terminal to "1", the H ₂ / ₁ terminal to "0", and the D/ terminal to "0". Set the terminal to “1”. The timing waveform in that case is shown in FIG. A start pulse signal SP with a width of 4H (Fig. 2A) and a clock signal CL with a period of 1H (Fig. 2B) are input to the flip-flop 61, and the output signal Q
(FIG. 2C) is selected by the clocked inverter 64 and input to the data terminal of the shift register 78. On the other hand, after processing the inverted output of the flip-flop 61 and the start pulse signal SP in a NAND circuit 67, the output signal is transferred to a clocked inverter 6.
9 is selected and input to the reset terminals of flip-flops 71 and 72 (FIG. 2D). A clocked inverter 73 selects a signal (FIG. 2E) obtained by frequency-dividing the clock signal CL by 1/4 by flip-flops 71 and 72, and inputs the selected signal to the clock terminal of a shift register 78. This shift register 78 shifts half bits at a time with respect to the clock signal.
The output signals of the shift register 78 are shown in FIG.
As shown in I, the pulse width is 4H, and the signal is shifted by 1H. On the other hand, the output signal of the OR circuit 76 is an enable signal for the row electrode driver output, and is as shown in FIG. 2F in the settings of this embodiment. 77
is a delay to adjust the timing
It is a circuit. The inverted signal of the first stage output signal (FIG. 2 G) of the shift register 78, the second stage output signal (FIG. 2 H), and the enable signal (delay circuit 7
The NOR signal (currently “0” at the output of 7) is sent to the NOR circuit 8.
0, and the pulse signal is level-shifted and output by the level shifter 81 (Fig. 2 J)
becomes the scanning side drive signal applied to the row electrodes of the liquid crystal display panel. In this way, the finally output signals are shifted one by one with a pulse width of 1H, as shown in FIG. 2J and K. That is, this output is equivalent to the odd numbered or even numbered signal extracted from the signal that is successively shifted one bit at a time. The signal at the terminal 86 is a signal generated by triggering the output signal of the nth stage of the shift register 78 at the rising edge of the inverted output signal of the flip-flop 71, and is used as the start pulse signal input for the next row electrode driver when a plurality of row electrode drivers are continuously connected. input to the SP terminal.

Next, adjust the pulse width of the output signal for right side extraction.
To set 2H, set R/ terminal to “1” and B/
Set the terminal to "1", the H ₂ / ₁ terminal to "0", the D/ terminal to "0", and the terminal to "1". The timing waveform in that case is shown in FIG. The data input signal and clock input signal of the shift register 78 are the same as when the pulse width of the output signal is set to 1H (FIGS. 2A-E and 3A-E).
When the H ₂ / ₁ terminal is set to "1", the output (enable signal) of the delay circuit 77 becomes "0" as shown in FIG. 3F. As shown in FIG. 3J and K, the final output signal is a signal with a pulse width of 2H that is sequentially shifted. This signal is the output signal when the pulse width is set to 1H, which is expanded temporally by 1H, and the overall pulse width is 2H.

Thus, the row electrode driver of the present invention has H ₂ /
Scanning pulse width can be changed to 1H by simply changing the setting of _H1 terminal.
Alternatively, it can be set to 2H, and good contrast can be obtained even when the time constant T _ON for charging the display picture element electrode is not sufficiently smaller than the horizontal scanning period H.

<Effects of the Invention> As detailed above, the liquid crystal display drive circuit of the present invention includes a switching terminal that allows the width of the scanning pulse signal applied to the row electrodes of the liquid crystal display panel to be selected to either 1H or 2H. are doing. This 2H is an extension of the conventional 1H to 1H earlier, and the voltage drop that occurs due to insufficient charging of the display pixel electrode through the switching transistor, without affecting the display position in any way. It is possible to establish an effective driving method that can reduce the deterioration of display characteristics, and it is possible to achieve low power consumption, miniaturization, and high integration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a row electrode driver showing one embodiment of the present invention. Fig. 2 is a waveform diagram of the main part when the row electrode driver of the embodiment shown in Fig. 1 is set for extraction in both left and right end directions and right end direction, and the scanning pulse width is set to 1H, and Fig. 3 is a similar diagram. Fig. 1 is a waveform diagram of the main part when the row electrode driver is set for extraction in both left and right directions and the scanning pulse width is set to 2H, and Fig. 4 explains the basic principle of the driving method of the present invention. FIG. 3 is a signal waveform diagram of signals of each electrode. Fig. 5 is a block configuration diagram showing the structure of a conventional liquid crystal display device, Fig. 6 is a timing waveform diagram showing the main driving waveforms of the liquid crystal display device shown in Fig. 5, and Fig. 7 is a conventional panel SH drive method. FIG. 8 is a circuit diagram illustrating a column electrode driver of the conventional driver SH driving method, and FIG. 9 is a timing waveform diagram showing drive waveforms in the circuit of FIG. 8. H...Horizontal scanning period, 31, 41, 78...Shift register, 32, 42...Analog switch, 43...Sampling capacitor, 44...
...Transistor, 61, 62, 63, 71, 7
2, 82...flip flop, 64, 65, 6
9, 70, 73, 74, 83, 84...Clocked inverter, 67, 68...NAND circuit, 80
...Noah circuit, 77...Delay circuit, 81...
level shifter.

Claims (1)

[Claims] 1. In a drive circuit for a matrix type liquid crystal display device comprising a liquid crystal display panel in which an addressing switching element is added to each pixel of a matrix type display pattern, a row electrode connected to the switching element of the liquid crystal display panel , a row electrode drive circuit that selectively applies either a signal with a scan pulse width of 1H (H is a horizontal scanning period) or a signal with a scan pulse width of 2H is connected, and the scan pulse width is applied to the row electrode drive circuit.
1. A drive circuit for a liquid crystal display device, comprising a switching terminal for setting either 1H or 2H.