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JPH04261054A - Lead of semiconductor package - Google Patents

Lead of semiconductor package

Info

Publication number
JPH04261054A
JPH04261054A JP1420191A JP1420191A JPH04261054A JP H04261054 A JPH04261054 A JP H04261054A JP 1420191 A JP1420191 A JP 1420191A JP 1420191 A JP1420191 A JP 1420191A JP H04261054 A JPH04261054 A JP H04261054A
Authority
JP
Japan
Prior art keywords
lead
semiconductor package
leads
base end
tip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1420191A
Other languages
Japanese (ja)
Inventor
Masaaki Namatame
生田目 雅章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1420191A priority Critical patent/JPH04261054A/en
Publication of JPH04261054A publication Critical patent/JPH04261054A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a lead of a semiconductor package whose lead tip does not float up even if load is applied in such a fashion that every lead may come into contact with a pattern on a substrate definitely when joining said substrate. CONSTITUTION:A Z-shaped semiconductor's lead is constituted by forming an acute angle between a lead base end section 2a and a lead central part 2b and between the lead central part 32b and a lead tip section 2c.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】この発明は、半導体パッケージの
リードに関し、特に半導体と基板上のパターンをリード
を介して接合する半導体パッケージにおけるリードの形
状に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to leads for semiconductor packages, and more particularly to the shape of leads in semiconductor packages that connect a semiconductor and a pattern on a substrate via the leads.

【0002】0002

【従来の技術】図3は、例えば特開昭60−86893
 号公報に示された従来の半導体パッケージのリードを
示す側面図であり、図において、1は半導体パッケージ
、2はこの半導体パッケージ1の側面より突出するリー
ドである。リード2は、半導体パッケージ1側から、リ
ード基端部2a、リード中央部2b、リード先端部2c
で構成されている。図4(a)、(b)はそれぞれ接合
時の荷重によるリードの変形を示す側面図で、3は基板
、4は基板3上に形成されたパターンである。
2. Description of the Related Art FIG.
1 is a side view showing a lead of a conventional semiconductor package disclosed in the publication; in the figure, 1 is a semiconductor package, and 2 is a lead protruding from the side surface of the semiconductor package 1. FIG. The leads 2 include, from the semiconductor package 1 side, a lead base end portion 2a, a lead center portion 2b, and a lead tip portion 2c.
It consists of 4(a) and 4(b) are side views showing deformation of the lead due to load during bonding, respectively, in which numeral 3 represents a substrate, and 4 represents a pattern formed on the substrate 3.

【0003】従来の半導体パッケージのリードは上記の
ように構成され、例えば図4に示すようにリード2とパ
ターン4を位置決め後、リード2とパターン4を確実に
接触させるように荷重をかけた状態で加熱し、はんだを
溶融させて接合を達成する。
The leads of a conventional semiconductor package are constructed as described above. For example, as shown in FIG. 4, after positioning the leads 2 and patterns 4, a load is applied to ensure that the leads 2 and patterns 4 are in contact with each other. The solder is heated to melt the solder and achieve the bond.

【0004】0004

【発明が解決しようとする課題】電子機器の小型化、高
機能化に伴い半導体パッケージにおいてリードピッチの
微細化が進んでいる。そこで、リードを所定の形状に曲
げるリードフォーミング工程においても高精度化がます
ます要求されるがいまだ十分でなく、現状ではリード形
状のばらつきが発生する形状のばらついたリードを基板
3上のパターン4に接触させるために、半導体パッケー
ジ1に対して矢印A方向に荷重をかける。従来の半導体
パッケージのリード形状は、以上のように、リード基端
部2aとリード中央部2bとが鈍角で交わり、さらにリ
ード中央部2bとリード先端部2cとが鈍角で交わって
いる。このため、図4(a)の図に向って右側のリード
をパターン4に接触させるような荷重をかけると、図4
(a)の図に向って左側のリード先端部2cはすでにパ
ターン4と接触していたので、リード先端部2cパター
ン上をすべる。その結果、リード先端部2cが浮き上が
り、図4(b)のようになってしまう。このような状態
ではんだ付けを行うと信頼性が十分に得られないといっ
た問題点があった。
[Problems to be Solved by the Invention] As electronic devices become smaller and more sophisticated, lead pitches in semiconductor packages are becoming increasingly finer. Therefore, even though higher precision is required in the lead forming process for bending the leads into a predetermined shape, it is still not sufficient. A load is applied to the semiconductor package 1 in the direction of arrow A in order to bring it into contact with the semiconductor package 1 . As described above, in the lead shape of a conventional semiconductor package, the lead base end portion 2a and the lead center portion 2b intersect at an obtuse angle, and the lead center portion 2b and the lead tip end portion 2c intersect at an obtuse angle. Therefore, if a load is applied to bring the lead on the right side into contact with the pattern 4 when facing the diagram in FIG.
Since the lead tip 2c on the left side in the figure (a) was already in contact with the pattern 4, the lead tip 2c slides on the pattern. As a result, the lead tip portion 2c is lifted up, resulting in a situation as shown in FIG. 4(b). If soldering is performed in such a state, there is a problem in that sufficient reliability cannot be obtained.

【0005】この発明は上記のような従来の問題点を解
決するためになされたもので、すべてのリードが基板上
のパターンと確実に接触するような荷重をかけても、リ
ード先端部が浮き上がらない半導体パッケージのリード
を得ることを目的とする。
This invention was made to solve the above-mentioned conventional problems, and even when a load is applied to ensure that all the leads are in contact with the pattern on the substrate, the tips of the leads do not lift up. The aim is to obtain leads for semiconductor packages that are not available.

【0006】[0006]

【課題を解決するための手段】この発明に係る半導体パ
ッケージのリードは、半導体パッケージ側からリード基
端部、リード中央部、及びリード先端部で構成し、リー
ド基端部を接合面に対して実質的に水平に形成すると共
に、リード中央部をリード基端部に対して鋭角をなすよ
うな直線形状とし、さらにリード先端部をリード中央部
に対して鋭角をなすようにしたものである。
[Means for Solving the Problems] A lead of a semiconductor package according to the present invention is composed of a lead base end, a lead center, and a lead tip from the semiconductor package side, and the lead base end is placed against the bonding surface. In addition to being formed substantially horizontally, the lead center portion has a straight line shape making an acute angle with respect to the lead base end portion, and furthermore, the lead tip portion makes an acute angle with respect to the lead center portion.

【0007】[0007]

【作用】この発明による半導体パッケージのリードは、
リード基端部、リード中央部、リード先端部でZ形状を
構成し、複数のリード形状がばらついた際に、すべての
リードが基板上のパターンと確実に接触するような荷重
をかけても、Z形状のリードがバネの役目を果たして余
分な荷重を吸収する。このためリード先端部付近はパタ
ーン上をすべることなく、リード先端部が浮き上がるの
を防止できる。
[Operation] The lead of the semiconductor package according to the present invention is
The base end of the lead, the center of the lead, and the tip of the lead form a Z-shape, and even when multiple lead shapes vary, even if a load is applied to ensure that all the leads are in contact with the pattern on the board, The Z-shaped lead acts as a spring to absorb excess load. Therefore, the vicinity of the lead tip does not slide on the pattern, and the lead tip can be prevented from lifting up.

【0008】[0008]

【実施例】実施例1.図1はこの発明の一実施例による
半導体パッケージのリードを示す側面図であり、図2(
a)、(b)は図1に示すリードを用いた場合の接合時
の荷重によるリードの変形を示したものである1〜4は
上記従来例のものと同様である。この実施例では、TA
Bテープを樹脂モールドしたものを用いた。TABテー
プは厚さ125 μmのポリイミドテープに厚さ35μ
mの銅箔を接着し、その後エッチングにてアウターリー
ド部は巾100 μmのリードを240 本形成した。 インナーリード部を半導体の電極と接合した後樹脂でモ
ールドし、リードフォーミング装置により図1に示すZ
型のリード形状に形成した。ここで、曲げ角度はリード
基端部側からθa=45°、θb=50°とした。
[Example] Example 1. FIG. 1 is a side view showing the leads of a semiconductor package according to an embodiment of the present invention, and FIG.
a) and (b) show the deformation of the lead due to the load during bonding when the lead shown in FIG. 1 is used. 1 to 4 are the same as those of the above conventional example. In this example, T.A.
A resin molded B tape was used. TAB tape is made of 125 μm thick polyimide tape with a thickness of 35 μm.
240 leads each having a width of 100 μm were formed in the outer lead portion by etching. After the inner lead part is bonded to the semiconductor electrode, it is molded with resin, and a lead forming device is used to form the Z as shown in Figure 1.
It was formed into a mold lead shape. Here, the bending angles were θa=45° and θb=50° from the lead base end side.

【0009】形状のばらついたリードを基板3 上のパ
ターン4 に接触させるために、半導体パッケージ1に
、対して荷重をかけるが、図1のリード形状によると、
図2(a)に示すように図に向って右側のリードをパタ
ーン4に接触させるように矢印方向に荷重をかけても、
図に向って左側の先にパターンと接触していたリードの
先端部が浮き上がることはない。これはZ型の形状のリ
ードがバネの役目をはたすためであり、すべてのリード
2が基板3上のパターン4と確実に接触し、図2(b)
のように接合できる。
In order to bring the leads of varying shapes into contact with the pattern 4 on the substrate 3, a load is applied to the semiconductor package 1, but according to the lead shape shown in FIG.
Even if a load is applied in the direction of the arrow so that the lead on the right side in the figure contacts the pattern 4 as shown in FIG. 2(a),
The tip of the lead that was in contact with the pattern on the left side as viewed in the figure does not lift up. This is because the Z-shaped leads act as a spring, and all the leads 2 are securely in contact with the pattern 4 on the substrate 3, as shown in FIG. 2(b).
It can be joined like this.

【0010】0010

【発明の効果】以上のように、この発明によれば、半導
体パッケージの側面から突出して設けられる半導体パッ
ケージのリードにおいて、上記半導体パッケージ側から
リード基端部、リード中央部、及びリード先端部で構成
し、上記リード基端部を接合面に対して実質的に水平に
形成すると共に上記リード中央部を上記リード基端部に
対して鋭角をなすような直線形状とし、さらにリード先
端部をリード中央部に対して鋭角をなすようにしたこに
より、リード形状がばらついた際にすべてのリードが基
板上のパターンと確実に接触するような荷重をかけても
、リード先端部が浮き上がらず、信頼性の高い接合部を
形成することができる半導体パッケージのリードが得ら
れる効果がある。
As described above, according to the present invention, in a lead of a semiconductor package that is provided protruding from the side surface of the semiconductor package, from the semiconductor package side to the lead base end, the lead center part, and the lead tip end. The base end of the lead is formed substantially horizontally with respect to the bonding surface, the central part of the lead is formed in a linear shape forming an acute angle with respect to the base end of the lead, and the tip end of the lead is formed into By making an acute angle with respect to the center, even if a load is applied to ensure that all the leads are in contact with the pattern on the board when the lead shape varies, the lead tips will not lift up, ensuring reliability. This has the effect of providing semiconductor package leads that can form a bonding portion with high properties.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】この発明の実施例1による半導体パッケージの
リードを示す側面図である。
FIG. 1 is a side view showing leads of a semiconductor package according to a first embodiment of the present invention.

【図2】実施例1によるリードの接合時の荷重による変
形を示す説明図である。
FIG. 2 is an explanatory diagram showing deformation due to load during bonding of the lead according to Example 1.

【図3】従来の半導体パッケージのリードを示す側面図
である。
FIG. 3 is a side view showing leads of a conventional semiconductor package.

【図4】従来のリードの接合時の荷重による変形を示す
説明図である。
FIG. 4 is an explanatory diagram showing deformation due to load during bonding of a conventional lead.

【符号の説明】[Explanation of symbols]

1  半導体パッケージ 2  リード 2a  リード基端部 2b  リード中央部 2c  リード先端部 1 Semiconductor package 2 Lead 2a Lead base end 2b Lead center part 2c Lead tip

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  半導体パッケージの側面から突出して
設けられる半導体パッケージのリードにおいて、上記半
導体パッケージ側からリード基端部、リード中央部、及
びリード先端部で構成し、上記リード基端部を接合面に
対して実質的に水平に形成すると共に上記リード中央部
を上記リード基端部に対して鋭角をなすような直線形状
とし、さらに上記リード先端部を上記リード中央部に対
して鋭角をなすようにしたことを特徴とする半導体パッ
ケージのリード。
1. A lead of a semiconductor package that is provided protruding from a side surface of the semiconductor package, which is composed of a lead base end, a lead center, and a lead tip from the semiconductor package side, and the lead base end is connected to a bonding surface. The leads are formed substantially horizontally with respect to each other, and the central portions of the leads are formed in a linear shape forming an acute angle with respect to the base end portions of the leads, and the leading ends of the leads are formed at an acute angle with respect to the central portions of the leads. A lead in semiconductor packages characterized by:
JP1420191A 1991-02-05 1991-02-05 Lead of semiconductor package Pending JPH04261054A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1420191A JPH04261054A (en) 1991-02-05 1991-02-05 Lead of semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1420191A JPH04261054A (en) 1991-02-05 1991-02-05 Lead of semiconductor package

Publications (1)

Publication Number Publication Date
JPH04261054A true JPH04261054A (en) 1992-09-17

Family

ID=11854502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1420191A Pending JPH04261054A (en) 1991-02-05 1991-02-05 Lead of semiconductor package

Country Status (1)

Country Link
JP (1) JPH04261054A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6114759A (en) * 1998-04-23 2000-09-05 Nec Corporation Semiconductor package
JP2015026791A (en) * 2013-07-29 2015-02-05 新電元工業株式会社 Semiconductor device and lead frame
WO2021157045A1 (en) * 2020-02-07 2021-08-12 三菱電機株式会社 Semiconductor device and method for manufacturing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6114759A (en) * 1998-04-23 2000-09-05 Nec Corporation Semiconductor package
JP2015026791A (en) * 2013-07-29 2015-02-05 新電元工業株式会社 Semiconductor device and lead frame
WO2021157045A1 (en) * 2020-02-07 2021-08-12 三菱電機株式会社 Semiconductor device and method for manufacturing semiconductor device
JPWO2021157045A1 (en) * 2020-02-07 2021-08-12

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