JPH04266063A - Manufacture of solid-state image pick-up device - Google Patents

Abstract

PURPOSE:To prevent read-out of impurities of a positive electric charge accumulation layer which is formed on a surface of a photo diode formed on a semiconductor substrate and diffusion to a lower portion of a gate electrode and then enable a gate voltage of the read-out gate electrode to be maintained normally. CONSTITUTION:Ions are implanted for a plurality of times and a positive electric charge accumulation layer 17 is formed at a region where impurities which are implanted by each ion implantation are synthesized. Impurities are implanted at a location which is away from a read-out gate electrode 13 for self-alignment by a certain distance AO for at least once out of the ion implantation. Therefore, even if impurities are diffused due to heat treatment, etc., impurities are not diffused at high concentration at a lower portion of a readout gate electrode 13, thus enabling read-out to be made without increasing the gate voltage.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is a CCD (charge coupled device)
The present invention relates to a method of manufacturing a solid-state imaging device, and particularly relates to a method of manufacturing a solid-state imaging device having a structure in which a positive charge storage layer is formed on the surface of a photodiode in which signal charges are generated by photoelectric conversion.

0002

2. Description of the Related Art A structure in which a positive charge storage layer (hole storage layer) is provided in order to improve sensitivity and reduce dark current is known as a structure of a light receiving section of a solid-state imaging device. For example, when an n-type silicon substrate is used as this positive charge storage layer,
This is a p+ type impurity diffusion region formed on the further surface of the n+ type impurity diffusion region provided on the surface side of the p type well, and holes are accumulated in this positive charge storage layer to generate the sensor surface. Current and dark current can be suppressed.

FIG. 6 is a sectional view showing the structure of a light receiving section of a conventional CCD solid-state imaging device. To briefly explain this structure, a p-type well region 62 is formed on an n-type silicon substrate 61, and a read gate electrode 63 is formed on a part of the well region 62 via an insulating film (not shown). Ru. Since the light-receiving section consisting of a photodiode is formed adjacent to the readout gate electrode 63 in terms of layout, ions are implanted in self-alignment with the readout gate electrode 63, and the n+
type impurity diffusion region 64 and p+ which becomes a positive charge storage layer.
A type impurity diffusion region 65 is formed. The n+ type impurity diffusion region 64 is formed at a deeper position than the p+ type impurity diffusion region 65.

0004

However, in the conventional solid-state imaging device having the structure shown in FIG. 6, impurities in the p+ type impurity diffusion region 65 formed on the surface of the substrate as shown by the broken line in the figure due to heat treatment, etc. may diffuse to the bottom of the read gate electrode 63. As a result, during readout, a problem arises in that the signal charges cannot be read out sufficiently unless the gate voltage supplied to the readout gate electrode 63 is made higher than necessary.

Therefore, in view of the above-mentioned technical problem, the present invention prevents the diffusion of impurities constituting the positive charge storage layer toward the readout gate electrode, thereby making it possible to read out signal charges using a predetermined gate voltage. An object of the present invention is to provide a method for manufacturing a solid-state imaging device.

[0006]

[Means for Solving the Problems] In order to achieve the above-mentioned object, the method for manufacturing a solid-state imaging device of the present invention includes ion implantation of an impurity of a first conductivity type in self-alignment with a readout gate electrode formed on a substrate. a step in which a part of the photodiode is formed in the substrate by the impurity; and at least one ion implantation of the second conductivity type impurity among the plurality of ion implantations of the second conductivity type impurity. is spaced apart from the edge of the readout gate electrode, and a positive charge storage layer is formed on a part of the surface of the photodiode by diffusion of the second conductivity type impurity introduced by the multiple ion implantations. The method is characterized by comprising a step of forming.

[0007]

[Operation] In the method for manufacturing a solid-state imaging device of the present invention, unlike conventional manufacturing methods, a positive charge storage layer is not formed by a single ion implantation, but impurities are synthesized by multiple ion implantations. A positive charge storage layer is formed on the surface side of the photodiode. By performing at least one of the multiple ion implantations at a distance from the end of the readout gate electrode, even if impurities diffuse into the lower part of the readout gate electrode, the distance from the end of the gate electrode can be increased. The concentration becomes thinner by the amount of ion implantation that is left open, and signal charges can be read out without increasing the voltage supplied to the gate electrode more than necessary.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to the drawings. First, the structure of a CCD image sensor formed by the solid-state imaging device manufacturing method of the present invention will be explained with reference to FIGS. 1 and 2.

FIG. 2 is a diagram showing the overall layout of a CCD image sensor. An imaging region 21 is formed on the silicon substrate, and within the imaging region 21, a plurality of light receiving sections 22 are formed in a matrix. In the light receiving section 22, signal charges are generated according to the incident light. A vertical register 23 is formed for each vertical column of light receiving sections 22, respectively. A readout section 24 is formed between the vertical register 23 and each light receiving section 22, and a readout gate electrode is formed in this readout section 24. The read gate electrode of the read section 24 is shared with the transfer electrode of the vertical register 23, for example. Transfer electrodes (not shown) of the vertical register 23 are supplied with required drive signals ΦIM1 to ΦIM4. This drive signal Φ
Signal charges of the vertical register 23 are transferred by IM1 to ΦIM4. Each vertical register 23 is electrically connected to a horizontal resistor 25 at its end. In this horizontal register 25, charge is transferred for each horizontal line by drive signals ΦH1 and ΦH2. An output section 26 is provided at the terminal end of the horizontal register 25, and a video signal corresponding to the incident light is output from the output section 26.

FIG. 1 is a diagram showing a cross-sectional structure near a readout section of such a CCD image sensor. CCD
The image sensor is formed using an n-type silicon substrate 11, and a p-type well region 12 is formed on the n-type silicon substrate 11. Surface 1 of silicon substrate 11
A readout gate electrode 13 is formed in a desired pattern on 1a via an insulating film (not shown). This read gate electrode 13 is made of, for example, a polysilicon layer or a combination of a polysilicon layer and a silicide layer.

N-type impurity ions are implanted into the p-type well region 12 in self-alignment with the read gate electrode 13, and an n+-type impurity region 14 is formed by the ion implantation. This n+ type impurity region 14 functions as a part of a photodiode, and accumulates signal charges (electrons) generated in response to incident light.

Impurities are implanted into the surface side of this n+ type impurity region 14 by two ion implantations, and a positive charge storage layer 17 is also formed. For more information,
First, a first ion implantation is performed on the end portion 13s of the read gate electrode 13 in a self-aligned manner, and a first p+ type impurity region 15 is formed. Next, a mask or the like is formed at a distance A0 from the end 13s of the read gate electrode 13, and a second p+ type impurity region 1 is formed at this position by second ion implantation.
6 is formed. These first p+ type impurity regions 1
5 and the second p+ type impurity region 16 are each diffused by heat treatment or the like. End 13a by distance A0
The impurity in the second p+ type impurity region 16 which is spaced apart finally diffuses to the boundary 18. Further, the impurity in the first p+ type impurity region 15 formed in alignment with the end portion 13a is finally diffused to the boundary 19. As a result, Figure 1
The shaded area in the middle is the overlapping area of the first and second p+ type impurity regions 15 and 16, and this overlapping area becomes the positive charge storage layer 17. The boundary 19 of the first p+ type impurity region 15 is located below the readout gate electrode 13, but the boundary 18 of the second p+ type impurity region 16 is located below the readout gate electrode 13. is not enough. Therefore, in the region below the read gate electrode 13, only the impurity of the first p+ type impurity region 15 is diffused, but it does not function as a substantial positive charge storage layer 17, and the region below the read gate electrode 13 is diffused. This eliminates the need to make the voltage higher than necessary.

Next, two specific examples of a method for manufacturing a solid-state imaging device having a structure in which the positive charge storage layer 17 is formed by multiple ion implantations will be described.

The first example is illustrated in FIGS. 3 and 4 and utilizes sidewalls provided at the ends of the gate electrode.

First, as shown in FIG. 3, ion implantation is performed to implant n-type impurities in self-alignment with the readout gate electrode 32 formed on the p-type well region 31, and then p-type impurities are implanted. Ion implantation is performed. As a result, an impurity region 33 into which n-type impurities are introduced
and an impurity region 34 doped with p-type impurities are both formed in self-alignment with the readout gate electrode 32, an n-type impurity region 33 is formed at a slightly deeper position in the well region 31, and a p-type impurity region 34 is formed in a self-aligned manner with the readout gate electrode 32. It is formed near the surface of the well region 31.

Next, an insulating film such as a silicon oxide film is formed on the entire surface, and the silicon oxide film is left on the end portion 32a of the read gate electrode 32 by etching or the like. This end 3
The sidewall 35 made of the insulating film remaining on 2a is
It functions as a part of a mask for spacing a certain distance from the end portion 32a. After forming the sidewalls 35, a second p-type impurity ion implantation is performed in a self-aligned manner using the sidewalls 35 and the readout gate electrode 32 as masks. By this ion implantation, an impurity region 36 into which p-type impurities are introduced is formed slightly deeper than the impurity region 34 and on the surface side of the impurity region 33 . This impurity region 36 is formed at a position farther from the read gate electrode 32 than the impurity region 34 by the distance of the sidewall 35 .

After that, the required annealing is performed, and the annealing causes the impurities to diffuse from the impurity regions 33 and 36, and the area of the well surface where the impurity regions 33 and 36 overlap functions as a substantial positive charge storage layer. do. At this time, the boundary expands as shown in FIG. 1, but since the position of the second ion implantation is set far from the readout gate electrode 32 by the sidewall 35, the boundary is formed after the diffusion. The position of the positive charge storage layer stops at the bottom of the sidewall 35 and does not reach the bottom of the read gate electrode 32. Therefore, there is no need to increase the voltage supplied to the readout gate electrode 32, and sufficient readout of signal charges can be achieved with the required gate voltage.

FIG. 5 is a diagram showing a specific example of another manufacturing method. A read gate electrode 42 is provided on the p-type well region 41.
is formed, and an n-type impurity region 43 and a p-type impurity region 44 are formed by ion implantation from a direction perpendicular to the read gate electrode 42. n-type impurity region 43
functions as a part of a photodiode, and a p-type impurity region 44 is formed on the surface side of the n-type impurity region 43. Next, the p-type impurity region 44 is formed by the first ion implantation in the vertical direction, but the second ion implantation is performed in the oblique direction, and the read gate electrode 4
2 and self-aligned, a p-type impurity region 45 is formed at a position separated from the read gate electrode 42 by a fixed interval. Even if the p-type impurity region 45 formed by the second ion implantation from the oblique direction is diffused, it does not reach the bottom of the read gate electrode 42. Therefore, the position of the substantial positive charge storage layer composed of the combined region of the impurity region 45 and the impurity region 44 does not extend under the read gate electrode 42, and as a result,
Signal charges can be reliably read out with a required gate voltage.

In the above embodiment, at the position A0 where the second ion implantation is spaced apart from the end of the readout gate electrode, the impurity introduced during the second ion implantation does not reach the lower part of the readout gate electrode due to heat treatment or the like. This is the position where a positive charge storage layer is formed in alignment with the end of the read gate electrode by synthesis with the impurity introduced in the first ion implantation. In addition, in the above embodiment, the number of times of multiple ion implantations was set to two, but
The present invention is not limited to this, and the positive charge storage layer may be formed by further ion implantation many times. Furthermore, in order to implant ions at a certain distance from the end of the readout gate electrode, we have explained an example in which sidewalls 35 and oblique ion implantation are used as a specific example, but of course it is also possible to use a mask material such as a resist mask. It is.

[0020]

As described above, in the method for manufacturing a solid-state imaging device of the present invention, impurities from multiple ion implantations overlap to form a positive charge storage layer on the surface side of the photodiode. By arranging at least one of the multiple ion implantations away from the edge of the readout gate electrode, even if impurities diffuse to the lower part of the readout gate electrode, the separated ion implantation However, the impurity concentration will be low. Therefore, there is no need to make the voltage supplied to the read gate electrode higher than necessary, and reliable readout of signal charges can be achieved with the required gate voltage.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a solid-state imaging device manufactured by an example of the solid-state imaging device manufacturing method of the present invention.

FIG. 2 is a schematic plan view of a solid-state imaging device to which an example of the method for manufacturing a solid-state imaging device of the present invention is applied.

FIG. 3 is a process cross-sectional view showing the first ion implantation by self-alignment in an example of the method for manufacturing a solid-state imaging device of the present invention.

FIG. 4 is a process cross-sectional view showing the second ion implantation after sidewall formation in an example of the method for manufacturing a solid-state imaging device of the present invention.

FIG. 5 is a process cross-sectional view schematically showing ion implantation at different angles in another example of the method for manufacturing a solid-state imaging device of the present invention.

[Fig. 6] Cross-sectional view showing an example of a conventional solid-state imaging device

[Explanation of symbols] 11...Silicon substrate 12...Well region 13, 32, 42...Reading gate electrode 14, 33, 4
3... N-type impurity regions 15, 34, 44... P-type impurity regions (first ion implantation) 16, 36, 45... P-type impurity regions (second ion implantation) 17... Positive charge accumulation layer

Claims (1)

[Claims] 1. A step in which impurities of a first conductivity type are ion-implanted in self-alignment with a readout gate electrode formed on a substrate, and a part of a photodiode is formed in the substrate by the impurities; Among the ion implantations of the second conductivity type impurity, at least one ion implantation of the second conductivity type impurity is at a constant distance from the end of the readout gate electrode, and A method for manufacturing a solid-state imaging device, comprising the step of forming a positive charge storage layer on a part of the surface of the photodiode by diffusing impurities of a second conductivity type introduced by implantation.