JPH0425144A - Semiconductor device using tape for three-layer tab and manufacture of tape for three-layer tab - Google Patents
Semiconductor device using tape for three-layer tab and manufacture of tape for three-layer tabInfo
- Publication number
- JPH0425144A JPH0425144A JP2130489A JP13048990A JPH0425144A JP H0425144 A JPH0425144 A JP H0425144A JP 2130489 A JP2130489 A JP 2130489A JP 13048990 A JP13048990 A JP 13048990A JP H0425144 A JPH0425144 A JP H0425144A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductor
- tape
- ground
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000010030 laminating Methods 0.000 claims abstract 2
- 239000004020 conductor Substances 0.000 claims description 57
- 238000005530 etching Methods 0.000 claims description 13
- 238000007747 plating Methods 0.000 claims description 10
- 239000012777 electrically insulating material Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 1
- 239000011810 insulating material Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 7
- 238000007772 electroless plating Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は配線パターン層および電源層、接地層の3層か
ら成る3層T A B用テープを用いた半導体装置及び
こ九に用いる3層TAB用テープの製造方法に関する。Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a semiconductor device using a three-layer T A B tape consisting of three layers: a wiring pattern layer, a power supply layer, and a ground layer. The present invention relates to a method for manufacturing a TAB tape.
(従来技術)
プレスあるいはエツチング加工によって製造したリード
フレームと半導体チップとをワイヤボンディングによっ
て接続した半導体装置では、リードフレームに形成でき
るリードの加工限界およびワイヤボンディングできるポ
ンディングピッチの制約から200ビン以−にのビン数
を有するパッケージを製造することが困難である。(Prior Art) In a semiconductor device in which a lead frame manufactured by pressing or etching and a semiconductor chip are connected by wire bonding, the lead frame is manufactured by wire bonding. It is difficult to manufacture packages with a number of bins.
このため、より高密度に配線パターンが形成でき、ワイ
ヤボンディングによるよりも多ピンの接続が可能な′J
″AB用テープを用いて半導体チップとリードフレーム
とを接続した半導体装置が従来提供されている。For this reason, it is possible to form wiring patterns with higher density, and it is possible to connect more pins than with wire bonding.
``Semiconductor devices in which a semiconductor chip and a lead frame are connected using AB tape have been conventionally provided.
この1”AB用テープはベースフィルム上に信号ライン
、電源ライン、接地ライン等所要の配線パターンを形成
したもので、配線パターンのインナーリードを半導体チ
ップに一括ボンディングで接続し、配線パターンのアウ
ターリードをリードフレームに接続する。This 1" AB tape has the required wiring patterns such as signal lines, power lines, and ground lines formed on a base film. The inner leads of the wiring pattern are connected to the semiconductor chip by bulk bonding, and the outer leads of the wiring pattern are bonded to the semiconductor chip. Connect to the lead frame.
TAB用テープにはこのようにベースフィルム上に導体
層を1層設けたものと、ベースフィルムの下面に共通に
用いる接地プレーンなどを設けたものがある。There are two types of TAB tapes: one in which a single conductor layer is provided on a base film, and one in which a commonly used ground plane is provided on the lower surface of the base film.
(発明が解決しようとする課題)
TAB用テープを用いた場合は、」1記のように通常の
リードフレームとくらべて容易に多ピン化が可能である
が、従来のT A 13用テープでは入出力端子数がさ
らに増大したような場合はリード本数の増大に対処でき
なくなること、また半導体パッケージの高速化等の電気
的特性の改善の要求に十分に対処できないといった問題
点がある。(Problem to be Solved by the Invention) When using TAB tape, it is easier to increase the number of pins compared to a normal lead frame as described in 1. However, with conventional TAB tape, If the number of input/output terminals increases further, there are problems in that it will not be possible to cope with the increase in the number of leads, and it will not be possible to sufficiently meet the demands for improved electrical characteristics such as higher speeds of semiconductor packages.
そこで、本発明は上記問題点を解消すべくなされたもの
であり、その目的とするところは、半導体チップの電極
数が増大した場合でもパッケージのり−ド本数をさほど
増加させずに済ますことができて半導体装置を小型化で
き、また電気的特性を向上させることができる3層TA
B用テープを用いた半導体装置及び3層TAB用テープ
の好適な製造方法を提供しようとするものである。Therefore, the present invention has been made to solve the above problems, and its purpose is to make it possible to do so without significantly increasing the number of package boards even when the number of electrodes on a semiconductor chip increases. A three-layer TA that can reduce the size of semiconductor devices and improve electrical characteristics.
The present invention aims to provide a semiconductor device using B tape and a suitable method for manufacturing a three-layer TAB tape.
(課題を解決するための手段)
本発明は」1記目的を達成するため次の構成をそなえる
。(Means for Solving the Problems) In order to achieve the object described in item 1, the present invention has the following configuration.
すなわち、信号ライン、電源ライン、接地ラインを有す
る配線パターン層、および前記電源ラインと接続される
電源層、前記接地ラインと接続される接地層が層間に電
気的絶縁材料を介在させて積層さ汎て成る33層71”
A B用テープを用いて半導体チップとリードフレー
ムとを接続したことを特徴とする。That is, a wiring pattern layer having a signal line, a power supply line, and a ground line, a power supply layer connected to the power supply line, and a ground layer connected to the ground line are laminated with an electrically insulating material interposed between the layers. 33 layers 71"
It is characterized in that the semiconductor chip and the lead frame are connected using A and B tape.
また、3mTΔ13用テープの製造方法において、積層
した際に中間層となる導体層に所定の導体パターンを形
成した4−F面に導体層を有するFPCに、片面に導体
層を右するFPC用基板を積層し、−にFの露出面およ
び中間層に導体層を有する積層体を設け、該積層体の上
下面を貫通してスルーホールを設けるとともに、めっき
等によりスルーホール内壁に導体部を形成して前記導体
層間を電気的に接続し、積層体の露出面の導体層をエツ
チングして所定パターンの導体パターンを形成すること
を特徴とし、また、上下面に導体層を有するFPC用基
板にスルーホールを設け、めっき等によりスルーホール
内壁に導体部を設けて前記導体層間を電気的に接続する
とともに、前記上下面の導体層をエツチングして所定の
導体パターンを形成し、−方の導体パターンの露出面を
電気的絶縁材料によって被覆して絶縁層を形成し、該絶
縁層の必要個所をエツチングにより除去して導体パター
ンを部分的に露出させ、該絶縁層に導体層を被着して、
絶縁層の表面に導体層を設けるとともに前記導体パター
ンと電気的な接続をとることを特徴とする。In addition, in the manufacturing method of the tape for 3mTΔ13, an FPC board with a conductor layer on one side is added to an FPC having a conductor layer on the 4-F side with a predetermined conductor pattern formed on the conductor layer that becomes an intermediate layer when laminated. are laminated, a laminate having a conductor layer on the exposed surface of F and the intermediate layer is provided at -, a through hole is provided passing through the upper and lower surfaces of the laminate, and a conductor portion is formed on the inner wall of the through hole by plating etc. The conductor layer is electrically connected between the conductor layers by etching the conductor layer on the exposed surface of the laminate to form a conductor pattern in a predetermined pattern. A through hole is provided, and a conductor portion is provided on the inner wall of the through hole by plating or the like to electrically connect the conductor layers, and the conductor layers on the upper and lower surfaces are etched to form a predetermined conductor pattern, and a conductor on the negative side is formed. The exposed surface of the pattern is covered with an electrically insulating material to form an insulating layer, the necessary portions of the insulating layer are removed by etching to partially expose the conductive pattern, and a conductive layer is applied to the insulating layer. hand,
It is characterized in that a conductor layer is provided on the surface of the insulating layer and electrically connected to the conductor pattern.
(実施例)
以下、本発明の好適な実施例につき図面に基づいて詳細
に説明する。(Embodiments) Hereinafter, preferred embodiments of the present invention will be described in detail based on the drawings.
〔3層T A B用テープを用いた半導体装置〕第1図
は、本発明に係る3層TAB用テープを用いた半導体装
置の一実施例を示す説明図である。[Semiconductor device using three-layer TAB tape] FIG. 1 is an explanatory diagram showing an embodiment of a semiconductor device using a three-layer TAB tape according to the present invention.
図で10はリードフレームのアウターリード、11はイ
ンナーリード、12はダイアタッチである。半導体チッ
プ13はダイアタッチ12」二に接合され、3層′J゛
ハB用テープ14を介してインナーリード」−1と接続
されている。In the figure, 10 is an outer lead of the lead frame, 11 is an inner lead, and 12 is a die attach. The semiconductor chip 13 is bonded to the die attach 12 and is connected to the inner lead 1 through a three-layer tape 14.
3層1’ A B用テープ14は信号ライン16、電源
ライン18、接地ライン20を同一面内で所定パターン
に形成した配線パターン層22と、電源層24および接
地層26の3層構造から成る。配線パターン層22およ
び電源層24、電源層24および接地層26間はそれぞ
れ絶縁層によって電気的に絶縁されている。前記配線パ
ターン層22の電源ライン18は電源層24と、接地ラ
イン20は接地層26とそれぞれ電気的導通をとって接
続される。The three-layer 1' A B tape 14 has a three-layer structure including a wiring pattern layer 22 in which a signal line 16, a power line 18, and a ground line 20 are formed in a predetermined pattern on the same plane, a power layer 24, and a ground layer 26. . The wiring pattern layer 22 and the power layer 24, and the power layer 24 and the ground layer 26 are electrically insulated by insulating layers. The power line 18 of the wiring pattern layer 22 is electrically connected to the power layer 24, and the ground line 20 is electrically connected to the ground layer 26.
配線パターンW122、電源層24、接地層26の層配
置類はとくに限定されるものではないが、実施例の3
Wj ′r A 13用テープ]−4では最」二層が配
線パターン層22、rlll?D層が電源層24、最下
層が接地層26で、各層間にはポリイミドの絶縁層を介
在させている。3WTAB用テープ14は接着剤28を
介してダイアタッチ12に接着する。Although the layer arrangement of the wiring pattern W122, the power layer 24, and the ground layer 26 is not particularly limited,
Wj'r A 13 tape]-4, the second layer is the wiring pattern layer 22, rllll? The D layer is a power supply layer 24, the bottom layer is a ground layer 26, and a polyimide insulating layer is interposed between each layer. The 3WTAB tape 14 is adhered to the die attach 12 via an adhesive 28.
第2図は、3層’I” A B用テープ14および半導
体チップ13、インナーリード11.の平面配置を示す
説明図でこれらの接続状態を示す。FIG. 2 is an explanatory diagram showing the planar arrangement of the three-layer 'I'' A B tape 14, the semiconductor chip 13, and the inner leads 11, and shows how these are connected.
図のように3層1’AB用テープ14は半導体チップ1
3を囲む枠状に配置され、3層TAB用テープ14の内
周部において、半導体チップ13と配線パターン層に設
けた信号ライン16、電源ライン18、接地ライン20
がボンディングされる。As shown in the figure, the three-layer 1'AB tape 14 is attached to the semiconductor chip 1.
A signal line 16, a power supply line 18, and a ground line 20 provided on the semiconductor chip 13 and the wiring pattern layer are arranged in a frame shape surrounding the semiconductor chip 13 and on the inner circumference of the three-layer TAB tape 14.
is bonded.
半導体チップ13の端子中には信号ライン16に接続さ
れるもの、電源ライン18、接地ライン20に接続され
るものが混在しているがら、3層TA、B用テープ14
を作成する際には半導体チップ13の仕様にしたがって
配線パターンを形成しておく。Among the terminals of the semiconductor chip 13, some are connected to the signal line 16, some are connected to the power supply line 18, and some are connected to the ground line 20, but the three-layer TA and B tape 14
When producing the semiconductor chip 13, a wiring pattern is formed in accordance with the specifications of the semiconductor chip 13.
配線パターン層22のうち信号ライン16は半導体チッ
プL3とリードフレームのインナーリードIJとを直接
接続するから、信号ライン16は配線パターン層を横断
するように形成され、3層”I’ A B用テープ14
の外周縁から外方に延出したリード端においてインナー
リード11に接続される。Since the signal line 16 in the wiring pattern layer 22 directly connects the semiconductor chip L3 and the inner lead IJ of the lead frame, the signal line 16 is formed to cross the wiring pattern layer, and is connected to the third layer "I" A B. tape 14
It is connected to the inner lead 11 at the lead end extending outward from the outer peripheral edge.
これに対し、電源ライン]8および接地ライン20は3
層”1”AB用テープ」−4の電源層24および接地層
26と接続をとるから配線パターン層22を横断して設
ける必要がなく、配線パターン層22の内周縁から半導
体チップ13の外縁側に延出させて設ける。電源ライン
18および接地ライン20はそれぞiシ下層の電源層2
4および接地層26とビア等で電気的導通がとられてい
る。On the other hand, the power supply line] 8 and the ground line 20 are
Since the tape for layer "1" AB tape connects with the power supply layer 24 and ground layer 26 of layer 4, there is no need to provide it across the wiring pattern layer 22, and from the inner periphery of the wiring pattern layer 22 to the outer edge of the semiconductor chip 13. It is provided by extending to. The power supply line 18 and the ground line 20 are connected to the power supply layer 2 in the lower layer.
4 and the ground layer 26 through vias or the like.
なお、電源層24および接地層26は配線パターン層の
外周縁の適宜位置に設けた電源ライン18aおよび接地
ライン20aでインナーリード11と接続して外部と接
続し共通電位とする。The power supply layer 24 and the ground layer 26 are connected to the inner lead 11 through a power supply line 18a and a ground line 20a provided at appropriate positions on the outer periphery of the wiring pattern layer to be connected to the outside and set to a common potential.
」1記のように31F) i’ A 13用テープは半
導体チップおよびリードフレームの仕様に合わせてあら
かじめ導体パターン層を形成する。31F) i' A 13 tape has a conductor pattern layer formed in advance according to the specifications of the semiconductor chip and lead frame.
第3図および第4図は配線パターン層22等の構成をわ
かりやすく示した説明図である。FIGS. 3 and 4 are explanatory diagrams showing the structure of the wiring pattern layer 22 and the like in an easy-to-understand manner.
第3図に示す例は配線パターン層22を最」二層に形成
し、その下層に電源層24、最下層に接地層26を設け
たものである。配線パターン層22中に設けた電源ライ
ン]8はビア3oを介して下層の電源層24に接続され
、接地ライン2oはビア30を介して最下層の接地層2
6に接続される(第3図(b))。信号ライン16は単
独で設けて層間の接続はとらない。In the example shown in FIG. 3, a wiring pattern layer 22 is formed as the two-most layer, a power supply layer 24 is provided in the lower layer, and a ground layer 26 is provided in the lowermost layer. The power line 8 provided in the wiring pattern layer 22 is connected to the lower power layer 24 via the via 3o, and the ground line 2o is connected to the lowermost ground layer 2 via the via 30.
6 (Fig. 3(b)). The signal line 16 is provided independently and no connection is made between layers.
第4図に示す例は配線パターン層22を中間層に設け、
電源層24を最−I−、層、接地層26を最下層に設け
たものである。電源ライン]−8および接地ライン20
はビア30を介してそれぞれ電源層24および接地層2
6に接続される。In the example shown in FIG. 4, the wiring pattern layer 22 is provided as an intermediate layer,
The power supply layer 24 is provided in the uppermost layer, and the ground layer 26 is provided in the lowermost layer. Power line]-8 and ground line 20
are connected to the power layer 24 and the ground layer 2 through vias 30, respectively.
Connected to 6.
なお、第3図および第4図に示す例においてともに電源
[24と接地層26の位置を入れかえて形成してもよい
。In addition, in the examples shown in FIGS. 3 and 4, the positions of the power source [24 and the ground layer 26 may be exchanged.
これら3層1” A B用テープでは各導体層間をボリ
イミド等の電気的絶縁性材料によって絶縁している。し
たがって、絶縁性材料の誘電率および厚さ等を適宜設定
することによってマイクロス1〜リツプ回路の特性イン
ピーダンスを自由に設定でき、他の回路の特性インピー
ダンスと合致させることによって信号伝播の高速性を向
上させることができる。In these three-layer 1" A B tapes, each conductor layer is insulated by an electrically insulating material such as polyimide. Therefore, by appropriately setting the dielectric constant and thickness of the insulating material, The characteristic impedance of the rip circuit can be freely set, and by matching the characteristic impedance of other circuits, the high speed of signal propagation can be improved.
本実施例の半導体装置によれば、上記のように、電源層
24および接地層26を配線パターン層22とは別体に
設けた3層TAB用テープを用いて半導体チップ13と
リードフレームとを接続するように構成したから、配線
パターン層22内で電源ライン18および接地ライン2
0を形成することが容易にできるようになり信号ライン
16を形成するスペースに余裕ができ、電極数が多い半
導体チップであっても容易に接続が可能となる。また、
電源層24、接地層26を共通に使用することによりリ
ードフレームのインナーリードのうち信号ライン16へ
分配できるリード数を増大することができ、リードフレ
ームのピン数をさほど増大させることなく多ピン化に対
hδすることができる。According to the semiconductor device of this embodiment, as described above, the semiconductor chip 13 and the lead frame are connected using the three-layer TAB tape in which the power supply layer 24 and the ground layer 26 are provided separately from the wiring pattern layer 22. Since the configuration is such that the power line 18 and the ground line 2 are connected in the wiring pattern layer 22,
0 can be easily formed, there is more space for forming the signal line 16, and even semiconductor chips with a large number of electrodes can be easily connected. Also,
By using the power supply layer 24 and the ground layer 26 in common, it is possible to increase the number of leads that can be distributed to the signal line 16 among the inner leads of the lead frame, making it possible to increase the number of pins without significantly increasing the number of pins on the lead frame. can be compared to hδ.
また、第2図に示すように半導体チップ13のどの電極
位置からも電源層24あるいは接地層26に接近させて
接続でき、接続ラインの長さが短縮できて電位降下など
の悪影響を解消することができる等の利点がある。Furthermore, as shown in FIG. 2, connection can be made close to the power supply layer 24 or the ground layer 26 from any electrode position on the semiconductor chip 13, reducing the length of the connection line and eliminating negative effects such as potential drop. There are advantages such as being able to
〔3層1”AB用テープの製造方法〕
続いて、上記半導体装置に用いる3層TAB用テープの
製造方法について説明する。[Method for manufacturing 3-layer 1'' AB tape] Next, a method for manufacturing a 3-layer TAB tape used for the semiconductor device will be described.
第5図は3層TAB用テープの製造方法の一実施例を示
す説明図である。この製造方法では3層の導体層を形成
した後、導体層間の導通をとり、上下面に露出する導体
層をパターニングすることを特徴とする。FIG. 5 is an explanatory diagram showing an example of a method for manufacturing a three-layer TAB tape. This manufacturing method is characterized by forming three conductor layers, establishing conduction between the conductor layers, and patterning the conductor layers exposed on the upper and lower surfaces.
まず、第5図(a)に示すように電気的絶縁性を有する
ベースフィルム40の上下面に導体層42を設けたフィ
ルムの一方の面にエツチングを施す。First, as shown in FIG. 5(a), etching is performed on one side of a base film 40 having electrically insulating properties and a conductor layer 42 provided on the upper and lower surfaces thereof.
このエツチングを施した面は最終的に中間層となるもの
で、最終的なパターンにしたがってエツチングを施す。This etched surface will eventually become the intermediate layer, and is etched according to the final pattern.
第5図(b)は上記フィルムに、ベースフィルム40の
下面に導体層42を設けたフィルムを積層した状態であ
る。これにより、導体層42は絶縁層を介して3層構造
となる。FIG. 5(b) shows a state in which a film in which a conductor layer 42 is provided on the lower surface of a base film 40 is laminated on the above film. As a result, the conductor layer 42 has a three-layer structure with an insulating layer interposed therebetween.
次に、パンチング、ドリル加工、レーザ加工等によりス
ルーホール44を設け(第5図(C)) 、無電解めっ
きおよび電解めっきを施し、スルーホール44の内壁に
めっき層46を設ける(第5図(d))。このめっき層
46によって最」二層と中間層、最上層と最下層との間
の電気的導通がとられる。なお、このときのめっきによ
りフィルムの上下面の導体層42の露出面もめっきさi
bる。Next, a through hole 44 is formed by punching, drilling, laser processing, etc. (Fig. 5 (C)), and electroless plating and electrolytic plating are applied to form a plating layer 46 on the inner wall of the through hole 44 (Fig. 5 (C)). (d)). This plating layer 46 establishes electrical continuity between the two-most layer and the middle layer, and between the top layer and the bottom layer. In addition, due to the plating at this time, the exposed surfaces of the conductor layer 42 on the upper and lower surfaces of the film are also plated.
bl.
次に、第5図(e)に示すようにフィルムの上下面にレ
ジス1−パターン48を設ける。図示する実施例では最
−I−、層を配線パターン層、中間層を電源層、最下層
を接地層としている。前記スルーホール44はフィルム
を貫通して設けるから、配線パターン層と電源層間での
み導通をとる場合は、スルーホール部と接地層との接続
部を接地層から分離さ1;3
せるようにエツチングすればよい。Next, as shown in FIG. 5(e), a resist 1 pattern 48 is provided on the upper and lower surfaces of the film. In the illustrated embodiment, the lowest layer is a wiring pattern layer, the middle layer is a power supply layer, and the bottom layer is a ground layer. Since the through-hole 44 is provided through the film, if conduction is to be established only between the wiring pattern layer and the power supply layer, etching is performed to separate the connection between the through-hole and the ground layer from the ground layer. do it.
第5図(f)はめっき層46および導体層42をレジス
トパターン48にしたがってエツチングした後、レジス
1〜を除去した状態である。こうして、最上層に配線パ
ターン層が設けられ電源ライン18と電源層24、接地
ライン20と接地層26が接続された3層T A I3
用テープが得られる。FIG. 5(f) shows a state in which the plating layer 46 and the conductor layer 42 have been etched according to the resist pattern 48, and then the resists 1 to 4 have been removed. In this way, a three-layer T A I3 with a wiring pattern layer provided on the top layer and connecting the power line 18 and the power layer 24 and the ground line 20 and the ground layer 26 is formed.
You can obtain a tape for use.
第6図は、3層TAB用テープの他の製造方法を示す説
明図である。FIG. 6 is an explanatory diagram showing another method of manufacturing a three-layer TAB tape.
この製造方法では、導体層間で導通をとった2層の導体
層を上下面に有するFPC(Flexible Pr1
njcd C1rcuit)を形成し、次に3層目の導
体層を形成することを特徴とする。In this manufacturing method, an FPC (Flexible Pr1
The method is characterized in that a third conductor layer is formed.
まず、第6M(a)に示すように、ベースフィルム40
の上下面に導体層42を設けたFPC用基板基板ンチン
グ等によってスルーホール44を形成する。 次に、無
電解めっきおよび電解めっきを施してスルーホール44
の内壁にめっき層46を形成する。このとき、導体層4
2の外面もめっきされる(第6図(b))。First, as shown in No. 6M(a), the base film 40
A through hole 44 is formed by cutting or the like on an FPC substrate provided with a conductor layer 42 on the upper and lower surfaces of the substrate. Next, electroless plating and electrolytic plating are applied to form the through holes 44.
A plating layer 46 is formed on the inner wall. At this time, the conductor layer 4
The outer surface of 2 is also plated (FIG. 6(b)).
次に、レジス1−パターン48を設けて(第6図((:
))−導体層42をエツチングする(第6図(d))。Next, a resist 1-pattern 48 is provided (Fig. 6 ((:
)) - Etching the conductor layer 42 (FIG. 6(d)).
本実施例では」−層を配線パターン層としているから、
エツチングによってベースフィルム40」二に信号ライ
ン1−6、電源ライン18、接地ライン20を設ける。In this embodiment, the "- layer is the wiring pattern layer, so
Signal lines 1-6, power line 18, and ground line 20 are provided on base film 40'' by etching.
ベースフィルム40の下面の導体層42は電源層となる
もので、所定パターンでエツチングすることによって電
源ライン18とスルーホール部で導通をとり、接地層に
接続する接地ライン20は独立させることができる。The conductor layer 42 on the lower surface of the base film 40 serves as a power supply layer, and by etching it in a predetermined pattern, conduction can be established between the power supply line 18 and the through-hole portion, and the ground line 20 connected to the ground layer can be made independent. .
次に、電源層24の下面に電気的絶縁層としてドライフ
ィルム50を接着しく第6図(e)) 、 ドライフ
ィルム50をエツチングするだめのレジス1〜パターン
52を設ける。レジス]−パターン52はドライフィル
ム50を部分的にエツチング除去して接地ライン20と
接地層とを導通させるよう設ける。Next, a dry film 50 is bonded to the lower surface of the power supply layer 24 as an electrically insulating layer (FIG. 6(e)), and resists 1 to 52 for etching the dry film 50 are provided. The resist pattern 52 is formed by partially etching away the dry film 50 to provide electrical continuity between the ground line 20 and the ground layer.
第6図(g)はドライフィルム50をエツチングし、レ
ジスl−パターンを除去した状態である。ドライフィル
ム52のうち接地ライン20の導通部が除去されている
。FIG. 6(g) shows a state in which the dry film 50 has been etched and the resist L-pattern has been removed. The conductive portion of the ground line 20 in the dry film 52 has been removed.
次に、ドライフィルム5oの露出面に対して無電解めっ
き、スパッタリング、蒸着等によって導体層を設は接地
/i?726とする。接地ライン2oの導通部は図のよ
うに接地層26と導通され接地ライン20と接地層26
とが接続される。こうして、3 WiT A 13用テ
ープが得られる。Next, a conductor layer is provided on the exposed surface of the dry film 5o by electroless plating, sputtering, vapor deposition, or the like. 726. The conductive part of the ground line 2o is electrically connected to the ground layer 26 as shown in the figure, and the ground line 20 and the ground layer 26 are connected to each other.
are connected. In this way, a tape for 3 WiT A 13 is obtained.
なお、上記例においては3層目の導体層を形成する際に
絶縁層としてドライフィルムを用いたが、ドライフィル
ムのかわりに感光性あるいは非感光性のワニスを用いて
もよい。In the above example, a dry film was used as the insulating layer when forming the third conductor layer, but a photosensitive or non-photosensitive varnish may be used instead of the dry film.
また、」上記3層TAB用テープの製造方法においては
、最」二層を配線パターン層とし、中間層を電源層、最
下層を接地層としたが、各導体層は任意パターンに形成
できるから、配線パターン層、電源層、接地層は任意の
屑に形成することが可能である。In addition, in the method for manufacturing the three-layer TAB tape described above, the two most layers are wiring pattern layers, the middle layer is a power supply layer, and the bottom layer is a ground layer, but each conductor layer can be formed into any pattern. , the wiring pattern layer, the power supply layer, and the ground layer can be formed on any scrap material.
上記製造]1程から明らかなように、配線パターン層は
ベースフィルム」二に設けた導体層をエツチングして形
成するから、容易に微細パターンが形成でき、多ビン化
に対応することができる。[Manufacturing] As is clear from step 1, since the wiring pattern layer is formed by etching the conductor layer provided on the base film 2, fine patterns can be easily formed and a large number of bins can be accommodated.
以−1−1本発明について好適な実施例を挙げて種々説
明したが、本発明はこの実施例に限定されるものではな
く、発明の精神を逸脱しない範囲内多くの改変を施し得
るのはもちろでんのことである。Below-1-1 The present invention has been variously explained using preferred embodiments, but the present invention is not limited to these embodiments, and many modifications can be made without departing from the spirit of the invention. I'm talking about Mochiroden.
(発明の効果)
本発明に係る3層1’ A rJ用テープを用いた半導
体装置によれば、従来の半導体装置にくらべてリードフ
レームのビン数を減らすことができ、パッケージを小形
化することができる。また、信号ラインに対してマイタ
ロス1〜リツプ構造をとることができ、電気的特性を向
」ニさせ・ることかできる。(Effects of the Invention) According to the semiconductor device using the three-layer 1'A rJ tape according to the present invention, the number of lead frame bins can be reduced compared to conventional semiconductor devices, and the package can be made smaller. I can do it. Further, a mita-loss 1~rip structure can be used for the signal line, and the electrical characteristics can be improved.
また、73層゛I”ハ1−3用テープの製造方法によれ
ば、従来の2層’I” A II用テープの製造と同様
にして容易に73層TABテープを製造することができ
る笠の著効を奏する。Furthermore, according to the method for manufacturing the 73-layer TAB tape for 73-layer "I" A 1-3, the 73-layer TAB tape can be easily manufactured in the same manner as the conventional two-layer "I" A II tape. It is very effective.
第1図は本発明に係る3層’I”AB用テープを用いた
半導体装置の一実施例を示す説明図、第2図は33層T
A 11川テープの接続状態を示す説明図、第3図(
a)および()))はai TAB用テープの、fHf
j面図および横断面図、第4図(a)および(b)は3
層’1’A■3用テープの他の実施例の縦断面図および
横断面図、第5図は;3層TA r3用テープの製造方
法を示す説明図、第6図は3層1’AB用テープの他の
製造方法を示す説明図である。
1−1−・・・インナーリード、 13・・・半導体
チップ、 1,4・・・3層’rAB用テープ、J、6
・・・信号ライン、 ]−8・・・電源ライン、20
・・・接地ライン、 22・・・配線パターン層、
24・・・電源層、 26・・・接地層、30・・・ビ
ア、 /10・・・ベースフィルム、42・・・導体
層、 44・・・スルーホール、46・・・めっき層
、 50・・・ドライフィルム。FIG. 1 is an explanatory diagram showing an embodiment of a semiconductor device using a 3-layer 'I'AB tape according to the present invention, and FIG.
A 11 Explanatory diagram showing the connection state of the river tape, Figure 3 (
a) and ())) are fHf of ai TAB tape.
J-side view and cross-sectional view, Figures 4 (a) and (b) are 3
A vertical cross-sectional view and a cross-sectional view of another embodiment of the tape for layer '1' It is an explanatory view showing other manufacturing methods of AB tape. 1-1-... Inner lead, 13... Semiconductor chip, 1, 4... 3-layer 'rAB tape, J, 6
...Signal line, ]-8...Power line, 20
...Grounding line, 22...Wiring pattern layer,
24... Power supply layer, 26... Ground layer, 30... Via, /10... Base film, 42... Conductor layer, 44... Through hole, 46... Plating layer, 50 ...Dry film.
Claims (1)
パターン層、および前記電源ラインと接続される電源層
、前記接地ラインと接続される接地層が層間に電気的絶
縁材料を介在させて積層されて成る3層TAB用テープ
を用いて半導体チップとリードフレームとを接続したこ
とを特徴とする3層TAB用テープを用いた半導体装置
。 2、積層した際に中間層となる導体層に所定の導体パタ
ーンを形成した上下面に導体層を有するFPCに、片面
に導体層を有するFPC用基板を積層し、上下の露出面
および中間層に導体層を有する積層体を設け、 該積層体の上下面を貫通してスルーホール を設けるとともに、めっき等によりスルーホール内壁に
導体部を形成して前記導体層間を電気的に接続し、 積層体の露出面の導体層をエッチングして 所定パターンの導体パターンを形成する ことを特徴とする3層TAB用テープの製造方法。 3、上下面に導体層を有するFPC用基板にスルーホー
ルを設け、めっき等によりスルーホール内壁に導体部を
設けて前記導体層間を電気的に接続するとともに、前記
上下面の導体層をエッチングして所定の導体パターンを
形成し、 一方の導体パターンの露出面を電気的絶縁 材料によって被覆して絶縁層を形成し、 該絶縁層の必要個所をエッチングにより除 去して導体パターンを部分的に露出させ、 該絶縁層に導体層を被着して、絶縁層の表 面に導体層を設けるとともに前記導体パターンと電気的
な接続をとる ことを特徴とする3層TAB用テープの製造方法。[Claims] 1. A wiring pattern layer having a signal line, a power supply line, and a ground line, a power supply layer connected to the power supply line, and a ground layer connected to the ground line, each having an electrically insulating material between the layers. 1. A semiconductor device using a three-layer TAB tape, characterized in that a semiconductor chip and a lead frame are connected using a three-layer TAB tape formed by interposing and laminating layers. 2. An FPC board having a conductor layer on one side is laminated on an FPC having a conductor layer on the upper and lower surfaces with a predetermined conductor pattern formed on the conductor layer that becomes the intermediate layer when laminated, and the upper and lower exposed surfaces and the intermediate layer are laminated. A laminate having a conductor layer is provided on the laminate, a through hole is provided passing through the upper and lower surfaces of the laminate, and a conductor portion is formed on the inner wall of the through hole by plating or the like to electrically connect the conductor layers, and the laminated body is laminated. A method for manufacturing a three-layer TAB tape, which comprises etching the conductor layer on the exposed surface of the body to form a conductor pattern in a predetermined pattern. 3. A through hole is provided in an FPC substrate having conductor layers on the upper and lower surfaces, and a conductor portion is provided on the inner wall of the through hole by plating or the like to electrically connect the conductor layers, and the conductor layer on the upper and lower surfaces is etched. A predetermined conductor pattern is formed using the method, the exposed surface of one of the conductor patterns is covered with an electrically insulating material to form an insulating layer, and the necessary portions of the insulating layer are removed by etching to partially expose the conductor pattern. A method for manufacturing a three-layer TAB tape, which comprises: depositing a conductor layer on the insulating layer, providing the conductor layer on the surface of the insulating layer, and establishing an electrical connection with the conductor pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2130489A JPH0425144A (en) | 1990-05-21 | 1990-05-21 | Semiconductor device using tape for three-layer tab and manufacture of tape for three-layer tab |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2130489A JPH0425144A (en) | 1990-05-21 | 1990-05-21 | Semiconductor device using tape for three-layer tab and manufacture of tape for three-layer tab |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0425144A true JPH0425144A (en) | 1992-01-28 |
Family
ID=15035484
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2130489A Pending JPH0425144A (en) | 1990-05-21 | 1990-05-21 | Semiconductor device using tape for three-layer tab and manufacture of tape for three-layer tab |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0425144A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07297225A (en) * | 1994-04-26 | 1995-11-10 | Nec Corp | Tape carrier package |
US5731962A (en) * | 1994-09-22 | 1998-03-24 | Nec Corporation | Semiconductor device free from short-circuit due to resin pressure in mold |
WO2023090165A1 (en) * | 2021-11-17 | 2023-05-25 | 株式会社デンソー | Semiconductor module |
-
1990
- 1990-05-21 JP JP2130489A patent/JPH0425144A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07297225A (en) * | 1994-04-26 | 1995-11-10 | Nec Corp | Tape carrier package |
US5731962A (en) * | 1994-09-22 | 1998-03-24 | Nec Corporation | Semiconductor device free from short-circuit due to resin pressure in mold |
WO2023090165A1 (en) * | 2021-11-17 | 2023-05-25 | 株式会社デンソー | Semiconductor module |
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