JPH042234A - Frame synchronizing system - Google Patents

Abstract

PURPOSE:To shorten the synchronization restoration time by revising the frame format of information to be sent depending on the synchronizing state at a reception side, adding synchronous information in the synchronizing state and increasing and sending the synchronous information to be added in the asynchronizing state. CONSTITUTION:When information to be sent is inputted to an mBnB conversion means 1, a frame pattern revising means 3 selects a frame format of transmission information according to the synchronous state of an opposite station and outputs the result to a frame format designation means 2. The frame format designation means 2 constitutes a frame pattern according to a frame format designated by a frame pattern revising means 3. The mBnB conversion means 1 adds additional information (control information, synchronous information and reception synchronization information, etc.) to the inputted transmission information according to the formed frame format and converts the code so that a marking rate is halved and the result is outputted. Thus, the restoration time from the asynchronous state till the synchronization establishment is shortened.

Description

[Detailed Description of the Invention] (Summary) Regarding the frame synchronization method, the purpose of this invention is to shorten the recovery time from an asynchronous state such as when recovering from an abnormality in a communication terminal or when starting communication to establishing synchronization. inserting additional information such as synchronization information, control information, and reception synchronization information into the frame according to the first frame format;
mBnB code conversion means 1 that performs mBnB code conversion; frame format designation means 2 that specifies the frame format upon code conversion of the mBnB code conversion means 1; and when an asynchronous state in the opposite station is detected, the transmission information Sending information by an information sending method comprising a frame format changing means 3 for changing the code conversion of the frame into a second frame format, and separating additional information such as the synchronization information, control information, and reception synchronization information from the received information; An nBmB code conversion means 4 converts the received information separated from the additional information into an nBmB code after synchronization is established, and manually inputs the synchronization information in the separated additional information to detect the establishment of synchronization of the received information, and After synchronization is established by the frame synchronization detecting means 5, additional information such as control information separated from the received information is sent to each output target terminal. A frame synchronization method in which signals are received using an information receiving method that includes additional information separation and output means 6 for outputting.

[Industrial application field]

The present invention relates to a frame synchronization system, and particularly to a frame synchronization system for information in which transmission information is mBnB code-converted in order to reduce the mark rate on a transmission path to 1/2.

When transmitting and receiving signals in recent years, the mark rate (ratio of 1s and 0s of the signal) of information sent to the transmission path is reduced to 1/2 so that the clock can be easily regenerated on the receiving side. ing. Furthermore, as transmission paths become faster and have higher quality, shortening the synchronization recovery time after recovery from an abnormality or at the start of communication has become an important issue.

[Prior Art] FIGS. 5 and 6 show the configurations of a conventional transmitting section and a receiving section, and FIG. 7 shows a conventional transmission frame format.

The mBnB code conversion operation will be explained below by taking 586B code conversion as an example.

First, as for the operation of the transmitter, the serial data to be transmitted is
The signal is input to the P converter 11. In the S/P converter 11, the input serial data is converted into 5-bit parallel data by a clock A obtained by dividing the operating clock of the serial data created by the oscillator 14 by 5 by the frequency divider 15.
The signal is output to the code conversion circuit 12. The 586B code conversion circuit 12 adds 1 or 0 information to the input 5-bit parallel data so that the mark rate of the transmission data is 1/2, converts it to 6-bit parallel data, and performs P/S conversion. Vessel 13
It is output to. The P/S converter 13 converts the input 6-bit parallel data into serial data according to the clock operation clock generated by the oscillator 16 and outputs the serial data. Here, the timing of the clocks generated by the oscillators 14 and 16 has a relationship of 1:1.2. Since both oscillators 14 and 16 need to be synchronized with each other, the clock A obtained by dividing the operating clock generated by the oscillator 14 by 5 by the frequency divider 15 and the operating clock generated by the oscillator 16 are divided by the frequency divider 18. The oscillator 16 is controlled to output the clock B whose frequency is divided by 6 to the PLL circuit 17, and to synchronize the phase of the operating clock.

The structure of the transmission frame is shown in Figure 7 (power), (ki), (
As shown in (2), one frame consists of 12 subframes, one subframe consists of 18 words,
One word consists of 6 bits.

As shown in Figure 7 (power), the transmission information changes to additional information of 1 or 0 at a rate of 1 word for every 18 words, and the control information or synchronization information of peripheral devices on the receiving side is transferred to overhead pits (hereinafter referred to as OHB and L7). ) is added. Therefore, there is a 12-bit OHB in one frame, and the timing at which the OHB is inserted is, for example, the 7th bit.
Control information and synchronization information are inserted in the format shown in Figure (ri). The OHB insertion operation will be explained below.

First, the clock A outputted from the frequency divider 15 is further divided by 18 by the frequency divider 2I and outputted as the clock C to the timing generation circuit 22 and the P/S converter 23. The timing generation circuit outputs an OHB insertion timing signal to the 5B6B code conversion circuit 12 and outputs a switching signal to the selector 24. On the other hand, the P/S converter 23 outputs control information or synchronization information to the selector 24 via the P/S converter 23 in accordance with the set frame pattern 71. Additional information is input to the selector 24 from the 5B6B code conversion circuit 12, and normally the additional information is sent as is to the P/S.
The control information or synchronization information is output to the converter 13, and the control information or synchronization information is selected by the switching signal from the timing generation circuit 22.
/S converter 13, and information substantially as shown in FIG. 7(ri) is sent out.

Next, as for the operation of the receiving section, first the serial received data is
/P converter 41. The S/P converter 41 converts the input serial data into a 6-bit parallel signal according to the operating clock B' which is obtained by dividing the operating clock of the serial signal generated by the oscillator 44 by 6 by the frequency divider 45. 685
It is output to the B code conversion circuit 42.

In addition, the synchronization detection section 81 extracts the value of one pin out of the 6-bit parallel signal output from the S/P converter 41,
Synchronization information is checked according to the frame pattern (OHB insertion timing) set on the transmitting side. If synchronization is not detected, the bit positions to be extracted are sequentially changed, and synchronization information is extracted and checked. For example, when a synchronous state is detected six times in a row (six stages of forward protection), it is determined that synchronization has been established, and when an asynchronous state is detected nine times in a row (nine stages of backward protection), it is determined that an asynchronous state is established.

When the synchronization detection section 81 detects the establishment of synchronization, the 685B code conversion circuit 42 is operated to remove the additional information and control information added on the transmitting side, and output it to the P/S converter 43. The P/S converter 43 converts the input 5-bit parallel data into serial data according to the clock operating clock generated by the oscillator 16 and outputs the serial data.

Here, the timing of the clocks generated by the oscillators 44 and 46 has a relationship of 1.21. Both oscillators 44
．． Since the oscillators 46 and 46 need to be synchronized with each other, the oscillator 44
A clock B' obtained by dividing the operating clock created by the oscillator 46 into 6 by a frequency divider 45 and a clock A' obtained by dividing the operating clock created by the oscillator 46 by 5 by a frequency divider 47 are used in the PLL circuit 1.
7, and controls the oscillator 46 so as to synchronize the phase of the operating clock.

After synchronization is established, the P/S converter 61 extracts OHB (control information and synchronization information), and outputs the control information and synchronization information to the corresponding peripheral devices.

[Problem to be solved by the invention]

In the conventional mBnB code conversion as described above, the time required to recover from an abnormal state or to establish synchronization from an asynchronous state at the start of communication is 2 bits of synchronization information out of 812 OH bits included in one frame. When the number of forward protection stages is, for example, six, the worst frame synchronization recovery time is as shown in the calculation below.

× 2X167.1168X10' = 1.68m5 N: Frame length (1296 bits) P: Probability that the received pulse sequence matches the synchronization pattern (
1/2) r: Number of frame pattern bits (2 bits) TF:
Half frame pattern detection] Ltl (1296/2x
167.11681+, that is, it takes a very long time to restore synchronization.

Therefore, it is an object of the present invention to shorten the recovery time from an asynchronous state, such as when a communication terminal recovers from an abnormal state or starts communication, until synchronization is established.

[Means to solve the problem]

FIG. 1 shows a diagram of the principle of the present invention. First, on the sending side,
Information to be transmitted is input to mBnB conversion means 1. Here, the frame pattern changing means 3 switches the frame format of the transmission information according to the synchronization state of the partner station and outputs it to the frame format specifying means 2. A frame pattern is constructed according to the frame format specified by According to the frame format configured here, the mBnB conversion means 1 adds additional information (control information, synchronization information, reception synchronization information, etc.) to the input transmission information, and performs code conversion so that the mark rate becomes 1/2. and output it.

Next, on the receiving side, the received information is first input to the nBmB conversion means 4. Here, additional information (control information, synchronization information, reception synchronization information) in the input reception information is input to the frame synchronization detection means 5, a synchronization state is detected, and reception synchronization information is output. After synchronization is established, the nBmB conversion means 4 is operated to convert the input information into code, and the additional information separation and output means 6 outputs the additional information to the peripheral device.

[Operation] The transmitting side changes the frame format of the information to be transmitted depending on the synchronous state (synchronous state, asynchronous state) on the receiving side, and in the synchronous state, 2 bits of synchronization information are added. By increasing the number of synchronized states and transmitting them when in an asynchronous state, the synchronization recovery time is reduced.

For example, for 12 bits of additional information in an asynchronous state,
The worst frame synchronization recovery time when 11 bits other than 1 pin of reception synchronization information are added as synchronization information is as shown in the calculation below.

= 6.31 μs N: Frame length (1296 bits) P: Probability that the received pulse sequence matches the synchronization pattern (
1/2) r: Number of frame pattern bits (11 bits) TF two and a half frame pattern detection period (1296/2 x 167.1168M) [Example
] 2x167.1168xlO' A detailed explanation will be given below based on the embodiment shown in the drawings.

The mBnB code conversion means 1 in FIG. 1 is the S/P converter 11 in FIG.
, oscillators 14, 16, frequency divider 15°17, PLL circuit 1
The frame format specifying means 2 in FIG. 1 corresponds to the part consisting of the frequency divider 21, timing generation circuit 22, P/S converter 23, and selector 24 in FIG. The frame formant changing means 3 in FIG. The nBmB code conversion means 4 in the figure includes the S/P converter 41 in FIG. 3, a 685B code conversion circuit 42, a P/S converter 43,
Oscillators 44, 46, frequency dividers 45, 47, PLL circuit 48
The frame synchronization detection means 5 in FIG. 1 corresponds to the synchronization detection section in FIG. 3, and the additional information separation and output means 6 in FIG. 1 corresponds to the S/P converter in FIG. 3. 61 is supported.

In FIG. 2, the transmission operation will be explained first. Information to be transmitted is input to the S/P converter 11.

In the S/P converter 11, the input information is a clock A which is obtained by dividing the clock created by the oscillator 14 by 5 with the frequency divider 15.
The signal is converted into a 5-bit parallel signal and output to the 586B code conversion circuit 12. The 586B code conversion circuit 12 performs code conversion to reduce the mark rate on the transmission path to 1/2, and outputs the transmission information, which has become a 6-bit parallel signal through code conversion, to the P/S converter 13. . The P/S converter 13 converts the input information into a serial signal according to the clock generated by the oscillator 16 and outputs the serial signal. Here, it is desirable that the operations of the S/P converter 11 and the P/S converter 13 be in a synchronous state, but the clock timing created by the re-transmitter 1416 has a relationship of 1:1°2, and the oscillator 14 The clock created by the oscillator 16 is divided by the frequency divider 15 (divided by 5), and the clock created by the oscillator 16 is divided by the frequency divider 17 (divided by 6).
The oscillator 16 is controlled to output the signal to the PLL circuit 18 via the oscillator 16 for phase synchronization.

On the other hand, as shown in Figure 4 (A), (B), and (T), the frame format of transmission information is such that one frame consists of 12 subframes, and one subframe consists of 18 subframes.
It consists of words, and one word consists of 6 bits. One bit out of the six bits constituting this one word is an additional bit of 1 or 0 added by code conversion.

When transmitting information according to such a frame format, one bit per 18 words is converted into additional bits and additional information such as reception synchronization information, control information, synchronization information, etc.
OHB) is added. As an operation to which additional information is added, the clock generated by the oscillator 14 is transferred to the frequency divider 15.
The frequency is divided by 5 at the frequency divider 21, and the frequency is further divided by 18 at the frequency divider 21 and output to the timing generation circuit 22 and the P/S converter 23. . The timing generation circuit 22 generates OHB from the input clock.
Create an insertion timing signal for selectors 24 and 5B.
It is output to the 6B code conversion circuit. Also, the P/S converter 23
In this case, the additional information set in the first frame format setting section 32 or the second frame format setting section 33 inputted via the selector is outputted to the selector 24 according to the clocks inputted sequentially. selector 24
Then, the additional bits added by the 586B code conversion input from the 5B6B code conversion circuit 12 and the additional information input from the P/S converter 23 are switched according to the timing input from the timing generation circuit 22.
It is output to.

Next, the reception operation will be explained. First, received information is input to the S/P converter 41. In the S/P converter 41, the input reception information is converted into a 5-bit parallel signal according to the clock B' which is obtained by dividing the clock generated by the oscillator 44 by 6 by the frequency divider 45, as in the conventional case, and performs 685B code conversion. It is input to circuit 42.

The 685B code conversion circuit 42 removes additional information and additional focus from the input 6-bit parallel information, converts the code into 5-bit original information, and outputs it to the P/S converter 43.

The P/S converter 43 converts the input information into a serial signal according to the clock generated by the oscillator 46 and outputs the serial signal. Here, it is desirable that the operations of the S/P converter 41 and the P/S converter 46 be in a synchronous state, but there is a 1.2:1 relationship between the clock timings created by the re-transmitters 44 and 46. The clock created by the frequency divider 45 (
(divided by 6) 2 The clock created by the oscillator 46 is sent to the frequency divider 4
7 (frequency divided by 5) to a PLL circuit 48, and an oscillator 46 is controlled to synchronize the phases. On the other hand, S/P
The value of 1 bit of the 6-bit parallel signal output from the converter 41 is input to the synchronization detector 81 and the S/P converter 61. First, the synchronization detection unit 81 detects synchronization from the input synchronization information according to the frame pattern (the OHB insertion timing) set on the transmitting side, and outputs it as reception synchronization information. If synchronization is not detected here, a shift signal is output to the S/P converter 41 so as to sequentially change the bit position to be extracted sequentially, and synchronization information is extracted and checked.

When an asynchronous state is detected 9 times in a row (9 stages of backward protection)
It is determined that the state is out of sync. Next, in the S/P converter 61, the control information, which is additional information input in the synchronized state, is sequentially output to peripheral devices according to the clock B' input from the transmitter frequency divider 45. The received synchronization information is output.

Here, the synchronization establishment operation when recovering from an abnormal state or when starting communication will be explained. First, the transmitter sends 11 bits other than the reception synchronization information FA, which indicates the reception status at its own station, as synchronization information to the opposing station as control information, according to the frame format shown in Figure 4 (1). Send to. On the receiving side of the opposing station, for example, synchronization protection of the front six stages is performed and synchronization information is checked according to the frame format of the received information (OHB insertion timing). Here, the worst synchronization recovery time from the asynchronous state to the establishment of synchronization is as follows, considering that in the asynchronous state, the synchronization information added to one frame format is 11 bits compared to 2 bits in the synchronous state.
As shown in the calculation below.

2 x 167, 1168 x 106 = 6.31
μs N: Frame length (1296 bits) P: Probability that the received pulse sequence matches the synchronization pattern (
1/2) r: Number of frame pattern bits (11 bits) TF two-and-a-half frame pattern detection period (1296/2 x 167.1168M) Therefore, the time required for synchronization recovery is 6.31 μs.

After the synchronization is established, the synchronization detecting circuit 51 outputs reception synchronization information indicating that synchronization has been established to the paired transmitter, and the reception synchronization information is returned to the own station as reception synchronization information. The own station inputs reception synchronization information indicating the synchronization state of the opposite station from the paired receiving unit, and selects the selector 3 according to the reception synchronization information.
1 and set the frame format of the transmission information to 4.
Switch to the format shown in figure (1) when synchronization is established,
The reception synchronization information FA indicating the reception status at the own station is sent to the opposite station as additional information.

The frame formats shown in FIGS. 4 and 7 used in the above description are merely examples.

In this embodiment, the pattern of the synchronization information included in the additional information is simplified by switching the control information to the synchronization information depending on the receiving state of the opposite station for the additional information added to the transmitted information, and pseudo synchronization pull-in is performed. The probability also decreases, and the pseudo-synchronization detection circuit becomes unnecessary.

〔Effect of the invention 〕

As described above, according to the present invention, since the additional information to be transmitted is switched depending on the synchronization state of the communication partner, the worst-case frame synchronization recovery time for restoring the synchronization state at the start of communication or when recovering from an abnormality can be significantly shortened.

6...Additional information separation output means, It is.

[Brief explanation of drawings]

FIG. 1 is a diagram of the principle of the present invention. FIG. 2 is an embodiment of the transmitting section of the present invention. FIG. 3 is an embodiment of the receiving section of the present invention. FIG. 4 is a frame format of transmitted and received information of the present invention. 5 is a diagram showing a conventional transmitting section, FIG. 6 is a diagram showing a conventional receiving section, and FIG. 7 is a diagram showing a conventional frame format of transmitted and received information. ...mBnB code converting means, 2... Frame format specifying means, 3... Frame format changing means, 4... nBmB code converting means, 5... Frame synchronization detection means,

Claims (1)

[Claims] 1. Convert the transmitted information to mBnB code and convert the received information to nBm
In an information transmission system in which the mark rate on the transmission path is maintained at a predetermined value by B code conversion, additional information such as synchronization information, control information, reception synchronization information, etc. is added to the transmitted information according to the first frame format. insert,
mBnB code conversion means 1 that performs mBnB code conversion; frame format designation means 2 that specifies the frame format upon code conversion of the mBnB code conversion means 1; and when an asynchronous state in the opposite station is detected, the transmission information An information transmission system characterized by comprising a frame format changing means 3 for changing the code conversion of the frame into a second frame format. 2. Convert the transmitted information to mBnB code and convert the received information to nBm
In an information transmission system in which the mark rate on the transmission path is maintained at a predetermined value by B code conversion, additional information such as synchronization information, control information, reception synchronization information, etc. is separated from received information, and the additional information is nBmB code converting means 4 converts the separated received information into nBmB code after synchronization is established, inputs the synchronization information in the separated additional information, detects the establishment of synchronization of the received information, and converts the nBmB code into the nBmB code after establishing synchronization. After synchronization is established by the frame synchronization detection means 5 that outputs reception synchronization information indicating the state, and the frame synchronization detection means 5,
An information receiving system characterized by comprising additional information separation/output means 6 for outputting additional information such as control information separated from the received information to each output target terminal. 3. Convert the transmitted information to mBnB code and convert the received information to nBm
In an information transmission system in which the mark rate on a transmission path is maintained at a predetermined value by B code conversion, information is transmitted by the information transmission method according to claim 1, and information is transmitted by the information reception method according to claim 2. A frame synchronization method characterized in that when an asynchronous state is detected on the receiving side by receiving information, additional information to be added to the information sent from the transmitting side is switched.