JPH04212464A - Horizontal conductivity modulation type semiconductor device - Google Patents

Abstract

PURPOSE:To lower the ON voltage for cutting down the turn off time by a method wherein a sub-emitter electrode is provided even in a first conductivity type first layer beneath a second conductivity type second layer on the emitter electrode and collector electrode side in the RESURE structure to be connected to the emitter electrode. CONSTITUTION:A substrate emitter electrode (sub-emitter electrode) 14 in contact with the rear surface of a P<-> substrate 1 is provided to be shortcircuited with an emitter electrode 12. That is, a terminal G, a terminal E1, a terminal C1 and a terminal E2 are respectively connected to a gate electrode 6, an emitter electrode 12, a collector electrode 13 and an emitter electrode 14. On the other hand, by impressing emitter electrodes with voltage, the electron current runs in from an n<+> emitter region 4 to an n<-> layer 2 and an n buffer region 8 passing through a channel region 7. Through these procedures, the potential declines by P<+>/n between a P<+> collection region 9 and the n buffer region 8 so that the conductivity may be modulated in the n buffer region 8 by hole injection from the P<+> collector region 9.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral conductivity modulation type semiconductor device, such as a lateral insulated gate bipolar transistor (hereinafter abbreviated as IGBT), in which on-resistance is reduced by conductivity modulation.

0002

2. Description of the Related Art In recent years, IGBTs, which are MOSFETs that utilize conductivity modulation, have been attracting attention as switching elements. Like a MOSFET, an IGBT has a high input impedance, and like a bipolar transistor, it can have a low on-resistance. IGBTs were initially developed as vertical elements, and recently horizontal IGBTs have been developed. This is because in a vertical IGBT, current flows between the front and back surfaces of the semiconductor substrate, whereas in a horizontal IGBT, both main electrodes and the gate are formed using only one side of the semiconductor substrate. This is due to the fact that it is easy to incorporate into a substrate, and it is easy to connect with an arithmetic circuit incorporated on the same substrate in order to make the device intelligent.

[0003] The feature of IGBT is that it can achieve a low on-voltage due to conductivity modulation even at a high withstand voltage, but on the other hand, a small number of
The majority carrier must be removed in order to transition to the off state, so the power MOSFET
The problem is that the switching speed is slow compared to . Figure 2 shows the conventional RESURF (REDU
This figure shows a horizontal IGBT having a CED (SURFACE FIELD) structure. In this IGBT, p+ buried regions 10 are selectively formed in the surface layer of p- substrate 1. An n- layer 2 is epitaxially grown thereon. Selective p base region 3 in the surface layer of n- layer 2
and n buffer regions 8 are formed at intervals. p
An n+ emitter region 4 is selectively formed in the surface layer of the base region 3. The surface portion of the p base region 3 sandwiched between the n- layer 2 and the n+ emitter region 5 becomes a channel region 7, and a gate electrode 6 is provided thereon with a gate oxide film 5 interposed therebetween. and p base region 3 and n
+ Emitter electrode 1 in common contact with emitter region 4
2 is provided between the gate electrode 6 and the insulating film 11. Further, a p+ collector region 9 is selectively formed in the surface layer of the n buffer region 8, and a collector electrode 13 is provided on the surface thereof, resulting in a three-terminal structure.

In such a three-terminal lateral IGBT, an electron current flows from the n+ emitter region through the channel region 7 to the n− layer 2 and n buffer region 8 by applying a voltage between the gate and emitter. p+ collector region 9 and n
A potential barrier of p+/n is formed by the buffer region 8, but as electrons accumulate in the n buffer region 8,
A potential drop is brought about at the p+/n junction, holes are injected from the p+ collector region 9 into the n buffer region 8, and conductivity modulation occurs. Holes, which are minority carriers in the n buffer region 8 that caused conductivity modulation, are in the p+ collector region 9.
is the emitter, the base is the n- layer 2 sandwiched between the n-buffer region and the n-buffer region and the p- substrate 1, and the collector is the p- substrate 1, the p+ buried region 10, and the p-base region 3. Since the transistor is a narrow base transistor, the p- flows into the substrate 1,
It passes through to the emitter electrode 12. Therefore, the hole concentration above the p- substrate 1 increases. As a result, the above n+
The electron current from the emitter region 4 to the n-buffer region 8 increases as the Coulomb force due to holes in the p-substrate 1 increases.
When passing through the n- layer 2, it is bent toward the p- substrate 1,
As electrons accumulate between n- layer 2 and p- substrate 1, the potential drop between p- substrate 1 and n- layer 2 decreases, so holes are injected from p- substrate 1 to n- layer 2. conductivity modulation occurs in the portion of the n- layer 2 close to the p- substrate 1. As a result, the resistivity of the entire n- layer 2 decreases, so the p+ collector region 9 and the n buffer region 8
and pn formed by n- layer 2 and p base region 3
The p-transistor is driven. Conductivity modulation occurs throughout the n- layer 2, and in that pnp transistor, the holes become p+
From the collector region 9, it passes through the n buffer region 8, the n- layer 2, the p base region 3, and the emitter electrode 12. Since the emitter electrode 12 electrically shorts the p base region 3 and the n+ emitter region 4, the p+ collector electrode 9
, n buffer region 8, n- layer 2, p- substrate 1, p+
A first parasitic thyristor consists of four layers: a buried region 10 and an n emitter region 4, and a second parasitic thyristor consists of four layers: a p+ collector region 9, an n buffer region 8, an n- layer 2, a p base region, and an n+ emitter region 4. The operation of the parasitic thyristor is blocked, and the device can be turned off by reducing the gate-emitter voltage to zero.

[0005]

[Problem to be solved by the invention] Three-terminal horizontal IGBT
Then, p+ collector electrode 9, n buffer region 8,
A first pnp transistor consists of an n- layer 2, a p-substrate 1, a p+ buried region 10, and a second pnp transistor consists of a p+ collector electrode 9, an n buffer region 8, an n- layer 2, and a p base region 3. Although they are driven in parallel, this is because the n- layer 2 of the second transistor has a wide base, and the p-layer of the first transistor
The long substrate distance results in high on-voltage and slow turn-off time, leading to increased switching losses. Furthermore, since the hole current injected from the p+ collector region 9 concentrates on the emitter electrode 12 in both the first and second transistors, the hole current passing through the p base region 3 causes a potential drop in the p base region. As a result, the potential barrier between the n+ emitter region 4 and the p base region 3 disappears, and electrons are injected from the n+ emitter region 4 into the p base region 3, which tends to cause so-called latch-up. As a result, the safe operation area of the element becomes narrow, resulting in problems such as the inability to perform steady switching operations.

Therefore, an object of the present invention is to provide a lateral conductivity modulation type semiconductor device which solves the above problems, reduces the on-state voltage, increases the turn-off time, reduces the switching time, and expands the safe operation area. It is about providing.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention comprises a first layer of a first conductivity type, a second layer of a second conductivity type laminated thereon, and a second layer of the second conductivity type laminated thereon. a base region of a first conductivity type selectively formed within the surface layer of the layer and connected to the first layer by a region of the first conductivity type; and a second conductivity type base region selectively formed within the surface layer of the base region. a conductivity type region, a gate electrode provided on the surface of the base region sandwiched between the second conductivity type region and the surface exposed portion of the second layer via an insulating film, and the second conductivity type region an emitter electrode in common contact with the base region; a buffer region of a second conductivity type and having a higher impurity concentration than the second layer selectively formed on the surface of the second layer away from the base region; In a lateral conductivity modulated semiconductor device having a collector region of a first conductivity type selectively formed in a surface layer of a buffer region and a collector electrode in contact with the collector region, an emitter It is assumed that a sub-emitter electrode is connected to the electrode. It is also effective for the collector region to sandwich the exposed surface portion of the buffer region, and for the collector electrode to commonly contact the exposed surface portion of the buffer region and the exposed surface portion of the collector region. Alternatively, the buffer region connecting portion of the first conductivity type extends from the buffer region immediately below the collector region to the collector region, and the buffer region connecting portion widens as it approaches the surface from the bottom of the collector region, and the widened portion It is also effective that the collector electrode is in common contact with the exposed surface portion of the collector region. Furthermore, in these cases, it is effective to locally interpose an insulating film between the collector electrode and the exposed portion of the surface of the buffer layer region or the connection portion of the buffer region.

[0008]

[Operation] When a voltage is applied between the gate electrode and the emitter electrode, minority carriers are injected from the collector region into the buffer region of the second conductivity type and cause conductivity modulation, causing the collector region of the first conductivity type to A bipolar transistor consisting of a buffer region and a second layer of the same type and a first layer of the first conductivity type is driven, and a current of minority carriers in the second conductivity type region flows to the sub-emitter electrode. Because the transistor is narrow-base, it has a high current amplification factor, low on-voltage, fast turn-off time, and reduced switching loss. Also, unlike in the past, two transistors are not driven in parallel between the emitter electrode and the collector electrode within the semiconductor substrate, so current concentration on the emitter electrode is eliminated, latch-up is less likely to occur, and the safe operating area is expanded.

Furthermore, it is also possible to adopt a collector short structure that increases the switching speed. In that case, if the collector electrode and the exposed portion of the buffer region are locally insulated, the path of the current flowing from the buffer region to the collector electrode is restricted. , the distance flowing along the collector region becomes longer, and a large potential drop occurs with a small current, which promotes carrier injection from the collector region and causes conductivity modulation even in the low current region. In addition, the buffer region expands as it approaches the surface and is exposed to the surface by a connection portion that penetrates the collector region, and by contacting the collector electrode only at the surface exposed portion of the expanded portion, the current flowing from the buffer region to the collector electrode can be reduced. The distance flowing along the collector region is longer.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a horizontal IGBT according to an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. The difference from FIG. 2 is that a substrate emitter electrode (sub-emitter electrode) 14 that contacts the back surface of the p-substrate 1 is provided;
This point is short-circuited to the emitter electrode 12. That is, this element has a terminal G on the gate electrode 6 and an emitter electrode 1 on the gate electrode 6.
2, a terminal C is connected to the collector electrode 13, and a terminal E2 is connected to the substrate emitter electrode 14.
It is GBT. In this IGBT, conventional IGBT
Similarly, by applying a voltage between the gate and emitter, n+
From the emitter region 4 through the channel region 7 to the n- layer 2
, n An electron current flows into the buffer region 8. A potential drop of p+ /n occurs between p+ collector region 9 and n buffer region 8, and conductivity modulation occurs in n buffer region 8 due to hole injection from p+ collector region 9. Holes that cause conductivity modulation in the n-buffer region 8 cause the p+ collector region 9 to become an emitter, the n-buffer region 8 and the n-
layer 2 as base, p- with substrate emitter electrode 14;
A pnp transistor with the substrate 1 as its collector is driven, and holes pass through the n- layer 2, the p- layer 1, and the substrate emitter electrode 14. The base region of this pnp transistor is very small because it consists of an n buffer region 8 and an n- layer 2 sandwiched between it and a p- substrate 1, and since it is a narrow base transistor, hfe is high. Therefore, a narrow base pnp with high hfe with a small electron current
Since the transistor is driven, the on-voltage is low, conductivity modulation occurs when it is on, and the area where carriers accumulate is narrow, so the turn-off time is shortened. Figure 3 shows the IV characteristics.
line 3 than the conventional three-terminal horizontal IGBT shown by line 31.
As shown by 2, a low on-voltage can be obtained. FIG. 4 is a trade-off curve between saturation voltage and turn-off time, and the turn-off time shifts toward a shorter line 42 in the case of the four-terminal type compared to line 41 in the case of the three-terminal type.

Further, the hole current generated by the pnp transistor consisting of the p+ collector region 9, the n buffer region 8, the n− layer 2, and the p base region 3 flows through the emitter electrode 12.
The pn layer is formed by the p+ collector region 9, the n buffer region 8, the n− layer 2, and the p− substrate 1.
Since the hole current generated by the p-transistor flows to the substrate emitter electrode 14 as described above, it is not concentrated on the emitter electrode 12 and latch-up is less likely to occur. Therefore, as shown in FIG. 5, the three-terminal type breaks down at a point on the line 51, whereas the four-terminal type breaks down at a point on the line 52, so the safe operating area shown by the broken line 50 is secured. , the safe operating area expands.

FIG. 6 shows another embodiment of the present invention, which employs a collector short structure as a conventional means of increasing switching speed. That is, n
A p+ collector region 9 is selectively formed in the surface layer of the buffer region 8, and a collector electrode 13 is in common contact with the p+ collector region 9 and an n+ collector region 81 formed in the middle thereof, resulting in a collector short structure. ing. However, conductivity modulation in an element with a collector short structure occurs when the p+/n junction is forward biased due to a potential drop due to the current flowing through the n buffer region 8 directly under the p+ collector region 9. When the resistance of the n-buffer region 8 is low, conductivity modulation does not occur in the low current region. Therefore, as shown by line 33 in FIG. 3, the I-V characteristics of such an element have a much higher on-voltage in the low current region than the IGBT characteristics 32 with a non-collector short structure, and the normally used current Even in this region, the on-voltage does not drop sufficiently and a negative resistance component begins to appear. This negative resistance causes problems such as an increase in losses such as transient on-loss and causes noise generation, and also becomes an obstacle when driving at a high frequency.

FIG. 7 shows an embodiment that improves this point. One difference from FIG. 6 is the shape of the p+ collector region 9, which is wider in the deeper region and narrower in the region closer to the surface. Such a p+ collector region 9 is a separated p+ collector region 9 as in FIG.
After forming region 9, impurities are removed from the intermediate surface of p+
It is formed by forming an n- layer 82 having a resistance similar to that of the n- buffer region 8 by diffusing it to a depth shallower than that of the n-buffer region 8, and further forming an n+ contact layer 83 having a low resistance on its surface layer. Another difference is that the n+ contact layer 8
The insulating film 15 remains on the surface of 3. This insulating film 15 is easily formed by leaving a portion of the gate oxide film 5 when patterning it.

In such an IGBT, an electron current flowing from the n+ emitter region 4 through the channel region 7 into the n− layer 2 due to voltage application passes through the low resistance n buffer region 8 directly under the p+ collector region 9. do. Since the collector electrode 13 is partially insulated, an electron current flows to the n+ contact layer 83, which has a low potential.
+The distance flowing along the collector region 9 becomes longer, a large potential drop occurs with a small current, and conductivity modulation occurs even in the low current region. Furthermore, the conductivity modulation becomes larger,
When the resistance of the n- layer 2 is reduced, current no longer flows along the n+ contact layer 83, so positive feedback due to conductivity modulation is likely to occur, and negative resistance as shown by line 33 in FIG. 3 is less likely to occur. , a reduction in loss during on-time can be achieved. However, in the embodiment shown in FIG. 6, simply providing the insulating film 15 locally between the n+ collector region 81 and the collector electrode 13 is effective in preventing the generation of negative resistance.

Although the n-channel lateral IGBT has been described above, it is clear that the above characteristics can also be obtained in a p-channel lateral IGBT in which the conductivity types are switched. It can also be implemented in other lateral conductivity modulated semiconductor devices such as lateral MOS controlled thyristors (MCTs).

[0016]

According to the present invention, in the RESURF structure, the first layer of the first conductivity type that exists under the second layer of the second conductivity type on the side where the emitter electrode and the collector electrode are provided also has a sub-emitter electrode. By providing and connecting to the emitter electrode,
It is possible to drive a narrow base bipolar transistor between the collector electrode and the emitter electrode, and this transistor has a high hfe, so the on-voltage is low, and the area where conductivity modulation occurs is narrow, so the turn-off time is shortened.
Power loss during switching can be reduced. In addition, since the current of one of the two transistors in parallel is released to the sub-emitter electrode, the concentration of current to the emitter electrode that contacts the emitter region next to the channel region is prevented, and the safe operation area is expanded. We were able to obtain a semiconductor device.

Furthermore, by adopting a collector short structure, it is possible to further reduce power loss during switching, and in that case, by restricting the contact area between the collector electrode and the buffer region, the area of the element can be significantly increased. We were able to make conductivity modulation more likely to occur due to carrier injection from the collector region even in the low current region without having to do so. As a result, it is possible to obtain a low on-voltage in the normally used current range, and it is also less likely to cause problematic negative resistance characteristics such as noise generation. In particular, we were able to obtain a commonly used horizontal IGBT.

[Brief explanation of the drawing]

[Fig. 1] A sectional view of a main part of a horizontal IGBT according to an embodiment of the present invention.

[Figure 2] Cross-sectional view of main parts of a conventional horizontal IGBT

[Fig. 3] Current/voltage characteristic diagrams of lateral IGBTs according to an embodiment of the present invention and a conventional example

[Fig. 4] Horizontal IGBT according to an embodiment of the present invention and a conventional example
Trade-off diagram of turn-off time and saturation voltage

[Figure 5
] Safe operating area diagram of IGBT according to an embodiment of the present invention

FIG. 6 is a sectional view of a main part of a horizontal IGBT according to another embodiment of the present invention.

FIG. 7 is a sectional view of a main part of a horizontal IGBT according to still another embodiment of the present invention.

[Explanation of symbols]

1 p- board 2 n- layer 3 P base region 4 n+ emitter region 5 Gate oxide film 6 Gate electrode 7 Channel area 8 N buffer area 9 p+ collector area 10 p+ embedding area 12 Emitter electrode 13 Collector electrode 14　　　　　Substrate emitter electrode 15 Insulating film 83 Contact layer

Claims (5)

[Claims] Claim 1: A first layer of a first conductivity type, a second layer of a second conductivity type laminated thereon, and a first layer selectively formed within the surface layer of the second layer. a base region of a first conductivity type connected by a region of a conductivity type; a region of a second conductivity type selectively formed in a surface layer of the base region; and a region of the second conductivity type and the second layer. a gate electrode provided on the surface of the base region sandwiched between the surface exposed portions via an insulating film; an emitter electrode commonly in contact with the second conductivity type region and the base region; a buffer region of a second conductivity type and having a higher impurity concentration than the second layer formed on the surface portion away from the base region; and a collector region of the first conductivity type selectively formed in the surface layer of the buffer region. and,
1. A lateral conductivity modulation type semiconductor device having a collector electrode in contact with the collector region thereof, and further comprising a sub-emitter electrode in contact with the first layer and connected to the emitter electrode. 2. A lateral conductivity modulated semiconductor device according to claim 1, wherein the collector region sandwiches the exposed surface portion of the buffer region, and the collector electrode commonly contacts the exposed surface portion of the buffer region and the surface of the collector region. . 3. A lateral conductivity modulation type semiconductor device according to claim 2, wherein an insulating film is locally interposed between the collector electrode and the exposed surface portion of the buffer region. 4. The device according to claim 1, further comprising a first conductivity type buffer region connecting portion extending from the buffer region immediately below the collector region to the collector region, the buffer region connecting portion extending from the bottom of the collector region to the surface. A lateral conductivity modulation type semiconductor device in which the collector electrode is in common contact with the surface of the collector region, and the exposed surface portion of the widened portion is in common contact with the surface of the collector region. 5. A lateral conductivity modulation type semiconductor device according to claim 4, wherein an insulating film is locally interposed between the collector electrode and the exposed surface portion of the buffer region connection portion.