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JPH04217341A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH04217341A
JPH04217341A JP2403096A JP40309690A JPH04217341A JP H04217341 A JPH04217341 A JP H04217341A JP 2403096 A JP2403096 A JP 2403096A JP 40309690 A JP40309690 A JP 40309690A JP H04217341 A JPH04217341 A JP H04217341A
Authority
JP
Japan
Prior art keywords
terminal
resistance
bonding
measured
measuring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2403096A
Other languages
Japanese (ja)
Other versions
JP2589876B2 (en
Inventor
Tadayoshi Seike
清家　忠義
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP2403096A priority Critical patent/JP2589876B2/en
Publication of JPH04217341A publication Critical patent/JPH04217341A/en
Application granted granted Critical
Publication of JP2589876B2 publication Critical patent/JP2589876B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To make possible to measure the contact resistance of wire bonding in a semiconductor, i.e., the resistance at the fused part of a gold wire bonded to an aluminum bonding pad. CONSTITUTION:Two terminals 1, 2 are additionally provided for a terminal 3 measuring the bonding resistance and the two additional terminals 1, 2 are connected, respectively, through two transistors 18, 20 and 19, 21 with the measuring terminal. Only when the bonding resistance is measured, the two additional terminals are switched for measuring and the transistors are turned ON to short-circuit the terminals. A constant current 23 is then fed from one terminal 2 to the measuring terminal 3 and voltage drop across a bonding resistance is measured between the other terminal 1 and the measuring terminal and then the bonding resistance is calculated based on the current and the voltage.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明は、半導体集積回路装置と
くに端子抵抗測定の可能なものに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuit devices, particularly those capable of measuring terminal resistance.

【０００２】0002

【従来の技術】図３は従来のボンディングワイヤと半導
体チップの接続の検査をする半導体集積回路装置の１例
を示すものである。図３において、２５は半導体チップ
、２６はＮ型半導体基板、２７はＮ型半導体基板の上に
形成されたＰ型半導体、２８はシリコンの酸化膜、２９
は中間絶縁膜、３０は金属配線、３１は表面保護膜、３
２はボンディングパッド、３３はボンディングワイヤ、
３４はインナーリード、３５は電源である。2. Description of the Related Art FIG. 3 shows an example of a conventional semiconductor integrated circuit device for inspecting connections between bonding wires and semiconductor chips. In FIG. 3, 25 is a semiconductor chip, 26 is an N-type semiconductor substrate, 27 is a P-type semiconductor formed on the N-type semiconductor substrate, 28 is a silicon oxide film, 29
3 is an intermediate insulating film, 30 is a metal wiring, 31 is a surface protective film, 3
2 is a bonding pad, 33 is a bonding wire,
34 is an inner lead, and 35 is a power supply.

【０００３】このように構成された従来の半導体集積回
路装置について以下その動作を説明する。Ｎ型基板２６
をＧＮＤレベルにし、インナーリード３４に電源３５よ
り負の電位を与える。３４は３２のボンディングパッド
を介し、金属配線３０を通ってＰ型半導体２７と接続さ
れる。Ｎ型半導体基板２６とＰ型半導体２７はＰＮ接合
の順方向となっているので、順方向の電位差がある一定
以上になると２６から２７の方向へ電流が流れる。この
電流はボンディングワイヤ，リード線を通って外へ流れ
出す。ＰＮ接合の順方向に一定電圧がかかるようにし、
電流が流れるかどうかで、ボンディングワイヤと半導体
チップの接続が正常に行なわれているかどうか検査する
ことができる。The operation of the conventional semiconductor integrated circuit device configured as described above will be explained below. N-type substrate 26
is set to GND level, and a negative potential is applied to the inner lead 34 from the power supply 35. 34 is connected to the P-type semiconductor 27 through the bonding pad 32 and the metal wiring 30. Since the N-type semiconductor substrate 26 and the P-type semiconductor 27 are in the forward direction of the PN junction, current flows in the direction from 26 to 27 when the forward potential difference exceeds a certain level. This current flows out through the bonding wire and lead wire. Apply a constant voltage to the forward direction of the PN junction,
It is possible to check whether the bonding wire and the semiconductor chip are properly connected by checking whether current flows.

【０００４】0004

【発明が解決しようとする課題】しかしながら、上記の
従来の構成では、ＰＮ接合の順方向に電流が流れるかど
うかでのワイヤボンディングの検査であったので、ワイ
ヤボンディング接触抵抗（以下ボンディング抵抗と呼ぶ
）の測定，検査ができないとういう問題点を有していた
。[Problems to be Solved by the Invention] However, in the above-mentioned conventional configuration, wire bonding is inspected based on whether or not current flows in the forward direction of the PN junction, so wire bonding contact resistance (hereinafter referred to as bonding resistance) is ) was not able to be measured or inspected.

【０００５】本発明は上記従来の問題点を解決するもの
で、ボンディング接触抵抗の測定のできる半導体集積回
路装置を提供することを目的とする。SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems and aims to provide a semiconductor integrated circuit device capable of measuring bonding contact resistance.

【０００６】[0006]

【課題を解決するための手段】この目的を達成するため
に、本発明の半導体集積回路装置は、被測定端子とチッ
プ内部にこれにアナログスイッチを介して接続する２個
の測定端子を設け、その１個の測定端子より電流を流し
、他の測定端子より電圧を測定できるように構成したも
のである。[Means for Solving the Problems] In order to achieve this object, the semiconductor integrated circuit device of the present invention is provided with a terminal to be measured and two measurement terminals connected inside the chip via an analog switch. The structure is such that current can be passed through one measurement terminal and voltage can be measured from the other measurement terminals.

【０００７】[0007]

【作用】この構成によって、被測定端子のボンディング
抵抗測定時に、外部からアナログスイッチの制御電極に
制御信号を印加して２個のアナログスイッチを閉状態に
して２個の測定端子をそれぞれ被測定端子と接続する。 さらに１個の測定端子から被測定端子に電流を流し、そ
のときのボンディング抵抗による電圧低下を他の測定端
子を用いて測定して、ボンディング抵抗を正確に測定す
ることが可能である。[Operation] With this configuration, when measuring the bonding resistance of the terminal to be measured, a control signal is applied from the outside to the control electrode of the analog switch, the two analog switches are closed, and the two measurement terminals are connected to the terminal to be measured, respectively. Connect with. Furthermore, it is possible to accurately measure the bonding resistance by passing a current from one measurement terminal to the terminal to be measured and measuring the voltage drop caused by the bonding resistance using another measurement terminal.

【０００８】[0008]

【実施例】以下、本発明の一実施例について、図面を参
照しながら説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【０００９】図１は本発明の一実施例における半導体集
積回路装置を示すものである。図１において、１は第１
の測定端子のインナーリード１Ａを有し、２は第２の測
定端子でのインナーリード２Ａを有し、３は被測定端子
でインナーリード３Ａを有し、４は第１の測定端子のボ
ンディングワイヤ、５は第２の測定端子のボンディング
ワイヤ、６は被測定端子のボンディングワイヤ、７は第
１の測定端子のボンディングパッド、８は第２の測定端
子のボンディングパッド、９は被測定端子のボンディン
グパッド、１０および１１はＮチャンネル型ＭＯＳトラ
ンジスタよりなるアナログスイッチ、１２は第１の回路
、１３は第２の回路、１４は半導体チップである。ただ
し、第１の回路および第２の回路とは、この半導体チッ
プの回路を構成する一部の回路である。FIG. 1 shows a semiconductor integrated circuit device according to an embodiment of the present invention. In Figure 1, 1 is the first
2 has an inner lead 1A of the measurement terminal, 2 has the inner lead 2A of the second measurement terminal, 3 has the inner lead 3A of the terminal to be measured, and 4 has the bonding wire of the first measurement terminal. , 5 is a bonding wire of the second measurement terminal, 6 is a bonding wire of the terminal to be measured, 7 is a bonding pad of the first measurement terminal, 8 is a bonding pad of the second measurement terminal, 9 is a bonding of the terminal to be measured Pads 10 and 11 are analog switches made of N-channel MOS transistors, 12 is a first circuit, 13 is a second circuit, and 14 is a semiconductor chip. However, the first circuit and the second circuit are some circuits that constitute the circuit of this semiconductor chip.

【００１０】以上のように構成された半導体集積回路装
置について以下にボンディング抵抗の測定方法を説明す
る。ＮチャンネルＭＯＳトランジスタ１０と１１のゲー
トには、端子抵抗測定時、ハイレベルの電圧が印加され
ともにオン状態にある。また１０と１１は被測定端子の
ボンディングパッド９にそれぞれ接続されている。第１
の測定端子のインナーリードと被測定端子のインナーリ
ード間に電圧計を接続する。また第２の測定端子のイン
ナーリードと被測定端子のインナーリード間に電源およ
び電流計を接続する。端子抵抗測定時には、第１の測定
端子からはトランジスタ１０にのみ、第２の測定端子か
らトランジスタ１１にのみ電流が流れるように状態が固
定されており、またこのとき第１の回路、第２の回路か
らは被測定端子に電流が流れないよう外部からの電圧印
加操作により状態が固定されている。図２は図１を等価
回路にした端子抵抗の測定回路である。図２において１
５は測定端子１の端子抵抗、１６は測定端子２の端子抵
抗、１７は被測定端子の端子抵抗、１８，２０はそれぞ
れアナログスイッチ１０をスイッチとオン抵抗に置き直
したもの、１９，２１はそれぞれアナログスイッチ１１
をスイッチとオン抵抗に置き直したものである。２２は
電圧計、２３は電流計である。２４は外部配線抵抗であ
る。A method for measuring the bonding resistance of the semiconductor integrated circuit device configured as described above will be explained below. At the time of terminal resistance measurement, a high level voltage is applied to the gates of N-channel MOS transistors 10 and 11, and both are in an on state. Further, 10 and 11 are respectively connected to the bonding pad 9 of the terminal to be measured. 1st
Connect a voltmeter between the inner lead of the measurement terminal and the inner lead of the terminal to be measured. Further, a power source and an ammeter are connected between the inner lead of the second measurement terminal and the inner lead of the terminal to be measured. When measuring terminal resistance, the state is fixed so that current flows only from the first measurement terminal to the transistor 10 and from the second measurement terminal to the transistor 11. The state is fixed by external voltage application so that no current flows from the circuit to the terminal under test. FIG. 2 is a terminal resistance measurement circuit that is an equivalent circuit of FIG. 1. In Figure 2, 1
5 is the terminal resistance of the measurement terminal 1, 16 is the terminal resistance of the measurement terminal 2, 17 is the terminal resistance of the terminal to be measured, 18 and 20 are the analog switch 10 replaced with a switch and an on-resistance, respectively, and 19 and 21 are the terminal resistance of the measurement terminal 1. Analog switch 11 each
is replaced with a switch and an on-resistance. 22 is a voltmeter, and 23 is an ammeter. 24 is an external wiring resistance.

【００１１】第２の測定端子から電流Ｉを流したとき、
第１の測定端子の電圧をＶとする。Ｖは被測定端子の端
子抵抗Ｒと外部配線抵抗２４の抵抗値ｒの両端の電位差
である。従ってＶ＝Ｉ（Ｒ＋ｒ）となる。外部配線抵抗
ｒをＲに比べて無視できる大きさにすることによってＶ
≒ＩＲなる関係式が得られる。この関係式により、第２
の測定端子から電流を流し、第１の測定端子で電圧を測
定することにより、被測定端子の端子抵抗を測定するこ
とができる。[0011] When a current I is passed from the second measurement terminal,
Let V be the voltage at the first measurement terminal. V is the potential difference between the terminal resistance R of the terminal to be measured and the resistance value r of the external wiring resistance 24. Therefore, V=I(R+r). By making the external wiring resistance r negligible compared to R, V
A relational expression ≒IR is obtained. According to this relational expression, the second
By passing a current through the measurement terminal and measuring the voltage at the first measurement terminal, the terminal resistance of the terminal to be measured can be measured.

【００１２】なお、図１において、１０，１１は半導体
アナログスイッチとしてＮチャンネル型ＭＯＳトランジ
スタで構成したが、Ｐチャンネル型ＭＯＳトランジスタ
でも、バイパーラトランジスタでも、又バイパーラトラ
ンジスタ，ダイオード等で構成されたアナログスイッチ
でもよい。また、この測定手段としては、一般に電流お
よび電圧の印加，測定をプログラムして行なう自動測定
装置が用いられるが、もちろん他の方法によつても可能
である。In FIG. 1, semiconductor analog switches 10 and 11 are composed of N-channel type MOS transistors, but they may also be composed of P-channel type MOS transistors, bipolar transistors, bipolar transistors, diodes, etc. An analog switch may also be used. Further, as this measuring means, an automatic measuring device is generally used which programs the application and measurement of current and voltage, but of course other methods are also possible.

【００１３】[0013]

【発明の効果】本発明は、被測定端子と別の２端子を接
続する２つのアナログスイッチを設けることにより、端
子抵抗を正確に測定することのできる半導体集積回路装
置を実現できるものである。According to the present invention, by providing two analog switches for connecting a terminal to be measured and two other terminals, it is possible to realize a semiconductor integrated circuit device that can accurately measure terminal resistance.

【図面の簡単な説明】[Brief explanation of the drawing]

【図１】本発明の一実施例である半導体集積回路装置の
回路図FIG. 1 is a circuit diagram of a semiconductor integrated circuit device that is an embodiment of the present invention.

【図２】図１の等価回路図[Figure 2] Equivalent circuit diagram of Figure 1

【図３】従来のボンディングワイヤと半導体チップのコ
ンタクト検査をする場合の回路図[Figure 3] Circuit diagram for conventional bonding wire and semiconductor chip contact inspection

【符号の説明】[Explanation of symbols]

１　　第１の測定端子 ２　　第２の測定端子 ３　　被測定端子 ４，５，６　　ボンディングワイヤ ７，８，９　　ボンディングパッド １０，１１　　Ｎチャンネルトランジスタ１２　　回路
１ １３　　回路２ １４　　半導体チップ １５，１６，１７　　端子抵抗 １８，２０　　トランジスタ１０を置き換えたスイッチ
およびオン抵抗 １９，２１　　トランジスタ１１を置き換えたスイッチ
およびオン抵抗 ２２　　電圧計 ２３　　電流計 ２４　　外部配線抵抗 ２５　　半導体チップ ２６　　Ｎ型半導体基板 ２７　　Ｐ型半導体 ２８　　シリコン酸化膜 ２９　　中間絶縁膜 ３０　　金属配線 ３１　　表面保護膜 ３２　　ボンディングパット ３３　　ボンディングワイヤ ３４　　インナーリード ３５　　電源1 First measurement terminal 2 Second measurement terminal 3 Terminals to be measured 4, 5, 6 Bonding wires 7, 8, 9 Bonding pads 10, 11 N-channel transistor 12 Circuit 1 13 Circuit 2 14 Semiconductor chip 15, 16, 17 Terminal resistance 18, 20 Switch and on-resistance 19, 21 replacing transistor 10 Switch and on-resistance 22 replacing transistor 11 Voltmeter 23 Ammeter 24 External wiring resistance 25 Semiconductor chip 26 N-type semiconductor substrate 27 P-type semiconductor 28 Silicon Oxide film 29 Intermediate insulating film 30 Metal wiring 31 Surface protection film 32 Bonding pad 33 Bonding wire 34 Inner lead 35 Power supply

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】半導体集積回路において、チップ上のボン
ディングパッドと外部リードとこれらを電気的に接続す
るボンディングワイヤとよりなる端子のうち、ワイヤボ
ンディング接触抵抗を測定すべき被測定端子に近接して
、第１および第２の測定端子と第１および第２のアナロ
グスイッチを設け、前記被測定端子と第１および第２の
測定用端子とをそれぞれ第１および第２のアナログスイ
ッチの入力電極および出力電極を介して接続してなるこ
とを特徴とする半導体集積回路装置。1. In a semiconductor integrated circuit, among terminals consisting of bonding pads on a chip, external leads, and bonding wires that electrically connect these, a wire bonding contact resistance is to be measured in the vicinity of the terminal to be measured. , first and second measurement terminals and first and second analog switches are provided, and the terminal to be measured and the first and second measurement terminals are connected to the input electrodes of the first and second analog switches, respectively. A semiconductor integrated circuit device characterized by being connected via an output electrode.
JP2403096A 1990-12-18 1990-12-18 Semiconductor integrated circuit device Expired - Fee Related JP2589876B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2403096A JP2589876B2 (en) 1990-12-18 1990-12-18 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2403096A JP2589876B2 (en) 1990-12-18 1990-12-18 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPH04217341A true JPH04217341A (en) 1992-08-07
JP2589876B2 JP2589876B2 (en) 1997-03-12

Family

ID=18512854

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2403096A Expired - Fee Related JP2589876B2 (en) 1990-12-18 1990-12-18 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JP2589876B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08184646A (en) * 1994-12-28 1996-07-16 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit
US6320805B1 (en) 2000-07-26 2001-11-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with external pins

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08184646A (en) * 1994-12-28 1996-07-16 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit
US6320805B1 (en) 2000-07-26 2001-11-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with external pins

Also Published As

Publication number Publication date
JP2589876B2 (en) 1997-03-12

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