JPH04207216A - Non-overlapping two-phase clock generating circuit - Google Patents

Abstract

PURPOSE:To sufficiently normally operate a circuit regardless of the variance of extents of delay of delay circuits from a design value by providing plural delay circuits which delay first and second phase clocks by different extents of delay. CONSTITUTION:A mask clock CKM inputted to an input terminal 1 is inputted to an inverter 2 and an AND circuit 3, and an output signal inverted CKM of the inverter 2 is inputted to an AND circuit 4. CKA is AND between the output of a NOR circuit 6 and CKM, and the trailing edge of the high level of CKA is determined by that of CKM. CKB is AND between the output of a NOR circuit 5 and the inverted CKM, and the trailing edge of the high level of CKB is determined by that of the inverted CKM. CKA is delayed by delay circuits 7 and 8 to obtain signal A1 and A2, and they are delayed in delay circuits 8 and 10 respectively to obtain signals B1 and B2. Signals A1 and A2 are inputted to the NOT circuit 5 and the AND circuit 4 to output CKB, and it is inputted to circuits 8 and 10, and CKB is outputted from an output terminal 12 as the clock. The clock CKA is outputted from a terminal 11 in the same manner.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock generation circuit, and particularly to a clock generation circuit that generates non-overlapping two-phase clocks.

[Conventional technology]

Figure 5 is a circuit diagram of a conventional non-overlapping two-phase clock generation circuit. In the figure, (1) is an input terminal, (21 (13) (1
4) is an inverter, (3H4] is an AND circuit, (71f
81 is a delay circuit, and (11) and (12) are output terminals.

The two inputs of the AND circuit (3) each have an input terminal (
1) and inverter 3z (14) are connected, the output of the delay circuit (8) is connected to the input of the inverter (14), and the input terminals are connected to the two inputs of the AND circuit (4). (1) is connected to the output of the inverter (2) and the output of the inverter (13), and the input of the inverter (13) is connected to the output of the delay circuit (7).
Also, the output of the AND circuit (3) is connected to the input and output terminal (110) of the delay circuit (7), and the output of the AND circuit (4) is connected to the input and output terminal (12) of the delay circuit (8). The configuration is as follows.

Next, the operation will be explained using the timing chart of FIG. Regarding the signal names in Figure 6, CKM is the master clock input to the input terminal (1), CKM is the inverted signal of the master clock that is the output of the inverter (2), and CKA is obtained from the output terminal (11). The first phase clock, REFCKA, can be obtained from the delay circuit (7).CK
A delayed signal, REFCKA is the inverted signal of REFCKA, which is the output of the inverter (13), and CKB is the output terminal (
12) The second phase clock, REFCKB, obtained from the delay circuit (8) is the delayed signal of CKH, REF, obtained from the delay circuit (8).
CKB is the output of the inverter (14) REFCKB
This is the inverted signal of In addition, RATE is the period of the master clock, TWM is the width of the H level of the master clock, and TD5
is the delay amount of CKA REFCKA, TD6 is CKB
TWA indicates the delay amount of REFCKB, TWA indicates the H level width of CKA, and TWB indicates the H level width of CKB.

The master clock CKM input from the input terminal (1) is input to the inverter (2) and the AND circuit 3. The output signal CKM of the inverter (2) is input to the AND circuit (4). CKA is the inverter (+41) output and C
It is the logical product of KM, and the trailing edge of the H level of CKA is XI
is determined by the trailing edge of the H level. Further, CKB is the logical product of the output of the inverter (13) and CKM, and the trailing edge of CKB's H level is determined by the trailing edge of CKM's H level. (1, KA is delayed by the delay circuit (7) and REFC
KA is obtained and further inverted by an inverter (13) to obtain REFCKA, which is input to an AND circuit (4). From this, the leading edge of CKB's H level is REFC.
It is determined from the leading edge of the H level of KA. AND circuit (4
) is output as the second phase clock from the output terminal (12), and is also sent to the delay circuit (8).
is input. The delayed signal REFCKB of CKB obtained from the delay circuit (8) is further inverted by the inverter (14) to obtain REFCKB, which is input to the AND circuit (3).
) is input. From this, the leading edge of CKA's H level is R
Determine from the H level leading edge of EFCKB.

CKA obtained from the AND circuit (3) is output from the output terminal (1
1) is output as the first phase clock, and
The signal is input to the delay circuit (7). Note that at the initial stage of operation, the outputs of the inverters (13) and (14) are uncertain, and the H levels of CKA and CKB are not determined.
If CKM is at L level, the output of inverter (3) is L.
If CKM is determined to be at L level, the output of the inverter (4) is determined to be at L level, so after CKM falls to L level and after TDI, REFCKA becomes H.
Since REFCK1 rises to the H level TDa after CKM falls to the L level, the H level of CKA and CKB is determined in sequence.

In the circuit shown in Fig. 3, TWA=TWM-TD6...(1)T
WB=RATE-TWM-TD 5...(2), TD5<TWA...(3) TD
6<TWB...If (4) is not satisfied, a correct non-overlapping two-phase clock cannot be obtained.

[Problem to be solved by the invention]

Since the conventional non-overlapping two-phase clock generation circuit was configured as described above, TD5. If TD6 is delayed by more than TWA and TWB, as shown in the timing chart in Figure 7, CKM will rise before REFCKA falls, and CKM will rise before REFCKB falls.
M will rise, making it impossible to obtain a correct non-overlapping two-phase clock. In other words, delay circuits (7) and (8
) does not match the designed value for some reason and the state becomes TD5>TWA, TD6>TWB, the conventional circuit cannot obtain a correct non-overlapping two-phase circuit. Also, TD5>TWA due to variation in the amount of delay with respect to the design value.

To avoid the occurrence of the condition TD6>TWB, TD5,
, T D 6 is shortened in advance, there is a problem that the period during which both the first and second phase clocks are at L level, the so-called non-overlapping period, cannot be made long enough.

This invention was made in order to solve the above-mentioned problems, and the delay amount of the delay circuit fluctuates and becomes large compared to the designed value, so that it can operate properly even in a range where conventional circuits do not operate normally. The purpose of the present invention is to obtain a non-overlapping two-phase clock generation circuit.

[Means to solve the problem]

A non-overlapping two-phase clock generation circuit according to the present invention includes a plurality of delay circuits that delay an output first phase clock by different delay amounts, and uses an inverted signal of an output signal of the delay circuits and an input signal as a reference. and a plurality of delay circuits that obtain a logical product of a mask clock and an inverted signal of the mask clock as a second phase clock, and delay the second phase clock by different delay amounts,
The logical product of the inverted signal of the output signal of this delay circuit and the reference master clock signal is obtained as the first phase clock.

[Effect]

In the non-overlapping two-phase clock generation circuit of the present invention, an output first phase clock is delayed by a plurality of delay circuits having different delay amounts, and an inverted signal of this signal and an inverted signal of a master clock input as a reference are generated. The logical product of
The output second phase clock is delayed by multiple delay circuits with different delay amounts, and the AND of the inverted signal of this signal and the master clock input as a reference is the first phase clock. Become.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is the input terminal, (2) is the inverter,
(31 (41 is an AND circuit, (51 (6) is a NOR circuit,
(7) to (12) are delay circuits, and (11) and (12) are output terminals. The input terminal (1) and the output of the NOR circuit (6) are connected to the two inputs of the AND circuit (3), respectively, and the inputs of the two inputs of the AND circuit (4) are connected to the input terminal (1), respectively. The output of the inverter (2) and the output of the NOR circuit (5) are connected, and the outputs of the delay circuits (7) and (9) are connected to the two inputs of the NOR circuit (5), respectively. The delay circuit (8) and the head output are connected to the two inputs of 6), respectively, and the output of the AND circuit (3) is connected to the output terminal (11) and the inputs of the delay circuits (7) and (9). , the output of the AND circuit (4) is output from the output terminal (1
2) and the inputs of delay circuits (8) and (9).

Next, the operation will be explained using the timing chart of FIG. Regarding the signal names in Figure 2, CKM is the master clock input to the input terminal (1), CKM is the inverted signal of the master clock that is the output of the inverter (2), and CKA is obtained from the output terminal (11). First phase clock, RECK, A1. REFCKA2 is a CKA delay signal obtained from delay circuits (7) and (9), respectively;
CKB is the second phase clock obtained from the output terminal (12), REFCKB 1 and REFCKB2 are the delayed signals of CKB obtained from the delay circuits (8) α, respectively. RATE is the period of CKM, and TWM is the H level of CKM. width, TDI is the delay amount of CKA REFCKAI, TD
2 is the delay amount of CKA REFCKA2, TD3 is CK
Delay amount of BREFCKBl, TD4 is CKB REF
The delay amount of CKB2, TWA is the H level width of CKA, TW
B indicates the H level width of CKB.

Master clock CKM applied to input terminal (1) is input to inverter (2) and AND circuit (3).

The output signal CKM of the inverter (2) is an AND circuit (4)
is input. CKA is the output of the NOR circuit (6) and CKM
The trailing edge of the H level of CKA is determined by the trailing edge of the H level of CKM. Also, CKB is the AND of the output of the NOR circuit (5) and CKM, and CKB
The trailing edge of the H level of CKM is determined by the trailing edge of the H level of CKM. CKA is delayed by delay circuits (7) and (9) to REFCKAI, respectively.

REFCKA2, and CKB is the delay circuit (8) and α
[delayed by REFCKB 1°RE respectively
It becomes FCKB2. In this embodiment, “delay time TD2 of delay circuit (9)”>“delay time TDI of delay circuit (7)”
, 'TDA between delay circuits'>'Delay circuit (8
) delay time TD3''. REFCKAI and R
EFCKA2 is input to the NOR circuit (5) and the EFCKA2 is input to the NOR circuit (5).
) outputs REFCKA1+REFCKA2, which is input to the AND circuit (4). From this, the leading edge of the H level of CKA is determined from the leading edge of the H level of REFCKA1+RE CA. Therefore, AND circuit (4)
CKB is outputted from the output terminal, which is input to the delay circuit (8) and the output terminal, and CKB is obtained from the output terminal (12) as the second phase clock. REFCKB 1 and R
EFCKB2 is input to the NOR circuit (6), and the NOR circuit (
6) outputs REFCKB1+REFCKB2,
This is input to the AND circuit (3). From now on CKA
The leading edge of H level is H of EFCKA1 + REFCKA2
Determined from the leading edge of the level. Therefore, AND circuit (3)
CKA is output from the delay circuits (7) and (9).
), and CKA is input from the output terminal (11) to the first
Obtained as a phase clock. Note that in the initial stage of operation, the output of the NOR circuit (6) and the output of the NOR circuit (7) are not determined, so the high level of CKA and CKB is
Although the level period is not determined, REFCKA1 + REFCKA after TD2 after the L level of CKM is determined.
Since the H level of 2 is determined, the L level of CKM is determined, and the H level of πIFCKB 1+REFCKB2 is determined after TDS, the H level periods of CKA and CKB are determined sequentially.

In Figure 2, the length of one cycle of CKM, which is the master clock, is RATE, the period of CKM is H, and the period is TWM.
, TWA the width of CKA's H and bell.

If CKH is TWB, TWA is TWA=TWM-TDA...(5)TW
B is determined by TWB = RATE - TWM - TD 2 (6), and in order to obtain a correct non-overlapping two-phase clock, TDI < TWA and the H of REFCKAI and REFCKA2.
It is only necessary that the high level periods of REFCKB1 and REFCKB2 overlap if TD3<TWB.

In addition, in the above embodiment, a case was shown in which the circuit was configured using a NOR circuit +51 (61), but as shown in FIG.
The outputs of delay circuits (7) to 001 are connected to inverters (
2) may be used to invert the signal, and the output thereof may be input to the AND circuits (15) and (16).

In addition, in the above embodiment, delay circuits (71 (91 and ()) are provided for each of the first phase clock and second phase clock.
8) Although we have shown the circuit configuration in which there are two 01s, as shown in FIG.
0) may be set to three or more.

〔Effect of the invention〕

As described above, according to the present invention, since a plurality of delay circuits are provided to delay the first and second phase clocks, a device with a wide operating range can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a non-overlapping two-phase clock generation circuit which is an embodiment of the present invention, Fig. 2 is a timing chart explaining the circuit operation of Fig. 1, and Figs. A circuit diagram of a non-overlapping two-phase clock generation circuit showing another embodiment, FIG. 5 is a circuit diagram of a conventional non-overlapping two-phase clock generation circuit, and FIGS. 6 and 7 show the circuit operation of FIG. It is a timing chart for explanation. In the figure, (1) is the input terminal, (2) is the inverter,
(3) (4) is an AND circuit, +51 +61 is a NOR circuit, (7) to α[ are delay circuits, (11) (12) are output terminals, (15) (1B) is a three-person AND circuit, (
17) (18) is a multi-input NOR circuit, (19) (2
0) indicates a delay circuit group consisting of a plurality of delay circuits. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a clock generation device that obtains non-overlapping two-phase clocks of the same frequency from a reference one-phase master clock, a plurality of delay circuits delay the output first-phase clock by different delay amounts, and the output second-phase clock a plurality of delay circuits that delay the outputted second phase clock by different delay amounts; and a plurality of delay circuits that delay the output second phase clock by different delay amounts. The AND of the inverted signal of the signal obtained from the plurality of delay circuits to be delayed and the mask clock is used as the first phase clock,
A non-transitory device characterized in that the logical product of an inverted signal of a signal obtained from a plurality of delay circuits that delay the first phase clock by different delay amounts and an inverted signal of a master clock is outputted as a second phase clock. Duplicate 2-phase clock generation circuit.