JPH04205897A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To easily confirm the used address of a redundancy memory and to discriminate whether or not a long-term fault in service life is in the redundancy memory by detecting a leakage current from an input terminal corresponding to the used address of the redundancy memory. CONSTITUTION:Earth detection circuits added with N-channel transistors 11a-11c connected in series are attached to all input terminals 16 and a fuse 12 is added to a terminator and the terminator is connected to Vcc 15. At the time of normal operations, the input terminals 16 swing from GND to the voltage Vcc. When an address row or line is switched to another row or line by using a redundancy memory, the fuse 12 of the input terminal 16 corresponding to the address row or line is disconnected. In addition, the input terminals 16 where no leakage current flows are made coincident with the row or line addresses of a main memory in advance. Therefore, the address switched to a redundancy memory can be detected.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device having a redundant memory, and particularly to a semiconductor memory device in which the address address of the redundant memory being used can be read out from a packaged product. The present invention relates to memory devices.

[Conventional technology]

A block diagram showing the conventional structure of a semiconductor memory device is shown in FIG. In the figure, (1) is a main memory, (2) is a main memory decoder, (3) is a redundant memory, (4) is a redundant memory decoder, and (5) is a redundant use program circuit.

A circuit diagram of a conventional memory cell array portion is shown in FIG.

In the figure, (1a), (lb), and (lc) are memory cells, (2) is a main memory decoder, (6) is a word line, and (
7a) (7a') (7a") is the human line, (7b
) (7b') (7b'') are bit lines.

Next, the operation will be explained. When using redundant memory, the defective memory column (in the main memory (11) can be removed by disconnecting the fuse in the redundant use program circuit (5).
This is done by electrically reconnecting the line (word line) or row (word line) (hereinafter referred to as address address) to the redundant memo. Normally, this switching of redundant memories is performed in a non-contact wafer state. After that, it is assembled into a packaged product.

Since a defective memory in the main memory (11) is detected in the silicon wafer state and replaced with the redundant memory (3), the address of the redundant memory (3) used by each chip is known, or if the product is packaged, it can be accessed externally. I don't know.

[Invention or problem to be solved]

Conventional semiconductor memory devices are configured as described above, so there is a drawback that it is difficult to tell from the outside whether redundant memory is being used for the address of the packaged product; When looking at the characteristics of a product (e.g. access time)
However, there were problems in that it was not possible to determine whether it was the redundant memory that was deteriorating the characteristics, and it was also difficult to determine whether it was the redundant memory that caused the long-term life failure.

This invention was made in order to solve the above-mentioned problems. Therefore, an external input signal is applied to the address address of the defective main memory and the redundant memory is switched to the redundant memory in the Puff K J Toda product. The object of the present invention is to obtain a semiconductor memory device that detects leakage current.

[Means to solve the problem]

A semiconductor or memory device according to the present invention includes a voltage detection circuit at an input terminal, a transfer gate and a fuse are provided in series at the terminal end of the detection circuit, the fuse terminal is grounded or fixed at a desired voltage, and the transfer gate The opening and closing of is controlled by other input signals.

[Effect]

In the semiconductor memory device of the present invention, the fuse connected to the input terminal is disconnected by making the address correspond to the use of the redundant memory, and the address address of the redundant memory being used is determined depending on the presence or absence of leakage current from the input terminal. It can be sensed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (lla) (llb) (IIc) are N-channel transistors, C2 is a fuse, (13 is an internal circuit inverter, 04 is an internal circuit signal line, C9 is V.C1
αG is an input terminal. FIG. 2 is a block diagram of the memory of FIG. 1. In Figure 2, +1+ is the main memory, (
8) means the defective memory in the main memory (11), and (A) means switching the redundant memory (3) with the defective memory (8).

FIGS. 3 and 4 are a circuit diagram and a block diagram showing an embodiment in which a plurality of redundant memories are replaced with a defective memory. In the figure, αη are other input terminals, (18a) (18b)
(+8c) (18d) is a transfer gate transistor, and C9 is a decoder.

In the figure, the same reference numerals indicate corresponding parts to those in FIG. 1, so the explanation thereof will be omitted.

Next, the operation will be explained. First, a detection circuit in which N-channel transistors (lla) (Ilb) (Ilc) are added in series is attached to all input terminals, which are generally address input terminals, and a fuse α2 is added to the terminal, and V
Connect to cca9. During normal operation, input terminal αe is GN
The voltage swings from D to Vcc. Input terminal 0υ or G
When ND, N channel transistor (IIa) is 0FF
L, no current flows. Furthermore, even if the voltage is increased from GND or higher to about VcC, the source of the N-channel transistor (lie) remains at Vcc, so it is turned off. However, the input terminal voltage is V. (If it is higher than lS and equal to or higher than the V and H drops of N-channel transistors (11a) to (llc), then N-channel transistors (lla) to (Ilc)
Current flows between ONL, input terminal OQ and Vcc.

That is, V to = 1. If OV, the voltage at the input terminal is VC, (5V) +1.0Vx3=8V or more -(1
When set to 1, current flows.

Here, when a column or row of a certain address is switched using the redundant memory, the corresponding fuse 0z of the input terminal αG is cut. If redundant memory is not used, leakage current will flow if 8V or more is applied to all input terminals, or if redundant memory is used, the fuse will be cut, so no leakage current will flow. By making it clear where no leakage current flows through this input terminal and making it match the column or row address of the main memory, it can be detected whether this address has been switched to the redundant memory. The fuse is cut at the same time as the fuse of the redundant use program circuit is cut with a laser.

Now, in the above case, only one redundant memory switching address in a column or row is known. In general, there is an advantage to installing multiple redundant memories, as it increases the recovery rate for defective memories and, in turn, increases the number of good memories.

Next, the case where a plurality of redundant memories are used will be explained with reference to FIGS. 3 and 4.

For example, as shown in FIG. 4, if there are four columns or rows of redundant memories and these are switched, four fuses O2 are added corresponding to each redundant memory, as in the circuit of FIG. 3.

Furthermore, fuse α2 and N-channel transistor (llc
) between the transfer gate transistor (18a) and
(18d) is inserted, and its conduction and non-conduction are controlled by decoding the signal on the other input terminal surface by a decoder (Igl) and using that signal.

First, when checking whether the redundant memory (3a) is used or not, the decoder circuit (19) turns on only the Tranosph T"-transistor (18a) and turns on the other transfer gate transistors (18b), (18c), and (18d'). )
is off. Here, 8 V is applied to the input terminal flfm.
Apply a voltage of G above L:j and sense the presence or absence of leakage current.

Regarding the sensing of the address, as mentioned above,
You can check whether there is any leakage current from all the input terminals that have been made compatible.

In addition, in the above embodiments, the detection circuit is configured only by N-channel transistors (Ila) to (Ilc), or is configured by the fifth transistor.
As shown in the figure, the resistance component of the P-channel transistor ■ may be included, or C3 (chip select) circuit (21)
Continuity may be completely cut off during standby using the control signal CH.

Also, as shown in Figure 6, do not connect the fuse terminal to Vcc.
It may be grounded to ND; in this case, if the voltage of the input terminal ai19 is 3V or more, leakage current will occur.

Any of these methods produces the same effects as the above embodiments.

〔Effect of the invention〕

As described above, according to the present invention, the address address of the redundant memory in use can be known by sensing the leakage current from the input terminal corresponding to the used address of the redundant memory, and the packaged product When looking at the characteristics of
Also, regarding long-term life failures, it is possible to easily determine whether the memory is redundant or not.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor memory device that is an embodiment of the present invention, FIG. 2 is a block diagram of the memory shown in FIG. 1, and FIGS. 3 and 4 show a case where multiple redundant memories are replaced with defective memories A circuit diagram and a block diagram showing one embodiment of this invention, FIGS. 5 and 6 are circuit diagrams of a semiconductor memory device showing another embodiment of this invention, and FIG. 7 is a block diagram of a conventional semiconductor memory device. , FIG. 8 is a circuit diagram of a memory circuit of a memory array portion common to the conventional device and the present invention. In the figure, (11 is the main memory, (3) (3a) to (
3d) is a redundant memory, (81 (8a) to (8d) are defective memories in the main memory, (lla) to (llc) are N-channel transistors, α2 is a fuse, 03 is an inverter, α4 is an internal circuit signal line, 09 is Vcc, (1G is an input terminal, 0'71 is another input terminal, QID (18a) to (
+8d)+transfer gate transistor, (19
1 is a decoder, the wire is a P-channel transistor, (21)
indicates a chip select circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] It has at least a main memory and a redundant memory, a path for transmitting a signal from an input terminal to an internal circuit, and a detection circuit for transmitting a signal when a voltage higher than a predetermined voltage is applied to the input terminal. , a transfer gate and a fuse are connected in series, the end of the fuse is grounded or fixed to a desired voltage, the transfer gate is controlled to be conductive or non-conductive by a control signal from another input terminal, and the cutting of the fuse is redundant. 1. A semiconductor memory device characterized in that an address address of a redundant memory being used can be sensed based on the presence or absence of a leakage current from the input terminal in correspondence with a used address of the memory.