JPH04204273A - Lsi mounting board and data processor - Google Patents

Abstract

PURPOSE:To effectively utilize the scan terminal of an LSI element and perform a test by mounting a scan address decoder circuit, a scan address wire, a scan data writing circuit and a scan reading circuit. CONSTITUTION:A board scan enable signal is given to a board terminal 24 and a board scan address to a board terminal 25 to decode with the use of a scan address decode circuit 23, for instance, an LSI element 112 is chosen to give a scan enable signal to a scan enable terminal 17 so as to be in a test- possible state. Next, when a scan address is applied in another scan address 33, a storage element of the element 112 is chosen and, if '1' is given to the terminal 28 as scan data in this state, it is applied on a scan set terminal 18 through a gate 29 and '1' is written in an inner storage element. And the data read from the storage element are output into a board terminal 35 through a scan reading circuit 34 from a scan-out terminal 21.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an LSI mounting board on which address scan type LSI elements are mounted, and a data processing device equipped with at least one of the LSI mounting boards.

``Prior Art'' In an LSI device, it is possible to address internal storage elements such as flip-flops, latch circuits, and registers, write data to the storage elements, and read data from the storage elements for testing. LS that was made into
There is an I element, and this LSI element is called an address scan type LSI element.

This address scan type LSI device will be briefly explained with reference to FIG. This LSI element 11 has a memory element section 12 consisting of a plurality of memory elements such as flip-flops and latch circuits, and a logic unit that performs various processes as a whole by combining the memory elements in this memory element section 12 and various logic elements. Combinational circuit 1 for configuring a circuit
3, it inputs clear and clock as necessary, inputs data as system input, processes the data and outputs it as system output, and performs its original function as an LSI element. is configured to do so.

Furthermore, in order to test this LSI element 11, this LS
Within the I-element II, an X-decoder 14. Y
A decoder 15 is provided, and when a scan address is supplied to the X decoder 14 and Y decoder 15 through a scan address terminal 16 and a scan enable signal is applied to a scan enable terminal 17, the memory element is When one is selected and data "I" is input to the scan center terminal 18, data "1" is written to the selected memory element, and when data "I" is input to the scan reset terminal 19, the data "1" is written to the selected memory element. The data ladder 0'' is written to the memory element 21, and the data of the selected memory element can be read out and output to the scan readout terminal 21 while the scan enable signal is applied.

By configuring the LSI device in this way, it becomes easy to automatically generate a test pattern for detecting a failure of the LSI device, and it also becomes easy to test the LSI device.

"Problem to be Solved by the Invention" Conventionally, after mounting a scan address type LSI element on a board, or after configuring a data processing device (system) using the LSI mounting board,
For testing the LSI mounting board, testing or monitoring the data processing device, scan address terminal 16, scan enable terminal 17. Scan set terminal 18. Scan reset terminal 19. The scan readout terminals 21 (these are referred to as scan terminals) were not used at all. In other words, the function of the scan address method was used only when the LSI element was used alone, and was not used at all after it was mounted.

The object of the present invention is to provide an LSI mounting board and a data processing device that can effectively utilize the functions of the scan address method even after the LSI elements of the scan address method have been mounted.

"Means for Solving the Problem" According to the invention of claim 1, an address scan type LS
In the LSI mounting board on which the I element is mounted, a scan address decoder circuit, a scan address line commonly connected to the scan address terminal of each LSI element,
A scan write data circuit and a scan read circuit are mounted, and a scan address decoder circuit is enabled by a board scan enable signal to decode a boat scan address and select one of the LSI elements to enable testing. The scan write data circuit is controlled by the write enable signal, and each LSI
According to the invention of claim 2, the scan data is commonly applied to the scan data write terminals of the devices, that is, the scan center terminals or the scan reset terminals, and the scan read circuit performs a logical sum of the data from the scan read terminals of each LSI device. For example, at least one of the LSI mounting boards used in a data processing device is the mounting board according to the invention of claim 1, and the data processing device includes a scan board register, a scan address register, and a scan data register means. The scan board register can select one of the LSI mounting boards and supply a board scan enable signal, and the scan address register can supply a board scan address to the scan address decoder circuit of each LSI mounting board and perform the scan. A scan address is given to the address line, and the scan data register means can give scan data to the scan write data circuit of each LSI mounting board and input the output of the scan read circuit.

According to the third aspect of the invention, most of the LSI mounting boards of the data processing device include address scan type LSIs.
An SI element is mounted, and the LSI mounting board is further equipped with a scan address decoder circuit, a scan address line commonly connected to the scan address terminal of each LSI element, and a scan readout circuit. The circuit becomes operational when a board scan enable signal is applied, and can select one of the LSI elements by decoding the board scan address, and the scan readout circuit performs the logical OR of the data from the scan readout terminals of each LSI element. Output. This data processing device also includes a scan board register that selects one of each LSI mounting board and supplies a board scan ear pull signal, and a scan board register that supplies a board scan address to the scan address decoder circuit of each LSI mounting board, and supplies a scan address to the scan address decoder circuit of each LSI mounting board. A scan address register is provided to provide a scan address to the line.

"Embodiment" FIG. 1 shows an embodiment of the invention of claim 1. This LSI mounting board 22 includes scan address type LSI elements 11 as shown in FIG. ~11. is implemented and these LSI
Element 11. -11. Although not shown in the figure, in order to perform the original data processing, each LSI element 11□ to 1
1. The system input terminal and system output terminal are connected between them, and the system input terminal and system output terminal are connected to a board terminal for external connection of the board 22. Here, only the parts related to this invention are shown.

In this invention, the scan address decoder circuit 23 is mounted on the board 22. This scan address decoder circuit 23 is enabled to operate by the board scan enable signal from the board terminal 24, and decodes the board scan address from the board terminal 25 in the enabled state, and decodes the board scan address from the board terminal 25 to decode the LSI elements 111 to 11. A scan enable terminal is provided to the scan enable terminal 17 of , -, to enable the LSI element to be tested.

A scan data write circuit 26 is also mounted on the board 22. Bumper 2 in scan data writing circuit 26
7, scan data is input from the board terminal 28, and data with the same polarity as that input and data with the opposite polarity are output from the haphazard sofa 27, and these are respectively gated) 29.3
1, and a write enable signal is also supplied from the board terminal 32 to the gates 29 and 31. gate 29
The output of LSI element 11. -11. % to each scan set terminal 18, and the output of gate 31 is supplied to each scan reset terminal 19 of LSt elements 11+ to 1111.

LS11 children 111-11. A scan address line 33 commonly connected to each scan address terminal 16 of 1 is mounted on the board 22. Scan address line 33 is connected to board terminal 25. L given to board terminal 25
The board scan address for selecting the SI element is supplied to the scan address decoder circuit 23, and the board scan address for selecting the SI element is supplied to the scan address decoder circuit 23, and the board scan address for selecting the SI element is sent to the scan address decoder circuit 23. ．． The scan address supplied to each scan address terminal 16 is supplied to the scan address line 33.

A scan readout circuit 34 is mounted on the board 22, and the LS
I element 11. ~11. ．． The outputs of the scan readout terminals 21 are logically summed by the scan readout circuit 34 and output to the board terminal 35. In this example, the output of scan readout circuit 34 is also supplied to gate 36;
The board scan enable signal from the board terminal 24 is supplied as a gate signal to the gate 36, and the output of the gate 36 is output to the board terminal 37.

With this configuration, even after the scan addressing type LSI elements 111 to 117 are mounted on the board 22, the board scan enable signal is applied to the board terminal 24 as needed, and the board scan enable signal is applied to the board terminal 25. A scan address is given and decoded by the scan address decoder circuit 23, and the LSI element 11. ~11. Select one of them, for example 11□, apply a scan enable signal to its scan enable terminal 17 to enable testing, and in this state apply a scan address from the board terminal 25 to the scan address line 33. , one of the memory elements in the LSI element 11□ which has been set to a testable state is selected by the scan address, and in this state, if "1" is given as scan data to the board terminal 28,
This is applied through the gate 29 to the scan set terminal 17 of the LSI element 11 that can be tested, and data "l" is written to the selected memory element. At that time, "0" is sent to the board terminal 28 as scan data. When , the output of the gate 31, that is, the scan reset terminal 19 becomes "1", and data "0" is written into the selected storage element of the LSI element 11g.

The data read from the selected memory element in the LSI element 11g that has been made testable is transferred from the scan readout terminal 21 to the board terminal 3 via the scan readout circuit 34.
5. Even after being mounted on the board 22 in this manner, the LSI elements 11. ~11. can be tested by effectively using the scan terminal. During testing, it is only necessary to apply the board scan enable signal to the board terminal 24 only when necessary, that is, when reading or writing data to the selected memory element.
4 is always supplied with a board scan enable signal, the board 22 is placed in a normal data processing state, and the data state of the memory element selected in the LSI element selected by the board scan address and the scan address is obtained from the gate 36. By observing the output of the board terminal 37 using, for example, an onroscope, it is possible to observe the transition of the internal state during operation.

FIG. 2 shows a plurality of LSIs showing an embodiment of the invention of claim 2.
Mounting board 22. ~22. and the control unit 38 are interconnected through the system bus 39, and the control unit 3B connects the LS
I mounting board 22. ~22° is controlled to perform data processing. This processing result is output from an output terminal not shown in the figure. In this example, LS
I-mounted boards 221-22. Each implements a scan address type LSI element as shown in Figure 1,
In addition, a board is used in which the scan terminal can be effectively used while mounted on the board. In this embodiment, a scan board register 41, a scan address register 42, and a scan data register means 43 are provided as a scan control section 44, and these scan board registers 41. Scan address register 42. Scan data register means 43 is connected to system bus 39. The scan board register 41 controls the LSI mounting boards 221 to 22 .
It is possible to select one of them and supply a board scan enable signal through the board terminal 24 to each scan address decoder circuit 23 (FIG. 1) not shown in the inner diagram.

The scan address register 42 receives the board scan address and scan address from the control unit 38, and the L
SI mounting boards 221-22. A board scan address is supplied to the scan address decoder circuit 23 through each board terminal 25, and a scan address is supplied to the scan address line. The scan data register means 43 reads the LSI mounting board 22 according to instructions from the control section 38.
, ~22. Scan data is provided through each board terminal 28 of the board, and each readout circuit 3 is provided through each board terminal 35.
4 output data can be imported. The write enable is sent from the read/write control unit 45 to each LSI mounting board 22.
．． ~22. The scan data is supplied to the scan data write circuit 26 through the board terminal 32 of the board. Each LSI mounting board 22, ~
22. Each board terminal 37 is individually led out to the outside.

With this configuration, when testing a data processing device, a signal indicating the LSI mounting board to be tested is set in the scan board register 41, and the LSI mounting board, for example 22. A board scan enable signal is given to the board scan enable signal, and in this state, a board scan address and a scan address are set in the scan address register 42,
LSI mounting board 22. ~22. one of them, e.g. 2
Select 2□, and then select one LSI on that board 22□.
select an element, select one memory element in the LSI element, take the memory contents from the board terminal 35 into the scan data register means 43, and then transfer the scan data from the scan data register means 43 to the selected memory element. can be written to. In this way, the scan terminal of the scan address type LSI element mounted in the data processing device can be effectively utilized for testing.

As the scan data register means 43, one register is used to store the scan data read from the LSI element, and after reading this by the control section 38, store the scan data to be written in the register. Alternatively, a register for storing read data and a register for storing scan data to be written may be provided separately.

Furthermore, even when normal data processing is performed by this data processing device, the scan board register 4 is
1, a signal indicating the LSI mounting board to be selected is sent, the board is made to output a board scan enable signal, and in this state, the board scan address and scan address set in the scan address register 42 are used to scan the selected LSI mounting board Changes in the state of the selected memory element in the selected LSI element can be known by observing the output of the board terminal 37.

LSI mounting board 22. ~22. The board scan enable signal may be simultaneously applied to all the terminals 24 of the board, and the state of the selected storage element in the selected LSI element on each board may be simultaneously outputted to each board terminal 37 so that it can be observed simultaneously.

The invention as claimed in claim 3 requires, in the embodiment shown in FIG. 2, a configuration in which the internal state of the selected storage element is monitored particularly during actual data processing.

Therefore, if only the monitoring function using this scan terminal is required, the scan data writing circuit 26 can be omitted in FIG. 1, and the scan data register means 43 and read/write control section 44 can be omitted in FIG. ,
The state of the selected memory element of the selected LSI element of the selected board is monitored. The scan board register 41 may also be omitted, and the board scan enable signal "1" is always applied to the terminal 24 of each board, that is, the boards are always in an operable state, so that each board can be observed simultaneously. Alternatively, the output of the scan readout circuit 34 may be directly supplied to the board terminal 37.

"Effects of the Invention" As described above, according to the invention of claim 1, a scan address decoder circuit, a scan address line, a scan data write circuit, and a scan read circuit are mounted on a board on which scan address type LSI elements are mounted. By doing so, the scan terminal of the LSI element can be effectively utilized for testing.

According to the invention of claim 2, the LS in the data processing device
By making the I-mounting board the LSI-mounting board of the invention of claim 1 and providing a scan board register, a scan address register, and a scan data register, the scan terminals of the LSI elements are effectively used during testing of the data processing device. be able to.

According to the invention of claim 3, in the data processing device,
For boards mounted with scan address LSI elements,
scan address decoder circuit, scan address line,
By implementing the scan readout circuit, it is possible to monitor the state of data in a selected internal storage element using the scan terminal of the LSI element while the data processing device is actually operating.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the invention of claim 1, Fig. 2 is a block diagram showing an embodiment of the invention of claim 2, and Fig. 3 is a block diagram showing an embodiment of the invention of claim 2.
The figure is a block diagram functionally showing a scan address type LSI element.

Claims (3)

[Claims] (1) On a board on which an address scan type LSI element is mounted, a scan that can decode the board scan address to enable testing of one of the LSI elements, and that can be operated by a board scan enable signal. An address decoder circuit, a scan address line commonly connected to the scan address terminals of each of the above LSI elements, and scan write data that is controlled by a write enable signal and commonly supplies scan data to the scan data write terminals of each of the above LSI elements. An LSI mounting board characterized in that a circuit and a scan readout circuit to which data from the scan readout terminals of each of the LSI elements are input are mounted on the board. (2) In a data processing device that operates at least one LSI mounting board in a control section to perform data processing, the LSI mounting board is constituted by the LSI mounting board according to claim 1, and one of the LSI mounting boards is a scan board register which selects and supplies the board scan enable signal to the board scan enable signal; and a scan address register which supplies the board scan address to the scan address decoder circuit of each LSI mounting board and the scan address to the address line, respectively. and scan data register means for applying scan data to the scan write data circuit of each of the LSI mounting boards and to which the output of the scan read circuit is input. (3) In a data processing device that processes data by operating at least one LSI mounting board in a control unit, at least one of the LSI mounting boards has an address scan type LSI element mounted thereon, and the board Decode the scan address and write the above LS
a scan address decoder circuit that can select one of the I elements and is operable by a board scan enable signal; a scan address line that is commonly connected to the scan address terminal of each of the LSI elements; a scan readout circuit to which data from the scan readout terminal of the element is input; a scan board register that selects one of the LSI mounting boards and applies the board scan enable signal to it; A data processing device characterized in that a scan address register is provided for respectively providing the board scan address to the scan address decoder circuit of the board and the scan address to the scan address line.