JPH04168758A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04168758A JPH04168758A JP29359490A JP29359490A JPH04168758A JP H04168758 A JPH04168758 A JP H04168758A JP 29359490 A JP29359490 A JP 29359490A JP 29359490 A JP29359490 A JP 29359490A JP H04168758 A JPH04168758 A JP H04168758A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- lead
- thickness
- semiconductor device
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 229910000679 solder Inorganic materials 0.000 abstract description 11
- 239000011347 resin Substances 0.000 abstract description 5
- 229920005989 resin Polymers 0.000 abstract description 5
- 238000005476 soldering Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000006071 cream Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
この発明は回路基板上に搭載される樹脂封止型の小型半
導体装置に係り、特に表面実装を行う回路基板に使用さ
れる半導体装置に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a resin-sealed small semiconductor device mounted on a circuit board, and particularly to a small semiconductor device mounted on a circuit board. The present invention relates to a semiconductor device.
（従来の技術）
従来、回路基板等に使用される小型樹脂封止型半導体装
置は第５図に示すように構成されている。(Prior Art) Conventionally, a small resin-sealed semiconductor device used for a circuit board or the like is constructed as shown in FIG.
図において、１１は樹脂で構成された外囲器であり、こ
の外囲器１■の側面から複数の外部取出しリード１２、
・・・が導出されている。In the figure, 11 is an envelope made of resin, and a plurality of external leads 12,
... has been derived.
このような半導体装置は一般に回路基板上に表面実装し
て使用される。回路基板としてはセラミック回路基板、
銅張り積層回路基板、銅張り金属回路基板等が使用され
るが、一般的な実装法は、第６図の断面図に示すように
、回路基板１４の配線パターン１５上にメタルマスク等
によりクリーム状の半田１３が印刷され、予備半田が施
こされる。予備半田が施こされた後は回路基板上に、第
５図の半導体装置が搭載される。そして、半導体装置が
搭載された状態で、回路基板が２４０〜２６０℃に熱せ
られた熱板上に乗せられ、半田が溶かされて半導体装置
の取出しリード■２と回路基板上の配線パターン１５と
が電気的に接続される。Such semiconductor devices are generally used by being surface mounted on a circuit board. The circuit board is a ceramic circuit board,
A copper-clad laminated circuit board, a copper-clad metal circuit board, etc. are used, but the general mounting method is to mount a cream onto the wiring pattern 15 of the circuit board 14 using a metal mask or the like, as shown in the cross-sectional view of FIG. A shaped solder 13 is printed and preliminary solder is applied. After preliminary soldering has been applied, the semiconductor device shown in FIG. 5 is mounted on the circuit board. Then, with the semiconductor device mounted, the circuit board is placed on a hot plate heated to 240 to 260°C, and the solder is melted to connect the semiconductor device's lead 2 and the wiring pattern 15 on the circuit board. are electrically connected.
このようにして半導体装置のリードが半田付けされるが
、従来ではリードの厚さが一様にされており、リードの
厚みに比べて半田の高さが低いため、第７図の断面図に
示すように、リード表面の状態により電気的接続が十分
になされず、接続不良が多々発生しており、信頼性に欠
けたものとなっている。The leads of semiconductor devices are soldered in this way, but conventionally the thickness of the leads is uniform and the height of the solder is low compared to the thickness of the leads, so the cross-sectional view in Figure 7 As shown, due to the condition of the lead surface, electrical connection cannot be made sufficiently, and connection failures occur frequently, resulting in a lack of reliability.
（発明が解決しようとする課題）
このように従来の半導体装置では外部取出しリードの厚
みが一様にされているので、回路基板との接続箇所にお
いて半田による電気的接続が十分ではなく、信頼性が低
いものになっている。(Problems to be Solved by the Invention) In this way, in conventional semiconductor devices, the thickness of the external lead is uniform, so the electrical connection by solder is not sufficient at the connection point with the circuit board, resulting in poor reliability. is low.
この発明は上記のような事情を考慮してなされたもので
あり、その目的は回路基板との接続箇所において半田に
よる電気的接続を確実に行うことができ、信頼性が高い
半導体装置を提供することにある。This invention has been made in consideration of the above circumstances, and its purpose is to provide a highly reliable semiconductor device that can reliably perform electrical connection by soldering at the connection point with a circuit board. There is a particular thing.
［発明の構成］
（課題を解決するための手段）
この発明の半導体装置は、外囲器と、上記外囲器から導
出された平板状の外部引出しリードとを具備し、上記外
部引出しリードの回路基板との接続箇所の厚みか他の部
分よりも薄くされてなることを特徴とする。[Structure of the Invention] (Means for Solving the Problem) A semiconductor device of the present invention includes an envelope and a flat external lead lead led out from the envelope, and includes a flat external lead lead led out from the envelope. It is characterized in that the thickness of the connection part with the circuit board is thinner than other parts.
（作 用）
外部引出しリードの回路基板との接続箇所の厚みが他の
部分よりも薄くされていることにより、半田がリードの
上面に十分に這い上がり、これにより電気的接続を確実
に行うことができる。(Function) Since the thickness of the connection part of the external lead to the circuit board is made thinner than other parts, the solder sufficiently creeps up to the top surface of the lead, thereby ensuring a reliable electrical connection. I can do it.
（実施例）
以下、図面を参照してこの発明を実施例により説明する
。(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.
第１図はこの発明に係る半導体装置の斜視図である。こ
の半導体装置は回路基板上に表面実装される小型トラン
ジスタの場合であり、樹脂で構成された直方体状の外囲
器１１内には図示しないトランジスタ・チップが封入さ
れている。また、この外囲器１１の互いに対向する２つ
の側面からは３本の外部取出しリード１２．・・・が引
き出されている。FIG. 1 is a perspective view of a semiconductor device according to the present invention. This semiconductor device is a small transistor that is surface-mounted on a circuit board, and a transistor chip (not shown) is enclosed in a rectangular parallelepiped-shaped envelope 11 made of resin. Also, three external leads 12. ...is brought out.
これら３本のリード１２．・・・はコレクタ、エミッタ
及びベースリードとしてそれぞれ使用されるものであり
、図では２本のリード１２．１２のみを示している。上
記３本のリード１２．・・・のそれぞれは厚みが例えば
５００μｍの金属薄板を打ち抜き加工して形成されてお
り、それぞれ平板状をなしている。These three leads 12. . . are used as collector, emitter, and base leads, respectively, and only two leads 12 and 12 are shown in the figure. The above three leads 12. . . . are each formed by punching a thin metal plate having a thickness of, for example, 500 μm, and each has a flat plate shape.
また、上記３本のリード１２．・・・は外囲器１１の側
面上でほぼ直角に屈曲形成され、さらにそれぞれの先端
は外囲器底部で再びほぼ直角に屈曲形成されている。そ
して、図中、斜線を施した半田１３によって、回路基板
１４上に設けられた配線パターン１５と電気的接続が図
られる各リード１２．・・・の平坦部の厚みは、例えば
押圧加工により当初の厚みである ５００μｍの例えば
半分の２５０μｍに減少している。In addition, the three leads 12. ... are bent at a substantially right angle on the side surface of the envelope 11, and each tip is bent at a substantially right angle again at the bottom of the envelope. Each lead 12 is electrically connected to a wiring pattern 15 provided on a circuit board 14 by solder 13 shaded in the figure. The thickness of the flat portion of .
このような構成の半導体装置を回路基板上に表面実装す
ると、各リード１２の平坦部が他の部分よりも薄くされ
ているため、第２図の断面図に示すように半田１３がリ
ード１２の上面にまで十分に這い上がることができる。When a semiconductor device having such a configuration is surface-mounted on a circuit board, the flat part of each lead 12 is made thinner than the other parts, so the solder 13 is applied to the lead 12 as shown in the cross-sectional view of FIG. You can climb up to the top.
このため、各リード１２と回路基板１４上の配線パター
ン１５との間には十分な電気的接続が確保される。なお
、上記各リード１２゜・・・の平坦部の厚みは当初の５
００μｍの半分の２５０μｍである場合について説明し
たが、これは半田クリーム層の厚み等に関係するが、少
なくとも当初の３７５の厚みである ３００μｍ以下に
されていれば良好な結果を得ることができることが確認
されている。Therefore, sufficient electrical connection is ensured between each lead 12 and the wiring pattern 15 on the circuit board 14. Note that the thickness of the flat part of each lead 12° above is the same as the original 5°.
We have explained the case where the thickness is 250 μm, which is half of 00 μm, but this is related to the thickness of the solder cream layer, etc., but it is clear that good results can be obtained if the thickness is at least 300 μm or less, which is the original thickness of 375. Confirmed.
次に上記半導体装置の製造方法について説明する。Next, a method for manufacturing the above semiconductor device will be explained.
まず、第３図の断面図に示すように一つのり一ド１２上
に半導体チップ１６を載置し、このチップ１６上の表面
電極（図示せず）と他のリード１２とを、例えばＡｕで
構成された金属細線１７により電気的に接続する。次に
樹脂封止を行う。この樹脂封止が終了した状態を第４図
に示す。次に回路基板上に搭載できるように個々の半導
体装置毎にリード１２を切断、分離し、かつ外部引出し
リード１２の曲げ加工を行う。この曲げ加工が行われた
後に平坦部をプレス加工等の方法で押圧し、その部分の
厚みを前記第２の断面図に示すように当初の半分程度に
まで減少させる。この後は前記第６図に示すような方法
により、回路基板上に実装する。First, as shown in the cross-sectional view of FIG. 3, the semiconductor chip 16 is placed on one adhesive 12, and the surface electrode (not shown) on this chip 16 and the other leads 12 are made of, for example, Au. Electrical connection is made by the constructed thin metal wire 17. Next, resin sealing is performed. FIG. 4 shows a state in which this resin sealing is completed. Next, the leads 12 are cut and separated for each individual semiconductor device so that they can be mounted on a circuit board, and the external lead leads 12 are bent. After this bending process is performed, the flat part is pressed by a method such as press working, and the thickness of that part is reduced to about half of the original thickness as shown in the second sectional view. Thereafter, it is mounted on the circuit board by the method shown in FIG. 6 above.
［発明の効果］
以上説明したようにこの発明によれば、回路基板との接
続箇所において半田による電気的接続を確実に行うこと
ができ、信頼性が高い半導体装置を提供することができ
る。[Effects of the Invention] As described above, according to the present invention, it is possible to reliably perform electrical connection by soldering at the connection point with the circuit board, and it is possible to provide a highly reliable semiconductor device.
第１図はこの発明の一実施例に係る半導体装置の外観形
状を示す斜視図、第２図は上記実施例装置の一部の断面
図、第３図は上記実施例装置の製造方法を説明するため
に使用される断面図、第４図は上記実施例装置の製造方
法を説明するために使用される斜視図、第５図は従来装
置の斜視図、第６図は従来装置及び上記実施例装置の製
造方法を説明するために使用される断面図、第７図は従
来装置を説明するために使用される断面図である。
１１・・・外囲器、１２・・・リード、１３・・・半田
、１４・・・回路基板。
出願人代理人 弁理士 鈴江武彦
＝ ７−FIG. 1 is a perspective view showing the external shape of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view of a part of the embodiment device, and FIG. 3 illustrates a method of manufacturing the embodiment device. 4 is a perspective view used to explain the manufacturing method of the above embodiment device, FIG. 5 is a perspective view of the conventional device, and FIG. 6 is a perspective view of the conventional device and the above embodiment. A cross-sectional view used to explain the manufacturing method of the example device, and FIG. 7 is a cross-sectional view used to explain the conventional device. DESCRIPTION OF SYMBOLS 11... Envelope, 12... Lead, 13... Solder, 14... Circuit board. Applicant's agent Patent attorney Takehiko Suzue = 7-
Claims (1)
を具備し、 上記外部引出しリードの回路基板との接続箇所の厚みが
他の部分よりも薄くされてなることを特徴とする半導体
装置。[Scope of Claims] A device comprising an envelope and a flat external lead lead led out from the envelope, wherein the thickness of the connection part of the external lead lead to the circuit board is thinner than other parts. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29359490A JPH04168758A (en) | 1990-11-01 | 1990-11-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29359490A JPH04168758A (en) | 1990-11-01 | 1990-11-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04168758A true JPH04168758A (en) | 1992-06-16 |
Family
ID=17796742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29359490A Pending JPH04168758A (en) | 1990-11-01 | 1990-11-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04168758A (en) |
-
1990
- 1990-11-01 JP JP29359490A patent/JPH04168758A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH08186151A (en) | Semiconductor device and manufacture thereof | |
| JP2001035961A (en) | Semiconductor and manufacture thereof | |
| JPH05226803A (en) | Mounting circuit board | |
| JPH08148635A (en) | Semiconductor device | |
| JPH02134890A (en) | Circuit element mounting board | |
| JPH04168758A (en) | Semiconductor device | |
| JPH0617317Y2 (en) | Connection structure of hybrid integrated circuit | |
| JP2006060106A (en) | Lead member and surface mounted semiconductor device | |
| JP2536568B2 (en) | Lead frame | |
| JP2641912B2 (en) | Lattice array type semiconductor device package | |
| JP2858252B2 (en) | Electrode structure of electronic components for surface mounting | |
| JPH0387051A (en) | Surface mounting type two-terminal semiconductor device | |
| JPH0214558A (en) | Semiconductor integrated circuit device | |
| JPH0119395Y2 (en) | ||
| JPH0456295A (en) | Mounting method for electronic component | |
| JPS6236345Y2 (en) | ||
| JPS5844593Y2 (en) | Beam lead type semiconductor device | |
| JPH04146659A (en) | Semiconductor device and manufacture thereof | |
| JPH046212Y2 (en) | ||
| JPH0585042U (en) | Connection structure of motherboard and sub board | |
| JPS62261129A (en) | Mounting body of electronic parts | |
| JPH04299544A (en) | Manufacture of film carrier semiconductor device | |
| JPH0758234A (en) | Manufacture of semiconductor device | |
| JPH09232378A (en) | Semiconductor chip mounting structure | |
| JPH05102348A (en) | Semiconductor device |