JPH04167564A - Mis transistor - Google Patents

Abstract

PURPOSE:To enable carriers to be efficiently recombined so as to enhance a MIS transistor in high frequency characteristics by a method wherein a region which is of the same conductivity type as a source and lower than the source in impurity concentration or of a conductivity type different from that of the source and lower than a substrate in impurity concentration is provided under the source. CONSTITUTION:A source 2, a drain 3, a gate oxide film 4, a gate electrode 5, and others are formed on an SinO2 insulating substrate 15 to constitute a MIS transistor, where a region of the same conductivity type as the source 2 and lower than the source 2 in impurity concentration or of a conductivity type different from that of the source 2 and lower than the insulating substrate 15 in impurity concentration is provided below the source 2. That is, an N<+> source 2 and an N<+> drain 3 are provided, and an N<-> region 16a is provided to the lower part of the source 2 in contact with a substrate 1b. By this setup, carriers can be efficiently recombined, and a MIS transistor excellent in high frequency characteristics can be realized.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to the structure of MISI-transistors.

(Prior art)) MIS (Metal In5ulator)
Sem1conductor) ) transistor (MIS
FETs (also referred to as FETs) have advantages such as low power consumption and ease of manufacture, and intensive research has been conducted on their processes and structures in recent years.

FIG. 5 is a diagram illustrating the structure and operation of a first conventional SOI MOS transistor.

First conventional example S OI (Silicon On I)
nsulator) MOS (Metal Oxide)
5esiconductor ) ) transistor 4
1 is a type of MISI transistor, and as shown in the figure, it is a semiconductor device in which an MO5 structure is formed on a silicon substrate 18 on an insulator 15 made of 5102.

In the figure, 18 is a P- (low concentration P type) silicon substrate, and 2 is an arsenic (A) silicon substrate in this silicon substrate 18.
N+ (high concentration N type) formed by diffusing impurities such as
3 is a drain formed by the same method as the source 2, 4 is a gate oxide film formed on the silicon substrate 18, and 5 is a polysilicon electrode formed on this gate oxide film 4. Further, a source electrode 6 and a source terminal 7 are formed on the source 2, and a drain electrode 8 and a drain terminal 9 are formed on the drain 3, respectively. By applying an appropriate potential to the source terminal 7 and drain terminal 9 and further applying a voltage to the gate oxide film terminal 10 of the gate oxide film electrode 5, the channel current flowing in the region 18a between the source 2 and the drain 3 is controlled. It is known that it can be done.

In this case, the accelerated high-energy electrons 11 collide with a crystal lattice (not shown) near the drain 3, generating electron-hole pairs 12.13. Since this transistor 41 does not have a substrate contact 14 in FIG. 6, which will be described later, all the holes 13 must be absorbed by the source 2. As the frequency becomes higher, the holes 13 become less absorbed by the source 2 and are accumulated in a portion 20 within the silicon substrate 18.

Region 18b surrounded by source 2 and drain 3 in FIG.
will be hereinafter referred to as the substrate section if necessary.

FIG. 6 is a diagram illustrating the structure and operation of a second conventional MISI transistor.

The MIS transistor 51 of the second conventional example includes a source 2, a drain 3, a gate oxide film 4, a gate electrode 5 made of polysilicon formed on a silicon substrate 19, a substrate contact 14, and the like. Other parts similar to those in FIG. 5 described above will not be described. Further, the operation is almost the same as that in FIG. 5, and the explanation thereof will be omitted.

In the same figure, source 2 and drain 3 are
By shortening the distance between the
1 collides with a crystal lattice (not shown) near the drain 3, generating electron-hole pairs 12.13. Most of the generated electrons 12 are absorbed by the drain 3. On the other hand, regarding the holes 13, some of the holes 13a are absorbed by the substrate contact 14 provided to fix the potential, and the remaining holes 13b are absorbed by the source 2.

(Problems to be Solved by the Invention) First conventional SolMOS having the above configuration
) In the transistor 41 and the old S transistor 51 of the second conventional example, the impurity concentration of the source 2 is high, and the barrier of the PN junction becomes high. Therefore, the generated carriers 12 and 13 cannot cross the barrier, which poses a problem of limiting the high frequency performance of the semiconductor device. In addition, especially in the case of a structure in which only the source 2 absorbs the carriers 13, such as the SOI MOS transistor 41 of the first conventional example, the carriers 13 accumulated on the part 20 of the substrate may cause kinking (
phenomenon in which the drain current bends), overshoot (
There was a problem in that the drain current was not stable for a long time after the switch was turned on.

The present invention has been made with attention to the above points, and an object of the present invention is to efficiently recombine carriers and obtain a transistor with excellent high frequency characteristics.

(Means for Solving the Problems) The Mis) transistor of the present invention has a region configured below the source that is the same as the P type or N type that is the source type and has a lower concentration, or a region that is different from the above. The above-mentioned objective is achieved by providing a region having a shape and having a lower concentration than the substrate.

Here, the above-mentioned type refers to the type of P-type or N-type semiconductor.

(Example) First, the behavior of carriers will be considered from the perspective of energy bands. Since the two conventional examples described above are considered to be substantially the same, the following discussion will be based on SOIMOS transistors.

FIG. 4 is a diagram explaining the energy level of the transistor shown in FIG. 1 and FIG. 5, which will be described later. This is the case with transistors.

In the case of the conventional 501 MOS transistor 41, as the operation becomes faster, the generated holes 13 accumulate in the lower part 20 of the source 2, as shown in FIG.

Since the lower part of the gate oxide film 4, that is, the substrate part 18b, is P-1, and the source 2 is N, high energy is present at the boundary between the source 2 and the substrate part 18b, as shown in FIG. Because of this barrier, the holes 13 cannot enter the source 2, making it difficult for them to recombine. If a region with an intermediate concentration of N+ and P- is created between the N source 2 and the P- substrate part 18b,
), the barrier becomes lower and the source 2 electrons,
Both holes enter this region where recombination takes place.

From the above considerations, it can be seen that a configuration that satisfies the band structure shown in FIG. 4(A) is sufficient.

Next, an example of a transistor invented based on the above consideration will be described in comparison with a conventional example.

FIG. 1 is an enlarged cross-sectional structural diagram showing an example of an SOI MOS) transistor, which is a first embodiment of the Mis) transistor of the present invention.

In this figure, the same elements as those in FIG. 5 described above are given the same numbers, and their explanations will be omitted.

As shown in the figure, a transistor 21 according to the first embodiment of the present invention has a source 2, a drain 3, a gate oxide film 4, a gate electrode 5, etc. formed on a silicon substrate 1 on an insulator 15 made of SiO2. These components are the same as those of the conventional example 51.

The difference between the transistor 21 of the first embodiment of the present invention and the first conventional example 41 is that, as shown in FIG. This is what we have in place.

In general, sources and drains are compatible, and in consideration of this point, a similar region 16b is formed below the drain 3 in FIG. Hereinafter, the lower part of the drain 3 will be shown in the drawings, but will not be described in the text.

FIG. 2 is an explanatory diagram showing the manufacturing process of the transistor shown in FIG. 1.

Hereinafter, the manufacturing method will be explained based on FIGS. 2(a) to 2(f).

(1) As shown in Figure (a), boron (B) is implanted into the silicon layer on the insulator 15 made of SiO2, and P-
A semiconductor substrate 1 is formed. An oxide film (S io
2) is created and used as an oxide film 4A.

(2) As shown in FIG. 4B, a polysilicon layer 5A is formed on the oxide film 4A by diffusion.

(3) As shown in the same figure (C), the polysilicon layer 5
A is etched into a desired shape to form the gate electrode 5.

(4) As shown in FIG. 4(d), arsenic (As) is implanted to form an N+ source 2 and drain 3. At this time, since the polysilicon gate electrode 5 is present, As is not implanted under it and remains as it is, forming the substrate portion 1b. Further, the region immediately below the oxide film 4A becomes a region 1a through which a channel current flows.

(5) Next, phosphorus (P) is injected with high energy.

At this time, adjust the driving energy and adjust the depth as shown in the figure (e
).

The N+ produced by this treatment and the P- of the substrate portion 1b neutralize each other, and the hatched regions 16a and 16b in the figure have a desired concentration of N.
− becomes.

(6) As shown in Figure (f), excluding unnecessary parts of the oxide film 4A, the gate oxide film 4, the electrode of the source 2, and the terminals 6, 7
, electrodes and terminals 8 and 9 of the drain 3, and a gate terminal 10 are provided.

In the MIS transistor 21 of the first embodiment of the present invention, the source 2 and drain 3 are compatible, and the N- region 16a below the source is formed at the same time as the N- region below the drain 3. It is possible to configure region 16b.

Since the SOI MOS transistor 21 of the first embodiment of the present invention efficiently recombines carriers, it is possible to improve problems such as kink and overshoot that the conventional 501 MO3I-transistor has.

FIG. 3 is an enlarged structural sectional view showing a second embodiment of the MISI transistor of the present invention.

In this figure, the same elements as those in FIG. 6 described above are given the same numbers, and their explanations will be omitted.

As shown in the figure, the MIS transistor 31 of the second embodiment of the present invention includes a P- silicon substrate 19, a source 2
, a drain 3, a gate oxide film 4, a gate electrode 5, etc., which are the same as in the second conventional example 51.

MIS of the second embodiment of the present invention) transistor 31 and second
The difference from conventional example 51 is that, as shown in FIG.
- It is configured as follows.

The method for manufacturing the MIS transistor 31 according to the second embodiment of the present invention is based on the Sol MO method according to the first embodiment of the present invention.
S) It is almost the same as the case of transistor 21, and detailed explanation will be omitted.

Although the manufacturing methods are almost the same as described above, there are differences in the resulting structures. It consists of the lower part of source 2 and the lower part of substrate 1.
9 is wider than the corresponding region 16a of the transistor 21 of the embodiment of Section 1 of the present invention. In the case of the embodiment of Section 1 of the present invention, since the source 2 region is in direct contact with the silicon oxide substrate 15, N
-, only the regions 16a and 16b shown in FIG. This is because it has spread to

Although the range of the low concentration region 19b in the second embodiment 31 of the present invention is wide, it is mainly the drain 3 that exhibits the effect.
The effect is not greater than that of the first embodiment of the present invention.

In the second embodiment of the present invention, the generated carriers can be efficiently recombined, so that the increase in channel current due to the accumulation of carriers near the source 2 and the resulting punch-through can be suppressed.

In the first and second embodiments of the present invention described above, the N-channel type was used, but the same holds true even if the P-channel type is used. In this case, the low concentration region according to the present invention, that is, 16a in FIG. 1 and 19b in FIG. 2 are P-.

The limit of lowering the concentration in the region 16a in the first embodiment of the present invention and in the region 19b in the second embodiment is intrinsic, and this case is shown by the dotted line in FIG. 4(A). The effective low concentration limit that constitutes this region can be said to be intrinsic.

(Effects of the Invention) According to the present invention, since the source efficiently absorbs holes generated by hot electrons, a MISh transistor with excellent high frequency characteristics can be obtained. In addition, since it can be produced basically using the same process as conventional methods, there is no increase in cost and it has great industrial value.

[Brief explanation of drawings]

FIG. 1 is an enlarged structural cross-sectional view showing an example of an SOI MOS transistor which is a first embodiment of the MIS transistor of the present invention, FIG. 2 is an explanatory diagram showing the manufacturing process of the transistor shown in FIG. 1, and FIG. 4 is an enlarged structural sectional view showing a second embodiment of the MIS transistor of the present invention, FIG. 4 is a diagram explaining the energy levels of the transistors shown in FIGS. 1 and 5, and FIG. 5 is a diagram showing the first conventional example. FIG. 6 is a diagram illustrating the structure and operation of a SOI MOS (SOI MOS) transistor, which is a second conventional example. DESCRIPTION OF SYMBOLS 1... Silicon substrate (semiconductor substrate), 1b... Substrate part (substrate), 2... Source, 3... Drain, 4...
. . . Gate oxide film, 5 . . . Gate electrode, 16a . . . ) transistor (MIS) transistor), 31... MISI- transistor. Patent applicant: Victor Company of Japan (A) February 4, 1991

Claims (1)

[Claims] M with gate, source, and drain formed on a semiconductor substrate
In an IS transistor, a region is provided below the source, either a region that is the same as the P type or N type that is the source type but has a lower concentration, or a region that is different from the above and has a lower concentration than the substrate. MI characterized by
S transistor.