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JPH04164321A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04164321A
JPH04164321A JP29157990A JP29157990A JPH04164321A JP H04164321 A JPH04164321 A JP H04164321A JP 29157990 A JP29157990 A JP 29157990A JP 29157990 A JP29157990 A JP 29157990A JP H04164321 A JPH04164321 A JP H04164321A
Authority
JP
Japan
Prior art keywords
film
gas
photoresist film
alloy film
oxygen gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29157990A
Other languages
Japanese (ja)
Inventor
Yasuyuki Ono
康行 大野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP29157990A priority Critical patent/JPH04164321A/en
Publication of JPH04164321A publication Critical patent/JPH04164321A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent power wirings from being corroded by a method wherein a dry etching is performed on an aluminum alloy film applied on a substrate using a photoresist film as a mask, the alloy film is patterned and thereafter, an ashing treatment is performed on the photoresist film using the mixed gas of oxygen gas and ammonia gas, then, a plasma treatment using oxygen gas is performed on the power wirings. CONSTITUTION:An Al-0.5% Cu alloy film 2 is subjected to dry etching using a photoresist film 3 as a mask and power wirings 4 are formed. At this time, a chlorine attachment 5 is adhered on the film 3 and the sidewalls of the wirings 4. Then, an ashing treatment is performed on the film 3 using the mixed gas of oxygen gas and ammonia gas and the resist and the attachment are removed. Then, a plasma treatment using oxygen gas is performed on the power wirings and an aluminum oxide film 6 which is a passivation film is formed for preventing the wirings 4 from being reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法に関し、特に半導体基
板上の配線を微細加工する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of finely processing wiring on a semiconductor substrate.

〔従来の技術〕[Conventional technology]

近年、半導体集積回路の高集積化に伴い、アルミニウム
の配線技術においては、各種マイグレーションの発生が
確認され、その抑制のため微量の銅(例えば0.1〜5
%)をアルミニウムに添加する技術が知られており、す
でに量産に導入されている。しかし、アルミニウムに微
量の銅を添加した合金は微細加工する上で数多くの問題
をかかえており、その最も大きなものとして、銅添加に
よる配線の腐食(以下アフターコロ−ジョンと称す)が
報告されている。
In recent years, with the increasing integration of semiconductor integrated circuits, the occurrence of various types of migration has been confirmed in aluminum wiring technology.
%) to aluminum is known and has already been introduced into mass production. However, alloys made by adding a small amount of copper to aluminum have many problems in microfabrication, and the biggest one is reported to be corrosion of wiring due to the addition of copper (hereinafter referred to as after-corrosion). There is.

例えば、重量比0.5%の銅入りアルミニウム合金(以
下AJ−0,5%Cuと称す)を半導体集積回路の配線
材料に用いた従来の配線技術を第3図に示す工程順断面
図を用いて説明する。
For example, a process-order cross-sectional view of a conventional wiring technology using a copper-containing aluminum alloy (hereinafter referred to as AJ-0.5%Cu) with a weight ratio of 0.5% as a wiring material for a semiconductor integrated circuit is shown in Fig. 3. I will explain using

まず、第3図(a)に示すように、半導体基板に所定の
拡散層、絶縁膜等が形成されたものを基板lとし、その
表面にAJ−0,5%Cu合金膜2をスパッタ法により
被着し、その上にフォトリソグラフィー工程により所定
形状のフォトレジスト膜3を形成する。ここで、この後
のフォトレジスト膜3の耐ドライエツチング性を増すた
めに紫外光(UV光)を照射する。
First, as shown in FIG. 3(a), a semiconductor substrate on which a predetermined diffusion layer, an insulating film, etc. have been formed is referred to as a substrate 1, and an AJ-0.5% Cu alloy film 2 is deposited on its surface by sputtering. A photoresist film 3 having a predetermined shape is formed thereon by a photolithography process. Here, in order to increase the dry etching resistance of the photoresist film 3 after this, ultraviolet light (UV light) is irradiated.

次に第3図(b)に示すようにフォトレジスト膜3をマ
スクにしてAffl−0,5%Cu合金膜2を反応性イ
オンエツチング法(RIE法)によりドライエツチング
を行ない、電極配線4を形成する。
Next, as shown in FIG. 3(b), using the photoresist film 3 as a mask, the Affl-0.5% Cu alloy film 2 is dry-etched by reactive ion etching (RIE) to form the electrode wiring 4. Form.

ここで用いられるドライエツチングとしては、三塩化ホ
ウ素(BCff13)と塩素(Cp2)にフロン系ガス
(例えばCF4又はCHF、)を小量添加したガスが一
般に用いられる。この場合は、エツチング後に電極配線
4の側壁及びフォトレジスト膜3の表面に塩化アルミニ
ウム(A!2c℃3)や塩素(Cρ2)付着物(以後塩
素系付着物と称す)5が残存している。
As the dry etching used here, a gas prepared by adding a small amount of fluorocarbon gas (for example, CF4 or CHF) to boron trichloride (BCff13) and chlorine (Cp2) is generally used. In this case, aluminum chloride (A!2c℃3) and chlorine (Cρ2) deposits (hereinafter referred to as chlorine-based deposits) 5 remain on the side walls of the electrode wiring 4 and the surface of the photoresist film 3 after etching. .

次に第3図(c)に示すように、基板1を酸素プラズマ
雰囲気にさらしてフォトレジスト膜3のアッシングを行
なう、しかしながら、アッシング後の電極配線4の表面
からは塩素系付着物5は完全に除去されず、残存した状
態となっている。
Next, as shown in FIG. 3(c), the substrate 1 is exposed to an oxygen plasma atmosphere to ash the photoresist film 3. However, the chlorine-based deposits 5 are completely removed from the surface of the electrode wiring 4 after ashing. It has not been removed and remains.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体装置の製造方法はアルミニウム合
金膜のパターニング後にマスクであるフォトレジスト膜
のアッシングを行なっても、アルミニウム合金膜の側壁
に塩化アルミニウム(AρC(3)や塩素(Cjlz)
を含んだ塩素系付着物が残存しているので、大気中の水
分と反応し塩化水素(HCJ)を形成し、アルミニウム
(AjI)と銅(Cu)の電池作用によってアルミニウ
ム合金の電極配線にアフターコロ−ジョンが発生する欠
点がある。アフターコロ−ジョンは配線断線へとつなが
り製品の信頼性の面からも大きな問題となる。
In the conventional semiconductor device manufacturing method described above, even if the photoresist film serving as a mask is ashed after patterning the aluminum alloy film, aluminum chloride (AρC(3) or chlorine (Cjlz)) is not present on the sidewall of the aluminum alloy film.
Since chlorine-based deposits containing residual chlorine react with moisture in the atmosphere to form hydrogen chloride (HCJ), the battery action of aluminum (AjI) and copper (Cu) causes after-effects on the aluminum alloy electrode wiring. There is a drawback that corrosion occurs. After-corrosion leads to wiring breakage, which poses a major problem in terms of product reliability.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置の製造方法は、基板上に被着したア
ルミニウム合金膜をフォトレジスト膜をマスクとしてド
ライエツチングを行なってバターニングした後に、酸素
カスとアンモニアガスの混合ガスにより前記フォトレジ
スト膜のアッシング処理を行ない、次に酸素ガスによる
プラズマ処理を行ない電極配線を形成するというもので
ある。
In the method for manufacturing a semiconductor device of the present invention, an aluminum alloy film deposited on a substrate is buttered by dry etching using a photoresist film as a mask, and then the photoresist film is etched using a mixed gas of oxygen scum and ammonia gas. Ashing processing is performed, and then plasma processing using oxygen gas is performed to form electrode wiring.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の実施例の工程順断面図である。FIG. 1 is a step-by-step sectional view of an embodiment of the present invention.

はじめに第1図(a)に示すように、半導体基板に所定
の拡散層、絶縁膜等が形成されたものを基板1としてそ
の表面にAρ−0,5%Cu合金膜2をスパッタ法によ
り厚さ約1.0μm膜被着する。その上にフォトリソグ
ラフィー工程により微細パターンのフォトレジスト膜3
を形成する。
First, as shown in FIG. 1(a), a semiconductor substrate on which a predetermined diffusion layer, an insulating film, etc. have been formed is used as a substrate 1, and an Aρ-0.5% Cu alloy film 2 is deposited on its surface by sputtering. A film with a thickness of about 1.0 μm is deposited. On top of that, a photoresist film 3 with a fine pattern is formed by a photolithography process.
form.

ここで、この後のフォトレジスト膜の耐ドライエツチン
グ性の向上を目的として、紫外光(UV光)を照射する
Here, ultraviolet light (UV light) is irradiated for the purpose of improving the dry etching resistance of the photoresist film thereafter.

次に、第1図(b)に示すように、フォトレジスト膜3
をマスクとして、Af−0,5%Cu合金膜2を反応性
イオンエツチング法(RIE法)によりドライエツチン
グを行ない電極配!!4を形成する。この時、フォトレ
ジスト膜3と金属配線4の側壁には塩素系付着物5が付
着している。前述のドライエツチングはバッチ式RIE
装置を用い、ガスはBCII3 : 11005CC,
CI2:50SCCM、CHF3 : IO3CCMの
混合ガスを用いた。エツチング時の圧力は20〜40m
Torrとし、RFパワーは1kWとした。
Next, as shown in FIG. 1(b), the photoresist film 3
Using as a mask, the Af-0.5% Cu alloy film 2 is dry-etched by reactive ion etching (RIE) to form the electrode arrangement! ! form 4. At this time, chlorine-based deposits 5 are attached to the side walls of the photoresist film 3 and the metal wiring 4. The dry etching mentioned above is a batch type RIE.
Using the device, the gas was BCII3: 11005CC,
A mixed gas of CI2:50SCCM and CHF3:IO3CCM was used. Pressure during etching is 20~40m
Torr, and the RF power was 1kW.

次に、第1図(C)に示すように、ドライエツチング終
了後枚葉式プラズマアッシャ−を用いてフォトレジスト
膜のアッシング処理を行ない、レジスト及び塩素系付着
物を除去した。アッシング条件は、02 : 400S
CCM、NH3: 100SCCM、圧カニ 1Tor
r、RFパワー:300W、ウェハー加熱温度:150
’C,処理時間72分の条件とした。次に第1図(d)
に示すように、電極配線にプラズマ処理を行なった。条
件は02  : 500SCCM、圧カニ1Torr、
RFパワー:300W、ウェハー加熱温度:150℃、
処理時間:2分とし、フォトレジストの除去された電極
配線4の表面に不動態の膜である酸化アルミニウム膜6
を形成した。
Next, as shown in FIG. 1C, after the dry etching was completed, the photoresist film was subjected to an ashing process using a single-wafer plasma asher to remove the resist and chlorine-based deposits. Ashing conditions are 02:400S
CCM, NH3: 100SCCM, pressure crab 1 Tor
r, RF power: 300W, wafer heating temperature: 150
'C, the processing time was set to 72 minutes. Next, Figure 1(d)
As shown in Figure 2, the electrode wiring was subjected to plasma treatment. Conditions are 02: 500SCCM, pressure crab 1 Torr,
RF power: 300W, wafer heating temperature: 150℃,
Processing time: 2 minutes, and an aluminum oxide film 6, which is a passive film, is formed on the surface of the electrode wiring 4 from which the photoresist has been removed.
was formed.

第2図は本発明による電極配線を形成した基板を大気中
に放置して、その耐食性を調べた場合の腐食発生までの
時間を示す図である。
FIG. 2 is a diagram showing the time until corrosion occurs when a substrate on which electrode wiring according to the present invention is formed is left in the atmosphere and its corrosion resistance is examined.

第2図に示すように、従来例の半導体ウェハは約12時
間後にアフターコロ−ジョンが発生した。一方、本実施
例の半導体ウェハは170時間経過してもアフターコロ
−ジョンは発生しなかった。
As shown in FIG. 2, after-corrosion occurred in the conventional semiconductor wafer after about 12 hours. On the other hand, no aftercorrosion occurred in the semiconductor wafer of this example even after 170 hours.

なお、A、C−0,5%Cu合金膜の下地に、WやTi
−Nなどのいわゆるバリアメタル膜を設けることも可能
である。
Note that W or Ti is used as the base of the A, C-0,5% Cu alloy film.
It is also possible to provide a so-called barrier metal film such as -N.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、アルミニウム合金膜のド
ライエツチングによるパターニングの後に、酸素く02
)ガスとアンモニア(NH3)ガスの混合ガスによるア
ッシング処理を施し、レジストをアッシングするととも
にアルミニウム合金膜表面に付着しているアフターコロ
−ジョンの原因となる塩化アルミニウム(A!2Cρ3
)や塩素(C,R2)に含まれる塩素成分をアンモニア
によって生じる○H基によって置換して除去する。更に
、クリーンになったアルミニウム合金膜に酸素プラズマ
処理を行ない、表面に不動態の酸化アルミニウム膜を形
成し、アフターコロ−ジョンを誘発させる水分に対する
保護力を強めたのて電極配線の腐食を防止できる効果が
ある。従って、微細配線を用いる製品の信頼性を高める
のに多大な効果がある。
As explained above, in the present invention, after patterning an aluminum alloy film by dry etching,
) gas and ammonia (NH3) gas to ash the resist and remove aluminum chloride (A!2Cρ3
) and chlorine (C, R2) are replaced and removed by ○H groups generated by ammonia. Furthermore, the cleaned aluminum alloy film is subjected to oxygen plasma treatment to form a passive aluminum oxide film on the surface, which strengthens its protection against moisture that can induce after-corrosion and prevents corrosion of electrode wiring. There is an effect that can be done. Therefore, it has a great effect on increasing the reliability of products using fine wiring.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(d)は、本発明の一実施例を説明する
ための工程順断面図、第2図は、本発明を実施した電極
配線の形成された基板を大気中に放置した場合にアフタ
ーコロ−ジョンが発生する迄の時間を従来と比較して示
した図、第3図(a)〜(c)は従来の技術を説明する
ための工程順断面図である。 1・・・基板、2・・・A々−0,5%Cu合金膜、3
・・・フォトレジスト膜、4・・・配線、5・・・塩素
系付着物、6・・・酸化アルミニウム膜。
Figures 1 (a) to (d) are cross-sectional views in the order of steps for explaining an embodiment of the present invention, and Figure 2 shows a substrate on which electrode wiring is formed, in which the present invention is applied, and is left in the atmosphere. FIGS. 3(a) to 3(c) are cross-sectional views in order of steps for explaining the conventional technique. DESCRIPTION OF SYMBOLS 1... Substrate, 2... A-0.5% Cu alloy film, 3
... Photoresist film, 4... Wiring, 5... Chlorine deposits, 6... Aluminum oxide film.

Claims (1)

【特許請求の範囲】 1、基板上に被着したアルミニウム合金膜をフォトレジ
スト膜をマスクとしてドライエッチングを行なってパタ
ーニングした後に、酸素ガスとアンモニアガスの混合ガ
スにより前記フォトレジスト膜のアッシング処理を行な
い、次に酸素ガスによるプラズマ処理を行ない電極配線
を形成することを特徴とする半導体装置の製造方法。 2、アルミニウム合金膜はアルミニウム−銅合金膜であ
る請求項1記載の半導体装置の製造方法。
[Claims] 1. After dry etching and patterning the aluminum alloy film deposited on the substrate using a photoresist film as a mask, the photoresist film is subjected to an ashing process using a mixed gas of oxygen gas and ammonia gas. 1. A method of manufacturing a semiconductor device, comprising: performing plasma treatment using oxygen gas to form electrode wiring. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the aluminum alloy film is an aluminum-copper alloy film.
JP29157990A 1990-10-29 1990-10-29 Manufacture of semiconductor device Pending JPH04164321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29157990A JPH04164321A (en) 1990-10-29 1990-10-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29157990A JPH04164321A (en) 1990-10-29 1990-10-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04164321A true JPH04164321A (en) 1992-06-10

Family

ID=17770756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29157990A Pending JPH04164321A (en) 1990-10-29 1990-10-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04164321A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100274974B1 (en) * 1998-05-29 2001-01-15 황인길 Method for manufacturing metal interconnection of semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5713743A (en) * 1980-06-30 1982-01-23 Toshiba Corp Plasma etching apparatus and etching method
JPS5986224A (en) * 1982-11-09 1984-05-18 Matsushita Electric Ind Co Ltd Removing method of resist

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5713743A (en) * 1980-06-30 1982-01-23 Toshiba Corp Plasma etching apparatus and etching method
JPS5986224A (en) * 1982-11-09 1984-05-18 Matsushita Electric Ind Co Ltd Removing method of resist

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100274974B1 (en) * 1998-05-29 2001-01-15 황인길 Method for manufacturing metal interconnection of semiconductor device

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