JPH04156712A - Automatic frequency controller circuit - Google Patents
Automatic frequency controller circuitInfo
- Publication number
- JPH04156712A JPH04156712A JP2282237A JP28223790A JPH04156712A JP H04156712 A JPH04156712 A JP H04156712A JP 2282237 A JP2282237 A JP 2282237A JP 28223790 A JP28223790 A JP 28223790A JP H04156712 A JPH04156712 A JP H04156712A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- signal
- digital
- converter
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 claims description 3
- 230000006866 deterioration Effects 0.000 abstract description 4
- 230000000063 preceeding effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は受信機の局部発振周波数制御回路に使用される
自動周波数制御回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic frequency control circuit used in a local oscillation frequency control circuit of a receiver.
一般に、S CP C(Single channel
per carrier)方式等の所要帯域幅の狭い
信号を使用して通信を行う場合に、送信機及び中継機内
の局部発振器周波数の経年変化あるいは衛星通信におけ
るドツプラー効果による周波数変動分を受信機において
吸収し、復調器に送出する周波数を一定にしておく必要
がある。例えば、衛星通信においては、親局より通信に
使用する以外の信号を送出しくパイロット信号と呼ばれ
る)、受信局はこのパイロット信号の周波数変動分を検
出し、その検出した信号に対して受信機の局部発振器の
出力周波数を変化させ、復調器に送出する信号の周波数
が一定となるように制御している。In general, S CP C (Single channel
When communicating using a signal with a narrow required bandwidth such as the per carrier system, the receiver absorbs frequency fluctuations due to secular changes in the local oscillator frequency in the transmitter and repeater or the Doppler effect in satellite communications. , it is necessary to keep the frequency sent to the demodulator constant. For example, in satellite communications, the master station sends out signals other than those used for communication (called pilot signals), the receiving station detects the frequency fluctuations of this pilot signal, and the receiver The output frequency of the local oscillator is changed to control the frequency of the signal sent to the demodulator to be constant.
従来、この種の自動周波数制御(以下AFCという)回
路は、第2図に示すように、受信機に入力された信号は
入力端子7Aに入力され、電圧制御発振器8よりの信号
と周波数混合器7において周波数混合され、両信号の差
周波数が出力信号となる。この出力信号の一部は雑音成
分を帯域制限する帯域フィルタ9を通り、周波数位相比
較器5に供給される。Conventionally, in this type of automatic frequency control (hereinafter referred to as AFC) circuit, as shown in FIG. 7, the frequency is mixed, and the difference frequency between both signals becomes an output signal. A part of this output signal passes through a band filter 9 that limits the band of noise components, and is supplied to a frequency phase comparator 5.
一方、基準信号発生器4の出力信号も周波数位相比較器
5に供給され、両者の周波数及び位相が比較される。比
較された結果生ずる周波数誤差、ならびに周波数引き込
み後の位相誤差成分は、電圧制御発振器8に負帰還され
、電圧制御発振器8の周波数又は位相を変化させる。こ
の一連の動作は、周波数位相比較器5の誤差成分がゼロ
となるまで続き、AFC回路の出力周波数は、入力信号
の周波数変化を吸収した常に一定の周波数となる。On the other hand, the output signal of the reference signal generator 4 is also supplied to the frequency phase comparator 5, and the frequency and phase of both are compared. The frequency error resulting from the comparison and the phase error component after the frequency pull-in are negatively fed back to the voltage controlled oscillator 8 to change the frequency or phase of the voltage controlled oscillator 8. This series of operations continues until the error component of the frequency phase comparator 5 becomes zero, and the output frequency of the AFC circuit becomes a constant frequency that absorbs the frequency change of the input signal.
特に、衛星通信の場合には、受信機の信号をロー・ノイ
ズ・コンバーターで一部低い周波数に変換した信号を入
力信号としている。また、ロー・ノイズ・コンバーター
内部の局部発振器は、短期安定度の低いものが用いられ
ていることがあり、受信機に入力される信号の周波数が
瞬時に変動すると、受信機のAFC回路は位相同期が追
つかず同期はずれが生じる。そのために受信機のAFC
回路は周波数掃引を開始する。ここで、受信機のAFC
回路の出力信号は復調器により復調されるので、復調器
の同期もはずれてしまう。また、−般に復調器のキャプ
チャ・レンジは受信機のAtC回路のキャプチャ・レン
ジよりも狭いので、前述のような入力信号周波数の変動
に受信機のAFC回路が追従できた場合には、復調器の
入力信号の周波数も瞬時に大きく変動するので、復調器
の同期がはずれてしまうことがあった。In particular, in the case of satellite communications, the input signal is a signal obtained by partially converting the receiver signal to a lower frequency using a low-noise converter. Additionally, the local oscillator inside the low-noise converter may be one with low short-term stability, and if the frequency of the signal input to the receiver changes instantaneously, the receiver's AFC circuit will lose its phase. Synchronization cannot catch up, resulting in out-of-sync. Therefore, the receiver's AFC
The circuit begins a frequency sweep. Here, the receiver's AFC
Since the output signal of the circuit is demodulated by the demodulator, the demodulator is also out of synchronization. Furthermore, since the capture range of the demodulator is generally narrower than that of the AtC circuit of the receiver, if the AFC circuit of the receiver can follow the fluctuations in the input signal frequency as described above, the demodulator Since the frequency of the input signal to the device also fluctuates greatly instantaneously, the demodulator sometimes loses synchronization.
上述した従来の受信機のAFC回路では、受信信号に周
波数同期をかける際に、その出力信号を復調する復調器
の位相同期はずれも引き起こし、信号系の符号誤り率を
劣化させてしまう欠点がある。The AFC circuit of the conventional receiver described above has the drawback that when applying frequency synchronization to the received signal, it also causes phase synchronization of the demodulator that demodulates the output signal, which deteriorates the bit error rate of the signal system. .
本発明の目的は、上記の問題にかんがみ位相同期までか
けていたものを、周波数同期までしかかけないことによ
り、復調器の同期はずれを回避できるようにして、信号
系の符号誤り率の劣化を防ぐことにある。In view of the above-mentioned problems, an object of the present invention is to avoid the de-synchronization of the demodulator and reduce the deterioration of the bit error rate of the signal system by applying only the frequency synchronization instead of the phase synchronization. The purpose is to prevent it.
本発明の自動周波数制御回路は、外部から入力される信
号を発振周波数を可変にできる電圧制御発振器と周波数
混合器とにより周波数変換信号を出力する第1の手段と
、基準信号発生器の基準信号と前記周波数変換信号とを
比較して周波数差又は位相差の誤差信号を出力する第2
の手段とを有し、前記誤差信号を前記電圧制御発振器に
負帰還する自動周波数制御回路において、
前記第2の手段の出力信号を低域フィルタを通した後に
この誤差信号をディジタル信号に変換するアナログ・デ
ィジタル変換器と、前記ディジタル信号に対応する周波
数誤差信号があらかじめ定められたしきい値の周波数誤
差Δf以内の場合には直前の周波数制御情報を出力し、
前記周波数誤差Δf以上の場合には入力された周波数誤
差信号を零とする周波数制御情報を出力する論理回路と
、前記論理回路のディジタル出力信号をアナログ信号に
変換するディジタルアナログ変換器とを有し、この変換
されたアナログ信号を前記電圧制御発振器に帰還する。The automatic frequency control circuit of the present invention includes a first means for outputting a frequency-converted signal using a voltage-controlled oscillator and a frequency mixer that can vary the oscillation frequency of a signal input from the outside, and a reference signal generator for outputting a frequency-converted signal. and the frequency-converted signal to output an error signal of a frequency difference or a phase difference.
an automatic frequency control circuit that negatively feeds back the error signal to the voltage controlled oscillator, the automatic frequency control circuit comprising: passing the output signal of the second means through a low-pass filter, and then converting the error signal into a digital signal; an analog-to-digital converter, and when the frequency error signal corresponding to the digital signal is within a predetermined threshold frequency error Δf, outputting the immediately preceding frequency control information;
A logic circuit that outputs frequency control information that sets the input frequency error signal to zero when the frequency error is greater than or equal to Δf, and a digital-to-analog converter that converts a digital output signal of the logic circuit into an analog signal. , this converted analog signal is fed back to the voltage controlled oscillator.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例のブロック図である。第1図
の実施例は、周波数混合器7により周波数変換された信
号を帯域フィルタ9に供給し、帯域制限された信号と基
準信号発生器4の出力信号とを周波数位相比較器5で周
波数位相比較を行うまでは従来と同じである。本発明に
おいては、周波数位相比較された信号レベルと、この信
号を低域フィルタ6を通した信号レベルとをそれぞれア
ナログ・ディジタル変換器1でディジタル信号に変換し
て、論理回路2に供給する。ここで、論理回路2は周波
数制御情報の履歴をもっており、通常の周波数変動であ
る周波数誤差情報があるしきい値Δf以下の場合には、
直前の周波数制御情報をディジタル・アナログ変換器(
以後D/A変換器という)3に送出し、Δfを越えた場
合には、周波数誤差が零となる方向の周波数制御情報を
D/A変換器3に送出することにより周波数同期をかけ
る。FIG. 1 is a block diagram of one embodiment of the present invention. In the embodiment shown in FIG. 1, a signal frequency-converted by a frequency mixer 7 is supplied to a bandpass filter 9, and a frequency-phase comparator 5 converts the band-limited signal and the output signal of a reference signal generator 4 into a frequency phase comparator 5. The process is the same as before until the comparison is made. In the present invention, the signal level whose frequency and phase have been compared and the signal level of this signal passed through a low-pass filter 6 are each converted into digital signals by an analog-to-digital converter 1 and supplied to a logic circuit 2. Here, the logic circuit 2 has a history of frequency control information, and when the frequency error information, which is normal frequency fluctuation, is below a certain threshold value Δf,
The previous frequency control information is transferred to the digital-to-analog converter (
If Δf is exceeded, frequency synchronization is performed by sending frequency control information in the direction in which the frequency error becomes zero to the D/A converter 3.
また、周波数誤差情報が瞬時にΔfを越えた場合には、
直前に送出した周波数制御情報をD/A変換器3に送出
する。このような処理により急激な周波数変動に対して
復調器の同期はずれを引き起こすという問題がなくなる
。ここで、低域フィルタ6のカット・オフ周波数をΔf
に選び、あらかじめAFC回路の入出力信号の周波数差
に応じた低域フィルタ6の出力レベルを調べておけば、
AFC回路の入出力信号の周波数差がΔfの範囲内にあ
るかどうかを低域フィルタ6の出力レベルより知ること
ができる。なお、Δfは復調器の同期をはずさない範囲
の値に選ぶ必要がある。D/A変換器3は、論理回路2
からの信号をアナログ信号に変換して電圧制御発振器8
の制御端子に加える。Furthermore, if the frequency error information instantaneously exceeds Δf,
The frequency control information sent just before is sent to the D/A converter 3. Such processing eliminates the problem of demodulator loss of synchronization due to sudden frequency fluctuations. Here, the cut-off frequency of the low-pass filter 6 is Δf
If you select the output level of the low-pass filter 6 in advance according to the frequency difference between the input and output signals of the AFC circuit,
It can be determined from the output level of the low-pass filter 6 whether the frequency difference between the input and output signals of the AFC circuit is within the range of Δf. Note that Δf needs to be selected within a range that does not cause the demodulator to lose synchronization. The D/A converter 3 is a logic circuit 2
The voltage controlled oscillator 8 converts the signal from the
Add to the control terminal of
本実施例を用いた場合のAFC回路の入出力信号の関係
を第3図の動作説明図に示す。A、B。The relationship between the input and output signals of the AFC circuit when this embodiment is used is shown in the operation explanatory diagram of FIG. A, B.
0点のように入力信号と出力信号との周波数差がΔfを
越えた場合には、出力信号の周波数がΔfだけオフセッ
トされる。D、E点のように入力信号の周波数が瞬時に
大きく変動した場合には出力信号の周波数は変化しない
。When the frequency difference between the input signal and the output signal exceeds Δf, as at point 0, the frequency of the output signal is offset by Δf. When the frequency of the input signal changes instantaneously and greatly as at points D and E, the frequency of the output signal does not change.
以上述べたように、本発明は低域フィルタ、A/D変換
器、論理回路、D/A変換器を追加することにより、入
力信号が所定のしきい値のΔfを越えた場合にΔfだけ
オフセットして位相引き込み範囲に周波数を設定し、急
激な周波数変動が生じた場合にその周波数に追従しない
ことにより、復調器の同期はずれを防ぎ信号系の符号誤
り率の劣化を防止できるという効果がある。As described above, the present invention adds a low-pass filter, an A/D converter, a logic circuit, and a D/A converter, so that when the input signal exceeds a predetermined threshold value Δf, By setting the frequency within the phase pull-in range by offsetting and not following the frequency when sudden frequency fluctuations occur, the effect is to prevent the demodulator from losing synchronization and prevent deterioration of the bit error rate of the signal system. be.
第1図は本発明の一実施例のブロック図、第2図は従来
の自動周波数制御回路のブロック図である。第3図は本
実施例の動作説明図である。
1・・・アナログ・ディジタル変換器、2・・・論理回
路、3・・・ディジタル・アナログ変換器、4・・・基
準信号発生器、5・・・周波数位相比較器、6・・・低
域フィルタ、7・・・周波数混合器、8・・・電圧制御
発振器、9・・・帯域フィルタ。FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional automatic frequency control circuit. FIG. 3 is an explanatory diagram of the operation of this embodiment. DESCRIPTION OF SYMBOLS 1... Analog-digital converter, 2... Logic circuit, 3... Digital-analog converter, 4... Reference signal generator, 5... Frequency phase comparator, 6... Low bandpass filter, 7... frequency mixer, 8... voltage controlled oscillator, 9... bandpass filter.
Claims (1)
る電圧制御発振器と周波数混合器とにより周波数変換信
号を出力する第1の手段と、基準信号発生器の基準信号
と前記周波数変換信号とを比較して周波数差又は位相差
の誤差信号を出力する第2の手段とを有し、前記誤差信
号を前記電圧制御発振器に負帰還する自動周波数制御回
路において、 前記第2の手段の出力信号を低域フィルタを通した後に
この誤差信号をディジタル信号に変換するアナログ・デ
ィジタル変換器と、前記ディジタル信号に対応する周波
数誤差信号があらかじめ定められたしきい値の周波数誤
差Δf以内の場合には直前の周波数制御情報を出力し、
前記周波数誤差Δf以上の場合には入力された周波数誤
差信号を零とする周波数制御情報を出力する論理回路と
、前記論理回路のディジタル出力信号をアナログ信号に
変換するディジタルアナログ変換器とを有し、この変換
されたアナログ信号を前記電圧制御発振器に帰還するこ
とを特徴とする自動周波数制御回路。 2、前記論理回路に入力される前記周波数誤差信号が瞬
時に前記周波数誤差Δfを越えた場合には直前の周波数
制御情報を出力することを特徴とする請求項1記載の自
動周波数制御回路。[Claims] 1. A first means for outputting a frequency-converted signal using a voltage-controlled oscillator and a frequency mixer that can vary the oscillation frequency of a signal input from the outside, and a reference signal of a reference signal generator. and a second means for comparing the frequency-converted signal and outputting a frequency difference or phase difference error signal, the automatic frequency control circuit configured to negatively feed back the error signal to the voltage controlled oscillator. an analog-to-digital converter for converting the error signal into a digital signal after passing the output signal of the means through a low-pass filter, and a frequency error signal corresponding to the digital signal having a frequency error Δf of a predetermined threshold If within, output the previous frequency control information,
A logic circuit that outputs frequency control information that sets the input frequency error signal to zero when the frequency error is greater than or equal to Δf, and a digital-to-analog converter that converts a digital output signal of the logic circuit into an analog signal. , an automatic frequency control circuit characterized in that the converted analog signal is fed back to the voltage controlled oscillator. 2. The automatic frequency control circuit according to claim 1, wherein when the frequency error signal input to the logic circuit instantaneously exceeds the frequency error Δf, the immediately preceding frequency control information is output.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2282237A JP3038877B2 (en) | 1990-10-19 | 1990-10-19 | Automatic frequency control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2282237A JP3038877B2 (en) | 1990-10-19 | 1990-10-19 | Automatic frequency control circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04156712A true JPH04156712A (en) | 1992-05-29 |
JP3038877B2 JP3038877B2 (en) | 2000-05-08 |
Family
ID=17649844
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2282237A Expired - Lifetime JP3038877B2 (en) | 1990-10-19 | 1990-10-19 | Automatic frequency control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3038877B2 (en) |
-
1990
- 1990-10-19 JP JP2282237A patent/JP3038877B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP3038877B2 (en) | 2000-05-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5175729A (en) | Radio with fast lock phase-locked loop | |
US5463351A (en) | Nested digital phase lock loop | |
US5416803A (en) | Process for digital transmission and direct conversion receiver | |
AU2001286987B2 (en) | Digital-data receiver synchronization method and apparatus | |
US4348772A (en) | Frequency stabilization circuit for a local oscillator | |
KR100434006B1 (en) | A satellite receiver for digital broadcasting system | |
US5594757A (en) | Method and apparatus for digital automatic frequency control | |
KR900008437B1 (en) | Transmission data demudulation circuit | |
JPS62231548A (en) | Frequency modulated signal receiver | |
JPH06510643A (en) | Clock signal generator for digital television receivers | |
EP0735715B1 (en) | Radio communication terminal station | |
US5896424A (en) | Interference radio wave elimination device and interference radio wave elimination method | |
US5630215A (en) | Radio having a combined PLL and AFC loop and method of operating same | |
IE894026L (en) | Digital automatic frequency control on pure sine waves | |
US4569064A (en) | Device for recovery of clock frequency in digital transmission | |
EP0983659B1 (en) | Clock recovery circuit and a receiver having a clock recovery circuit | |
JPH04156712A (en) | Automatic frequency controller circuit | |
US6081559A (en) | Apparatus for detecting the presence or the absence of a digitally modulated carrier, a corresponding receiver, and a corresponding method | |
HU208201B (en) | Satellite radio receiver | |
WO1997016900A1 (en) | Method and apparatus for symbol timing tracking | |
JP2985376B2 (en) | Automatic frequency control circuit | |
FI72626C (en) | ANORDING FOR COMPENSATION OF FREQUENCY VARIATION IN FM SYSTEM. | |
US6735425B1 (en) | Telephone with a demodulator circuit with an improved local oscillator | |
JPS6166433A (en) | Clock synchronizing circuit | |
JPH05152945A (en) | Automatic frequency gain control circuit |