JPH0414312A - Chopper type comparator - Google Patents

Abstract

PURPOSE:To eliminate a through-current and to reduce current consumption by providing a transistor(TR) controlled by a clock so as to inhibit a through- current from flowing to an inverter amplifier of an amplifier stage for sample- and-hold period. CONSTITUTION:The comparator is provided with a switch 2 controlled by a clock signal phis, a switch 4 controlled by a clock signal phir, an inverter amplifier 6 or the like and also with a 2nd inverter amplifier. The 2nd inverter amplifier consists of a PMOSTR 8 and NMOS TRs 9, 10 and a TR 10 is controlled by a clock phib inverse to the clock phia. Then the TR 10 is interrupted when the inverter amplifier 6 is at a sample-and-hold period, that is, when a node 12 is at an intermediate potential, and no through-current flows different from a conventional comparator. Thus, the through-current of the inverter amplifier at the chopper type comparator output stage is stopped for sample-and-hold period to reduce the current consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a chopper type comparator used in AD converters and the like.

BACKGROUND OF THE INVENTION FIG. 3 is a connection diagram showing the configuration of an example of a conventional chopper type comparator.

First, the configuration of this conventional chopper type comparator will be explained. In FIG. 3, the compared analog signal ■, is input from a terminal 41 and connected to a capacitor 45 via a switch 42 controlled by a clock signal φ3, and the reference voltage V, is input from a terminal 43 and is connected to a capacitor 45 by a clock signal φ. It is connected to a capacitor 45 via a controlled switch 44. The other end of the capacitor 45 is an inverter amplifier 46
The input and output of the inverter amplifier 46 are connected by a switch 47 controlled by a clock signal φ. The output of the inverter amplifier 46 is further input to an inverter amplifier 48, and a comparison output is output from an output terminal 49. Figure 4 shows the CMOS transistors that constitute the 4648 inverter amplifier, 51 is the inverter amplifier input, 52 is the inverter amplifier output, and 53 is the PMOS transistor.
The transistor 54 is an NMOS transistor.

Next, the operation of this chopper type comparator will be explained. FIG. 5 shows φ1. The timing of φ, φ, the voltage waveform of the node 50 output terminal 49, and the inverter amplifier 46
．． 48 shows the current flowing through 48. Period A shown in FIG. 5 is a sample-and-hold period, and B is a comparison period.

During period A, switches 42 and 47 are closed, and switch 44 is closed.
is open, and the input side of the capacitor 45 is at the compared potential V
It is charged in s. On the other hand, the other end of the capacitor 45 is biased to the operating point (2) of the inverter amplifier 46, which is short-circuited by the switch 47. (2) is a potential approximately halfway between the power supply potential and the ground potential. The inverter amplifier 48 has this V.

The potential of VC is input, and similarly, the potential of VC, which is approximately the intermediate potential, is output. At this time, inverter amplifier 46.4
Since the input of 8 is at an intermediate potential, the through current 1.8 is at an intermediate potential as shown in FIG. , IC is flowing.

Moving to the comparison period B, switches 42 and 47 are opened;
The switch 44 closes. The input side of the capacitor 45 is charged with the reference potential V, and the output side of the capacitor 45 is charged with (
V, -V, ) potential changes occur, and the inverter amplifier 46
The signal is amplified by the inverter amplifier 48 and output from the output terminal 49. At this time, current flows transiently through the inverter amplifiers 46 and 48 as shown at 1461 to 148 in FIG. 5, and then the current flows to a steady state.

Note that the above circuit has a configuration of one stage of capacitively coupled inverter amplifier and one stage of inverter amplifier, but in order to increase the gain, the same operation can be achieved with a configuration of two stages of capacitively coupled inverter amplifier and one stage of inverter amplifier. be.

Problems to be Solved by the Invention As mentioned above, in the conventional technology, a through current flows through the inverter amplifier in the amplification stage during the sampling and holding period of the chopper type comparator, increasing the current consumption. was there.

Means for Solving the Problems The present invention is a chopper-type comparator in which a transistor controlled by a clock is added to prevent a through current from flowing through an inverter amplifier in an amplification stage during a sample-and-hold period.

Effect: With this configuration, the through current of the inverter amplifier during the sample and hold period can be eliminated, and the current consumption can be reduced.

Embodiments An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a chopper type comparator in one embodiment of the present invention. 1 is an analog input terminal to be compared, 3 is a reference voltage input terminal, 2 is a switch controlled by a clock signal φ, 4 is a switch controlled by a clock signal φ, 5
is a capacitor, 6 is an inverter amplifier, 7 is a switch controlled by clock signal φ1, 8 is a PMOS transistor, 9 is an NMOS transistor, 10 is a clock signal φ
b is an NMOS transistor whose gate terminal 13 is controlled; 11 is an output terminal; and 12 is an output node of the inverter amplifier 6. FIG. 6 shows the clock timing of this chopper type comparator, the potentials of the node 12 and the output terminal 11, and the current 16. This indicates Is. Switches 2, 4.7 in FIG. 1 operate at the same timing as in the conventional example, and node 12 also shows the same voltage waveform. The inverter amplifier composed of the next-stage PMOS transistor 8 and NMO3I-transistors 9 and 10 is controlled by the clock φ5 of the NMOS transistor 10, which is in opposite phase to the clock φ, and the inverter amplifier 6 is controlled during the sample and hold period, that is, When the node 12 is at an intermediate potential, the NMO3) transistor 10 is cut off, and no through current flows as in the conventional example.

FIG. 2 is a circuit diagram of another type of chopper type comparator according to an embodiment of the present invention. 21 is an analog input terminal to be compared, 22 is a switch controlled by clock signal φ3, 23 is a reference voltage input terminal, 24 is a switch controlled by clock signal φ, 25 is a capacitor, 26 is an inverter amplifier, 27 is a clock A switch 28 is controlled by a clock signal φ. 29 is a PMOS transistor controlled by the gate 33,
30 is an NMOS transistor, 31 is an output terminal, and 32 is an output node of the inverter amplifier 26. Figure 6 shows the clock timing, inverter amplifier 26 and PMOS
Current I26. flowing through transistor 28. I28 is shown. As in the example of FIG. 1, the inverter amplifier 26 is cut off during the sample-and-hold period in the PMOS transistor 28, and no through current flows as in the conventional example.

In both the embodiments of the present invention, FIG. 1 and FIG. 2, the output stage inverter amplifier is cut off during the sample and hold period, so no through current flows and the current consumption is small.

Although the above embodiment is a case in which the capacitively coupled inverter amplifier has one stage, the effect is the same even if there are two stages.

Effects of the Invention As described above, the present invention has the effect of stopping the through current of the inverter amplifier of the chopper type comparator output stage during sample and hold, and reducing the current consumption.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a chopper type comparator which is an embodiment of the present invention, Fig. 2 is a block diagram showing a chopper type comparator which is another embodiment of the invention, and Fig. 3 is a block diagram showing a conventional chopper type comparator. The configuration diagram, Figure 4 is CMOS
FIG. 5 is a diagram of the configuration of an inverter amplifier. FIG. 5 is a timing, potential, and current waveform diagram of a conventional chopper type comparator. FIG. 6 is a diagram of timing, potential, and current waveform of the present invention. 1.21...Analog input terminal, 2,4.72
2.24.27...Switch, 3.23...
...Reference voltage input terminal, 5, 25... Capacitor, 626... Inverter amplifier, 8, 9,
10,2829.30...transistor, 11
．． 31...Output terminal. Name of agent: Patent attorney Shigetaka Awano and one other person Figure 1 Figure 3 Figure 4 Figure 5 AB (Sy3pJ tree) (ratio vt) i・ruto）(、Hiken effect φC -"-1-"-shi- It, Izt-"-knee-L-

Claims (1)

[Claims] a first switch means connected to an input terminal to which a compared analog voltage signal is applied and controlled by a clock signal;
a second switch means connected to an input terminal to which a reference voltage is applied and controlled by the clock signal; and a capacitor whose one plate is commonly connected to each output side of the first and second switch means. a first inverter amplifier whose input side is connected to the other plate of the capacitor; a third switch means that connects the input and output of the first inverter amplifier and controls it with the clock signal; and a second inverter amplifier configured with CMOS that receives the output of the first inverter amplifier as input, and controls a gate between the source of the NMOS transistor of the second inverter amplifier and the ground potential using the clock signal. NMOS
A chopper type comparator comprising a transistor or a PMOS transistor whose gate is controlled by the clock signal between the source of the PMOS transistor of the second inverter amplifier and a power supply potential.