JPH04147665A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To advantageously obtain high integration when a capacitor of big capacity is required by laminating a lower layer wiring, an insulating layer and an upper layer wiring in order on the stepped surface, where a thin oxide film and a thick oxide film are mutually adjoined, of a semiconductor substrate having a formed diffusion layer. CONSTITUTION:A part having a field oxide film 2 forms a projected part and a part having a gate oxide film 3 forms a recessed part. A first wiring 4 and a second wiring 6 constitute a capacitor, generating ups and downs according to unevenness and having a layer insulating film 5 as a dielectric. Provided that specific dielectric constant of the layer insulating film 5 is epsilon1, a thickness is d1 and an opposed area of the first wiring 4 and the second wiring 6 is S1, electrostatic capacity C1 of between the first wiring 4 and the second wiring 6 is to be given by C1=S1.(E0.E1)/d1 so as to be S1=(pir+l).y. That is, electrostatic capacity of (pir+l)/(2r+l) times compared with conventional examples can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit including a capacitor.

[Conventional technology]

A capacitor in a semiconductor integrated circuit according to the prior art will be explained with reference to FIG.

In the capacitor, a first wiring 4 and a second wiring 6 are formed on a flat field oxide film 2 formed on a semiconductor substrate, with an interlayer insulating film 5 serving as a dielectric sandwiched therebetween.

[Problem to be solved by the invention]

The permittivity of vacuum is ε. , the dielectric constant of the oxide film is ε1, the thickness of the insulating film is d1, and the opposing area of the electrodes is S, then the capacitance C is given in proportion to the opposing area of the electrodes.

Therefore, when a large capacitance capacitor is required, the element area becomes large, which is disadvantageous for high integration.

[Means to solve the problem]

In the semiconductor integrated circuit of the present invention, a lower layer wiring, an insulating layer, and an upper layer wiring are sequentially laminated on a stepped surface where a thin oxide film and a thick oxide film are adjacent to each other on a semiconductor substrate on which a diffusion layer has been formed. It is something.

〔Example〕

A first embodiment of the present invention will be described with reference to FIG. 1 and FIG. 2, which is a sectional view taken along the line AB.

As shown in FIG. 2, the area where the field oxide film 2 is located is a convex portion, and the area where the gate oxide film 3 is located is a concave portion. The first wiring 4 and the second wiring 6 use the interlayer insulating film 5 as a dielectric, and are undulated according to the unevenness to form a capacitor.

The relative dielectric constant of the interlayer insulating film 5 is ε4, the thickness is dl, and the first
Assuming that the opposing area of the wiring 4 and the second wiring 6 is 81, the capacitance C1 between the first wiring 4 and the second wiring 6 is given by the following equation. From Figure 1, S 1 = (π r + , e ) · y
[m2 ko (3).

Next, regarding the second embodiment of the present invention, FIG. 3 and its A
This will be explained with reference to FIG. 4, which is a sectional view taken along line B.

If the opposing area of the first wiring 4 and the second wiring 6 in FIG. 4 is S, then the capacitance Crl is given by: From Figure 1, St”(n π r + Σ ! ,, ) ・
y,, [m2 ko (5).

〔Effect of the invention〕

In the case of the first embodiment, the capacitance given by equation (2) can be obtained, and the capacitance with respect to the conventional example can be obtained.

In the case of the second embodiment, the capacitance given by equation (5) can be obtained, and the capacitance with respect to the conventional example can be obtained. Against r! If Σ1vl is sufficiently small, equivalent capacitance can be obtained with an area of approximately 2/π, and the area occupied by the capacitor can be reduced.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention, FIG. 2 is a sectional view taken along the line AB in FIG. 1, FIG. 3 is a plan view showing a second embodiment of the present invention, The figure is a sectional view taken along line AB in FIG. 3, and FIG. 5 is a sectional view showing a capacitor portion of a semiconductor integrated circuit according to the prior art. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Field oxide film, 3...
. . . gate oxide film, 4 . . . first wiring, 5 . . . interlayer insulating film, 6 . . . second wiring.

Claims (1)

[Claims] A semiconductor integrated circuit characterized in that a lower layer wiring, an insulating layer, and an upper layer wiring are sequentially stacked on a stepped surface where a thin oxide film and a thick oxide film are adjacent to each other on a semiconductor substrate on which a diffusion layer has been formed. .