JPH04139882A - Thin film transistor - Google Patents

Abstract

PURPOSE:To facilitate control of dimension so as to be fit to make a size very small, by forming a gate electrode with sidewall made of a polysilicon, at the end part of a wiring in a region of a source being prearranged, and by implanting impurity ions for a source and drain into the silicon oxide film having a uniform film thickness, with which the difference in level of the gate electrode is covered. CONSTITUTION:After a silicon oxide film 4 to come into a gate oxide film is grown, a polysilicon 5 doped with phosphorus is deposited, and by forming the sidewall made of the polysilicon 5 doped with phosphorus only on the side face of the difference in level of a polysilicon 9 doped with phosphorus, a gate electrode is obtained. Then, a silicon oxide film 11 is deposited thereon, and ions are implanted thereinto, and further, after an interlayer insulation film 8 is deposited, reflow-flattening is performed by annealing in the atmosphere of nitrogen. At this time, a source 7 and a drain 7a are formed, by the implanted impurity ions being activated. Thereby, an offset is formed between the drain 7a and the electrode 5, and the length 1 of the offset is equal to the thickness of the oxide film 11. Therefore, by adjusting the thickness of the oxide film 11, the length of the offset can be controlled easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor, and particularly to a thin film transistor using a polysilicon film as a channel layer.

[Conventional technology]

A conventional thin film transistor (T F 1'') will be explained with reference to FIGS. 3(a) to 3(C).

First, as shown in FIG. 3(a), a P-type silicon substrate 1 is steam oxidized to grow a silicon oxide film 2 with a thickness of 5000 nm.

Next, a non-doped polysilicon film 3 with a thickness of 600 nm is deposited by the CVD method, and then a silicon oxide film 4, which will become a gate oxide film, is formed by dry 02 oxidation.

Next, phosphorus-doped polysilicon 5 is grown to a thickness of 3000 nm by CVD, and then phosphorus-doped polysilicon 5, which will become a gate electrode, is formed by photolithography and anisotropic etching.

Next, as shown in FIG. 3(b), a resist 6 is formed to cover from the gate electrode 5 to a part of the planned drain region.

Next, using the photoresist 6 as a mask, phosphorus is injected with an acceleration energy of 30 keV1 in a large amount (dose) of 3 x i o ”
Impurities are introduced into the source-drain region and the gate electrode 5 by Cm-2 ion implantation.

Next, as shown in FIG. 3C, after removing the photoresist 6, heat treatment is performed in an oxidizing atmosphere to activate the previously ion-implanted impurities, thereby forming the source 7, drain 7a and gate electrode 5. form.

Next, an interlayer insulating film 8 made of a BPSG film is deposited by a normal pressure CV l) method.

Next, the interlayer insulating film 8 is reflowed in a nitrogen atmosphere at 900° C. to flatten the surface.

Next, contacts are opened by photolithography and RIE, and then aluminum wiring 12 serving as source-drain and gate electrode wiring is formed to complete the element portion of the TF'T.

[Problem to be solved by the invention]

In the conventional TF'T, a high resistance offset region made of non-doped polysilicon is provided between the drain diffusion layer and the gate electrode to reduce leakage current.

However, the cost -1 due to the addition of a blind exposure process to form a resist pattern to provide an offset area.
- There was a problem with Noboru.

Furthermore, there was the problem that miniaturization would become the nation's greatest strength since it required extra margin.

[Means to solve the problem]

The thin film transistor of the present invention has a first layer on one main surface of a semiconductor substrate.
an insulating film is deposited on a portion of the first insulating film, and a first insulating film is deposited on a portion of the first insulating film.
A second polysilicon film is formed on the entire surface, and a step formed by the first polysilicon film is separated from the second insulating film deposited on the entire surface. A third polysilicon film serving as a side wall is formed, a third insulating film is deposited on the entire surface, and the second polysilicon film is separated from the third polysilicon film by the thickness of the third insulating film.
It has an impurity diffusion region of one conductivity type formed in a polysilicon film.

〔Example〕

Regarding the first embodiment of the present invention, FIGS. 1(a) to (g)
Explain with reference to.

First, as shown in FIG. 1(a), a silicon oxide film 2 having a thickness of 4,000 wafers is formed on a P-type silicon substrate 1. Next, a phosphorus-doped polysilicon film 9 and a silicon nitride film 10 are deposited to a thickness of 4000 by CVD.

Next, the nitride film 10 and the phosphorus-doped polysilicon 9 are anisotropically etched while covering the intended source region with a photoresist (not shown).

Next, as shown in FIG. 1(b), a silicon oxide film 10a having a thickness of 200 mm is formed by steam oxidation.

Next, as shown in FIG. 1(C), only the nitride film 10 is selectively removed using hot phosphoric acid, and then a thickness of 80 mm is removed using the CVD method.
A layer of non-doped polysilicon 3 is deposited.

Next, as shown in FIG. 1(d), a silicon oxide film 4 with a thickness of 200 nm is formed to become a gate oxide film by dry 02 oxidation.
After growing, phosphorus-doped polysilicon 5 is deposited to a thickness of 5,000 wafers by CVD.

Next, as shown in FIG. 1(e), the phosphorus-doped polysilicon 5 is etched back by anisotropic etching to form a sidewall of the phosphorus-doped polysilicon 5 only on the side surface of the step of the phosphorus-doped polysilicon 9. Form. This becomes the gate electrode.

Next, as shown in FIG. 1(f), a silicon oxide film 11 with a thickness of 2,000 wafers is deposited by CVD.

Next, phosphorus is accelerated through the silicon oxide film 11 at an energy of 180 keV and an implantation amount (dose) of 6 x 10'5 cm-2.
Implant ions.

Next, as shown in Figure 1 (g), a B
After depositing an interlayer insulating film 8 made of a PSG film, reflow planarization is performed by annealing in a nitrogen atmosphere. At this time, the ion-implanted impurities are activated and the source 7 and drain 7a are formed.

Next, contacts are opened to the gate electrode 5 and the source-drain 7.7a, an aluminum wiring 12 is formed, and the TPT
The element section is completed.

In this way, an offset is formed between the drain 7a and the gate electrode 5. The offset length 1 is approximately equal to the thickness of the oxide film 1. The offset length can be easily controlled by adjusting the thickness of the oxide film. Since the source 7 is thicker than the drain 7a, its layer resistance is lower.

Next, regarding the second embodiment of the present invention, FIGS.
This will be explained with reference to (C).

In this example, phosphorus is 1! - Form a step in the intended source region by using a silicon oxide film instead of silicone.

First, as shown in FIG. 2(a), a silicon oxide film 2 having a thickness of 1.0 .mu.m is deposited on a P-type silicon substrate 1''2 by the CVD method.

Next, a foot resist (
(not shown) as a mask, the silicon oxide film 2 is deposited to a depth of 50 mm.
Redundancy and notching up to 00 people.

Next, as shown in FIG. 2 (1)), a non-doped polysilicon film 3 is formed on the entire surface, and a silicon oxide film 4 that becomes a gate oxide film is formed.
, phosphorus-doped polysilicon 5 is sequentially deposited.

Next, as shown in FIG. 2C, a gate electrode made of phosphorus-doped polysilicon 5 is formed by etching back, and a silicon oxide film 11 is deposited by CVD.

Next, a source 7 and a drain 7a are formed by ion-implanting phosphorus at an acceleration energy of 100 k e V 1 dose LX 10 I6 cm-''.

Thereafter, the TPT element section is completed through the formation of an interlayer insulating film, contact openings, and aluminum wiring.

〔Effect of the invention〕

A gate electrode is formed by a polysilicon sidewall at the wiring end of the intended source region via a polysilicon channel and a gate oxide film.

Furthermore, a film with a thickness of 7 cm was deposited to cover the step of the gate electrode.
Source-drain impurity ions are implanted through a silicon oxide film of various types.

Therefore, it is recommended that the source-drain and offset regions are all formed using self-aligned lines.

It has the advantage of being easy to control dimensions, suitable for miniaturization, and reducing alignment exposure steps.

[Brief explanation of drawings]

FIGS. 1(a) to (g) are cross-sectional views showing the first embodiment of the present invention in the order of steps, and FIGS. 2(a) to (C) are cross-sectional views showing the second embodiment of the present invention in the order of steps. 3(a) to 3(C) are cross-sectional views showing a method for manufacturing TF'T according to the prior art in the order of steps. 1... P-type silicon substrate, 2... silicon oxide film,
3... Non-doped polysilicon, 4... Silicon oxide 1] L5-*doped polysilicon, 6... Photoresist, 7... Source, 7a... Drain, 8...
・Interlayer insulating film, 9... phosphorus-doped polysilicon, 10.
...Silicon nitride film, 10.11...Licon oxide film, 12...-〇- Aluminum wiring. 10,000 figures 1″ Figure helmet? Figure easy map

Claims (1)

[Claims] A first insulating film is deposited on one main surface of the semiconductor substrate, a first polysilicon film is formed on a part of the first insulating film, a second polysilicon film is formed on the entire surface, and a second polysilicon film is formed on the entire surface. A third insulating film that forms a side wall with respect to a step formed by the first polysilicon film across the second insulating film deposited on the polysilicon film.
a polysilicon film is formed, a third insulating film is deposited on the entire surface, and a third insulating film is formed in the second polysilicon film at a distance from the third polysilicon film by the thickness of the third insulating film. A thin film transistor characterized by having an impurity diffusion region of one conductivity type.