JPH04123466A - Semiconductor device - Google Patents

Abstract

PURPOSE:To stably operate an LSI in which an ON-chip voltage limiter is used, by separating the power sources of a reference voltage generator block and a comparator block from that of an output transistor, and supplying them from separate power source pads. CONSTITUTION:Power for an output transistor T to be supplied to K in which a large transient current flows is supplied from a pad VC2, and power is supplied to a circuit block S including a reference voltage generator block F and a comparator block A from another power pad VC1. Thus, a large transient current flows to the transistor T to be alleviated by a bypass capacitor, and even if noise is induced in the power source, the blocks F, A are stably operated. Since a large current also flows to a low potential side of the K, a power pad VE2 of the K in which large transient current flows similarly to the low potential side is different bonding pad from a pad VE1 for the block S including the blocks F and A.

Description

[Detailed description of the invention]

[Field of Industrial Application] The present invention relates to the configuration of a power supply bonding pad for an integrated circuit (LSI) having a circuit for generating an internal voltage different from an external power supply voltage. [Prior Art] Conventionally, the pin configuration of an ECL type integrated circuit using bipolar transistors is shown in "Motorola MECLnl Series Handbook" or "Hitachi IC Memory Data Book." According to these, the voltage V CC1 applied to the collector of the I) out transistor of the ECL circuit and the voltage V cc applied to other circuits are supplied from separate pins. In this way, when charging and discharging the output load capacitance, the VC
Even if the voltage of Cl fluctuates, it does not affect the internal circuit to which Vcc'z and ■cc2 are applied, so stable operation of the circuit can be guaranteed. [Problems to be Solved by the Invention] What is the so-called on-chip voltage limit that generates an internal voltage different from the externally applied voltage within a chip and operates a large number of MOS or bipolar circuits with this voltage? LSI using /ri method
Then, the following situation similar to the above occurs. In other words, the on-chip voltage limiter consists of: ■ a circuit block that generates a reference voltage (reference voltage generation circuit block); ■ a circuit block that compares the reference voltage and the generated voltage and controls the output transistor (comparison circuit block); ■ an output transistor and However, the output of the on-chip voltage limiter is connected to a number of circuits, such as a CMO8 circuit, through which current flows only during charging and discharging. For this reason, a large transient current flows through the output transistor when charging and discharging a large load capacity, and the reference voltage fluctuates due to the noise of the power supply induced by this, and the comparator circuit cannot operate normally. An object of the present invention is to achieve stable operation of an LSI using such an on-chip voltage limiter. [Means for Solving Problem 11] The above object is to separate the power supply for the reference voltage generation circuit block and the comparison circuit block and the power supply for the output transistor in the on-chip voltage limiter, and supply them from separate power supply pads. This can be achieved by

[Effect]

With the above means, even if a large transient current flows through the output transistor, current is supplied to the reference voltage generation circuit block and the comparison circuit block from separate power supply pads, so that they can operate stably. Further, as a result, the generation of the reference voltage and the control of the output transistor can be performed well, so that the desired voltage and current can be supplied from the internal power supply terminal, and the entire LSI can operate stably.

【Example】

The present invention will be explained in detail below. FIG. 1 is a diagram showing a first embodiment of the present invention. In FIG. 1, F is a reference voltage generation circuit block whose output terminal is E, and A is a comparison circuit block whose output terminal is P.゛The above circuit blocks A and F are collectively designated as block S. T is an output transistor, and its output terminal is ■L. Here, a bipolar transistor is used as the output transistor, and it supplies a power supply current with a high current supply capability, and uses a VBE drop to generate a low voltage necessary for the fine MO8. Also, K is a circuit block where current flows only during charging and discharging, like the CMO8 circuit, and C is a terminal v
Is is a bypass capacitor to keep voltage fluctuations small, and Is is a small current source to generate a constant voltage even during standby. Vc and vC2 are power supply pads on the high potential side, and VE and VH2 are power supply pads on the low potential side. In these circuit blocks, the power for the output transistor T, which is supplied to K through which a large transient current flows, is supplied from the Vcz pad, and the circuit block S, which includes F and A, has a
It is supplied from a separate power supply pad Vc. As a result, even if a large transient current flows through the output transistor T and noise is induced in the power supply, although it is alleviated by the bypass capacitor, the reference voltage generation circuit block F and comparison circuit block A operate stably (with high precision). do. Since a large current flows also on the low potential side of K, the power supply pad VE of K, through which a large transient current also flows on the low potential side, is connected to the block S including the reference voltage generation circuit block F and the comparison circuit block A.
The padding pad is different from the pad VE1 used for this purpose. According to this embodiment, in addition to the power supply pad c2 for the output transistor T through which a large transient current flows, a power supply pad Vc for the block S including the reference voltage generation circuit block F and the comparison circuit block A is provided. A stable VL can be generated. This Vt is a voltage VBE lower than the voltage of the 8-power terminal P of S, so if the Vt voltage is stabilized, VL
This is because it is also stable. Note that although voltages of the same potential are normally applied to both type source pads, different voltages may be applied depending on the purpose. The same applies to VE□ and Vl:z. Also, the bypass capacitor C is set to M as shown in FIG.
When configuring using an OS, it is preferable to use a MOS with a small threshold value or a depression type MOS. In this way, a capacitance is always formed regardless of the potential of Vt. For this purpose, it is preferable to use a triple well structure as disclosed in Japanese Patent Application Laid-Open No. 62-119958 so that the same conductive layer as the source/train always exists directly under the gate. In Fig. 1, a bipolar transistor is used for the output transistor T, but when using a process that can only produce CMOS, or due to the need for temperature compensation/process variation compensation, or due to the relationship between the generated voltage and the power supply voltage, the output transistor T shown in Fig. 2 is used. And as shown in FIG. 3, MOS transistors may have to be used. In this case as well, stable operation can be achieved by separately providing the power supply pad vc2 for the output transistor T and the power supply pad Vcm for the circuit block S for generating and comparing reference voltages. FIG. 4 shows an embodiment in which the embodiment shown in FIG. 1 is more specifically described. The reference voltage generation circuit block F consists of a bandgap generator using a bipolar transistor, a circuit that converts the voltage at the 8-power terminal BG of the bandgap generator into a desired reference voltage, and generates it at the terminal E, and an aging circuit. There is. Regarding the detailed configuration and operation of these circuits, a description of similar circuits can be found in IEE, Journal of Solid State Circuits, Vol. 24. No. 3, pages 597 to 602 (IEEE. Journal of 5olid-8tateC
circuits, vol, 24. No, 3゜pp, 59
7 to 6o2) are detailed, so they are omitted here. The feature of this circuit block F is that the reference voltage generated at the terminal E has small temperature dependence and process dependence. Note that VR is a terminal that generates a reference voltage for a bipolar current switch that constitutes an ECL input circuit block that will be described later. Circuit block A is a circuit that compares a reference voltage and a generated voltage to control the output transistor. In this figure, resistance R, bipolar Q = Qz −M
It is constituted by a differential amplifier circuit consisting of O8Mp, current source MOS Ms, and MH2. The other configurations and functions are the same as the embodiment shown in FIG. By using the circuit of the embodiment shown in FIG. 4 and supplying power to the circuit block S from the power supply pad Vc2 for the output transistor T and another power supply pad Vc, the circuit block F has low temperature dependence and process variation dependence. It is possible to generate a reference voltage that is not affected by power supply noise while maintaining the characteristics of the above. As a result, the generation of the reference voltage and the control of the output transistor can be performed with high accuracy, so that the desired voltage and current can be supplied from the internal power supply terminal, and the entire LSI can operate stably. Now, as a circuit block through which current flows only during charging and discharging, various circuit blocks other than the CMO8 circuit can be considered. Here, K is a dynamic random access memory (D
A case will be explained in which a memory array (RAM) is included. DRAMs have so far been mainly used with TTL interfaces. In the case of a TTL interface DRAM, the circuit is configured such that current flows almost only during charging and discharging. Therefore, the entire DRAM can be considered to be a circuit block. However, with the miniaturization of MOS and the use of BiCMO5, high-speed RAM has become possible, and DRAM with an ECL interface used in systems using such high-speed memory is also being developed. In the case of an ECL interface, it is easier and more efficient to configure the circuit using a bipolar current switch circuit in the input/output section. In a bipolar current switch circuit, the current is CMO
Unlike the S circuit, which only flows during charging and discharging, a constant current flows all the time. In other words, an ECL interface DRAM has a constant current circuit block mainly consisting of a bipolar current switch circuit in the input/output section, and a CM
It consists of circuit blocks having the same performance as K, such as decoders and word drivers, which are constructed of O8 or BiCMO8 circuits, and in which current flows only during charging and discharging. Further, in this bipolar current switch circuit, the internal high potential side power supply voltage cannot be lowered as much as the voltage at the terminal VL. However, the CMOS circuit constituting K requires a low internal high-potential side power supply voltage due to a decrease in breakdown voltage due to miniaturization of MOS. An example in which an ECL interface DRAM is configured taking these conditions into consideration will be described below. 5 to 7 are diagrams showing circuit blocks of an embodiment in which the embodiment of FIG. 1 is applied to an ECL interface DRAM. In these figures, ■ is an input circuit block mainly consisting of a bipolar current switch, K is a circuit block that includes memory cells and through which current flows only during charging and discharging, such as a decoder and a word driver, and 0 is a bipolar circuit block like the circuit. This is an output circuit block mainly consisting of a current switch. Note that power supply to I and O may be performed by providing an on-chip voltage limiter as necessary. In the embodiment shown in FIG. 5, dedicated power supply pads are provided for each of blocks I, O, T, and S. By using such a configuration, not only the stable operation of the circuit block S that generates and compares the reference voltage can be achieved, but also the circuit block I, which is mainly composed of a bipolar current switch through which a constant current flows, can also be used for charging and discharging. Circuit block K where current flows only when
Stable operation is achieved without being affected by power supply noise. In the embodiment shown in FIG. 5, both circuit blocks I and 0 are mainly bipolar current switches through which a constant current flows. If power is supplied to circuit blocks with the same characteristics from the same power supply pad as shown in FIG. 6, the number of power supply pads can be reduced and the features of the embodiment shown in FIG. 5 can also be obtained. . However, due to limitations in the number of pins of the package or layout limitations, it may not be possible to provide as many power supply pads as shown in FIGS. 5 and 6. In this case, the power for the circuit block S that generates and compares the reference voltage according to the present invention is supplied only from a dedicated power supply pad, and the power for the other blocks I, T(K), and O is supplied from a common power supply pad. The configuration shown in FIG. 7, which is supplied from In this configuration, for example, current is first supplied from a common power supply pad to circuit blocks I and O through which a constant current flows, and then current is supplied via output transistor T to circuit block K through which current flows only during charging and discharging. It's good to do that. By doing this, the present invention not only has the feature of being able to stably generate and compare reference voltages, but also
The circuit blocks I and O through which a constant current flows can also operate stably, resulting in stable operation as a whole. In actual LSIs, the configuration of the embodiment shown in FIG. 7 is often adopted due to the limitation of the number of pins of the package, but by using the present invention in the above-mentioned configuration, the same stability as that of the embodiments of FIGS. 5 and 6 is achieved. can accomplish the action. FIG. 8 is a diagram showing main circuits when the embodiment of FIG. 7 is specifically applied to a DRAM. In this figure, ■ is an input circuit block of the ECL interface, and one of the address buffer circuits is shown here as an example. K is a circuit block through which current mainly flows only during charging and discharging, and here it includes a decoder circuit PD, a word driver WD, a memory cell array M, a write amplifier RA in the memory cell array, and a Y selection signal applied to the terminal YS. MO8 differential circuit (MolHM 0
21 MD, IM o 4 ), etc. are shown for one data line pair. W is a word line, and D and /D are data lines. DC is a common data line which is the output of the direct sense amplifier. Chip enable signal /CE is connected to terminal C1.
A signal voltage generated from is applied. ○ is an output circuit block, in which a preamplifier circuit amplifies the current signal of the common data line DC and transmits it to the data bus line DB, and a current signal of the data bus line Da is DOUT.
It shows the main amplifier circuit that converts the signal. Terminal M
A signal voltage is applied to A for selecting which preamplifier if there are a plurality of preamplifiers, and a signal voltage for setting the output to a low level during standby is applied to the terminal 10E1. Although Vco is omitted in FIGS. 5 to 7, it is a power supply pad for the DoU transistor described in the prior art. Further, the MOS whose gate is connected to the terminal Va is a current source MOS. The on-chip voltage limiter has three types of internal voltage terminals Vt,
x + VE2. Different voltages are generated at Vt, . S circuit is a circuit for generating and comparing a reference voltage for terminal VL circuit, T1 is its output transistor, S2. T2 and S,,T, are similar circuits for V Let vt,3, respectively. Here, for example, a bandgap generator or the like in the SZI may be shared. Although omitted in Fig. 8, terminals Vt, □ and terminal v
E □t V L2 and VE2. It is desirable to provide a bypass capacitor between VL3 and VE as shown in FIG. 1 to alleviate power supply noise. According to this embodiment, the power supply for the circuit block S tsztsa that generates and compares the reference voltage in the on-chip voltage limiter is supplied from the dedicated power supply pad V C1t V El, so that the output transistor T1. Stable operation can be achieved without being affected by power supply noise due to the circuit block K through which current flows only during charging and discharging, which is supplied from T, ,T. Also,
Since the voltages applied to the terminals Vc, VR□, etc. are also required to be stable, it is preferable to generate them in a circuit supplied with power from Vcm and VE. The purpose of the present invention is to supply power to a circuit that generates and compares a reference voltage in an on-chip voltage limiter from a dedicated power supply pad, thereby stabilizing it without being affected by power supply noise caused by a circuit block through which current flows only during charging and discharging. The purpose is to plan the action. This is broadly applied to dividing an LSI into multiple circuit blocks, and for circuit blocks that charge and discharge particularly large load capacities, or circuit blocks that require a particularly stable power supply voltage, to have a dedicated power supply separate from other normal circuits. This can be said to be aimed at achieving stable operation with a configuration in which power is applied from the pad. FIG. 9 shows an embodiment in which the concept of the present invention is expanded in this way. DRAM is used as an example. In Figure 9, the power supply bonding pads (Vccp, VCCM, VCCRI VC
COIVsspy VssMy VSSR, VSSO)
The following shows how to apply power supply voltage to each circuit block. In addition, there are &Nte Vccp, V outside the package.
ccM* VCCF#v cco is connected to the positive power supply Vcc, V
ssp+ VssMy VSSF, Vsso are connected to the negative power supply Vss. For TTL interface, normally Vcc = 5 V, Vss = OV, E
For CL interface, usually Vcc=OV, Vss
=-5.2V. Block M is a memory cell array block, and the current for rewriting and refreshing memory cells is set to Vcc.
Apply from M, V ssM. High-speed, large-capacity DRAM
VCCM, VSS
Since a large noise voltage is induced in the circuit, current is supplied from a dedicated bonding pad to prevent other circuits from malfunctioning. Block F is a reference voltage generation circuit block, which includes a reference voltage generation circuit for an on-chip voltage limiter, a reference voltage generation circuit for an input/output buffer of an ECL interface, and a constant current source drive voltage generation circuit. These are applied from dedicated bonding pads in order to supply a stable power supply voltage V CICF t V ssp. In addition, in an analog/digital mixed type LSI, an analog circuit is also included in this circuit block. Block O is an output circuit block. Even when charging and discharging the output load capacity at high speed, the power supply voltage V c co +V
Since a large noise voltage is induced in sso, it is also applied to these from dedicated bonding pads. Also, among the output circuit blocks that accurately control the output level such as the ECL output, stable V CCF and V SSF should be supplied to the current switch circuit for determining the output level, excluding the DoUT transistor. . The block P is another peripheral circuit block including an address buffer, a decoder, a word driver, a main amplifier, a control circuit, and the like. This block does not require special stability, but in order to prevent large noise voltages from being applied to other blocks, it is supplied from a dedicated bonding pad as Vccp+Vssp, and the previously mentioned VccM,
V CCF m V cco + V SSM 1Vs
Separate from s+-y Vsso. With the above configuration, power can be applied to circuit blocks that charge and discharge large load capacities, or circuit blocks that require a particularly stable power supply voltage, from a dedicated power supply pad separately from other normal circuits. , the influence of noise caused by other circuit blocks can be suppressed. 10 and 11 show a method of wire bonding from the bonding pad to the lead frame of the package. Here, in order to make the wiring delay on the chip isotropic, it is necessary to make the wiring delay on the chip isotropic.
87I S SCC, Digest of Tec
As shown in Hnical Papers, p. 316), the placement of the bonding pads is central. FIG. 10 shows a method of wiring each bonding pad to a different lead frame, and FIG. 11 shows a method of wiring from a plurality of bonding pads to a common lead frame. Although the power supplies are more completely isolated in FIG. 10, the disadvantage is that the number of pins on the package increases. The case shown in FIG. 11 has the advantage that the number of pins on the package can be reduced, although it is somewhat prone to noise. Note that in high-speed DRAMs, noise due to the inductance of bonding wires and packages becomes a problem. As a solution to this problem, wireless bonding methods such as the flip-chip method have been proposed. This is a method in which solder bumps are formed on the electrode portions of the chip in advance during the wafer process, and the solder bumps are aligned face-down with the conductor pattern of the substrate and soldered. By combining this wireless bonding method with the present invention, a more stable RAM can be obtained. The embodiments of the present invention have been described above using DRAM as an example.
The present invention uses an on-chip voltage limiter to apply to other SRAMs and EPRs that have circuit blocks through which current flows only during charging and discharging.
It can be widely applied to memory LSIs and logic LSIs such as OM and EEPROM.

【Effect of the invention】

In the present invention, in the on-chip voltage limiter, the power supplies of the reference voltage generation circuit block and comparison circuit block and the power supply of the output transistor are separated and supplied from separate power pads, so that a large transient current flows through the output transistor. However, since current is supplied to the reference voltage generation circuit block and comparison circuit block from separate power supply pads, they can operate stably. Further, as a result, the generation of the reference voltage and the control of the output transistor can be performed well, so that the desired voltage and current can be stably supplied from the internal power supply terminal, and the entire LSI can operate stably.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing a first embodiment of the present invention;
2 and 3 are diagrams showing other embodiments of the present invention in which the power transistors in FIG. 1 are constructed with MOS, and FIG. 4 is a diagram showing a concrete example of the reference voltage generation circuit and comparison circuit in FIG. The circuit diagrams shown in FIGS. 5 to 7 are plan views showing the configuration of a power supply bat when the present invention is applied to an LSI with an ECL interface, and FIG. 8 is a concrete diagram of the DRAM circuit in the configuration of FIG. 7. 9 is a plan view showing the configuration of a power supply pad when the concept of the present invention is expanded, and FIG. 10 is a circuit diagram shown in FIG.
FIG. 11 is a plan view showing an example of wire bonding. Explanation of symbols F...Reference voltage generation circuit block A...Control circuit block T...Output transistor K...Circuit block C where current flows only during charging and discharging...
・Bypass capacitor Is...Standby current source Vc~■c4...High potential power supply pad VE1~■E4
...Low potential power supply pad E...Input circuit block O...Output circuit block PD...Decoder WD...Word driver M...Memory cell array D and /D...Data line DC...・Common data line DB... Data bus diagram ~ Figure η

Claims (1)

[Claims] 1) A first circuit that supplies an internal power supply voltage different from the external power supply voltage to the fourth circuit group, a second circuit that generates a reference voltage, and the reference voltage and the voltage of the internal power supply terminal. 1st compared with
a third circuit for controlling a circuit, at least one of a bonding pad for supplying power voltage to the first circuit and a bonding pad for supplying power voltage to the second and third circuits; A semiconductor device characterized by having a separate pad. 2) The semiconductor device according to claim 1, wherein the first circuit is constructed using a bipolar transistor. 3) The semiconductor device according to claim 1 or 2, wherein the second circuit is constructed using a bandgap generator of bipolar transistors. 4) The semiconductor device according to claim 1, 2, or 3, characterized in that it includes a memory cell composed of a MOS transistor. 5) Claims 1, 2, or 3, characterized in that the bypass capacitor inserted between the internal power supply terminal and the external power supply terminal is constituted by a gate-channel capacitance of a MOS transistor. Or the semiconductor device according to item 4. 6) The semiconductor device according to claim 5, wherein the MOS transistor constituting the bypass capacitor is of a depression type. 7) Claim 6, characterized in that the channel region of the depletion type MOS transistor is formed before the gate layer of the MOS is formed, and is formed in a well region of the same conductivity type layer as the source and drain regions. The semiconductor device described.